- Fix _try_ltspice_generation() to use spicelib.simulators.ltspice_simulator.LTspice
instead of the abstract Simulator base class (which always returned unavailable)
- Use LTspice.create_netlist() instead of Simulator.run() for correct netlist generation
- Add --ltspice-exe CLI option to specify LTspice binary path
- Add --bom flag for component BOM CSV output (works on any parse completeness)
- Add --bom-wiring flag for wiring BOM CSV from mapped output
- Add real 1002A.asc demo circuit and pre-generated .net as test fixtures
- Add @pytest.mark.ltspice marker for tests requiring LTspice binary
- Bump version to 2026.2.14
Layered graph drawing approach to minimize cable crossings:
- Layer assignment via BFS from external connectors (J*, TP*, P*)
- Barycenter ordering (forward + backward sweep) within each layer
- Connection orientation: earlier connector always on the left
- Pin reordering: weighted average neighbor position groups pins
by destination, reducing within-connector crossings
- Connection sorting: shorter (adjacent-pair) connections first
Fixes from Apollo safety review:
- Explicit ValueError on pin remapping failures (was silent KeyError)
- Weighted pin averaging for star topology (GND shared across modules)
- Fully deterministic sort keys for reproducible output
- Documented closure capture pattern in loop sort keys
C1: Port count mismatch now emits ERROR to stderr and marks
unconnected ports as __UNCONNECTED_<name>__ (never silent)
C2: Single-module pin mapping built in lockstep — cable_wires
always matches header_pins length, warns on unmappable nets
C3: VSS removed from is_power_net (it's ground per CMOS convention),
dead _POWER_PATTERN regex replaced with _KNOWN_NET_PATTERN
C4: apply_filters dead computation removed, docstring clarifies
that net-level filtering is a mapper concern
I3: WireViz render catches (ValueError, TypeError, OSError) with
diagnostic context instead of bare Exception
I5: Invalid --format flags now warn and error instead of silently
falling through to defaults
I6: Model/value heuristic warns on stderr when it triggers, since
signal names like ALERT or DATA could be misidentified
New tests: VSS classification, port count mismatch (C1), model/value
heuristic warning (I6), duplicate refs (S3), empty subcircuit (S2),
full pipeline determinism across 3 runs (S1)
115 tests pass, ruff clean
- Use CalVer dot notation (2026.2.13) for PEP 440 compliance
- Filter pinlabels for top-level components when ground/power hidden
- Fix unused variables, long lines, import ordering (ruff clean)
- Use StrEnum for PinDirection (Python 3.11+)
- Add .gitignore and README.md
- All 105 tests pass including WireViz roundtrip validation
