spice2wireviz

History

Ryan Malloy b9154e851b Address all critical and important findings from safety review

C1: Port count mismatch now emits ERROR to stderr and marks
    unconnected ports as __UNCONNECTED_<name>__ (never silent)
C2: Single-module pin mapping built in lockstep — cable_wires
    always matches header_pins length, warns on unmappable nets
C3: VSS removed from is_power_net (it's ground per CMOS convention),
    dead _POWER_PATTERN regex replaced with _KNOWN_NET_PATTERN
C4: apply_filters dead computation removed, docstring clarifies
    that net-level filtering is a mapper concern

I3: WireViz render catches (ValueError, TypeError, OSError) with
    diagnostic context instead of bare Exception
I5: Invalid --format flags now warn and error instead of silently
    falling through to defaults
I6: Model/value heuristic warns on stderr when it triggers, since
    signal names like ALERT or DATA could be misidentified

New tests: VSS classification, port count mismatch (C1), model/value
heuristic warning (I6), duplicate refs (S3), empty subcircuit (S2),
full pipeline determinism across 3 runs (S1)

115 tests pass, ruff clean

2026-02-13 01:34:30 -07:00

fixtures

Initial project structure for spice2wireviz

2026-02-13 01:24:41 -07:00

__init__.py

Initial project structure for spice2wireviz

2026-02-13 01:24:41 -07:00

test_cli.py

Fix linting issues and ground/power filtering in inter-module mapper

2026-02-13 01:27:45 -07:00

test_filter.py

Fix linting issues and ground/power filtering in inter-module mapper