Ryan Malloy c2197f6fe6 Add star-topology layout optimization for single-module diagrams ...

Three-pass optimization eliminates cable crossings:
1. Order boundary components by average header pin position
2. Regroup header pins by boundary component (reduces inter-cable crossings)
3. Reorder boundary component pins to parallel header (eliminates within-cable
   crossings)

Safety hardening from Apollo review:
- Duplicate header pin deduplication (prevents silent mapping corruption)
- Connection structure validation at entry
- Fan-out averaging for component pins connected to multiple header pins
- Explicit ValueError on pin remapping failures with diagnostic context

145 tests passing (was 130).

2026-02-13 03:07:50 -07:00

..

fixtures

Initial project structure for spice2wireviz

2026-02-13 01:24:41 -07:00

__init__.py

Initial project structure for spice2wireviz

2026-02-13 01:24:41 -07:00

test_cli.py

Fix linting issues and ground/power filtering in inter-module mapper

2026-02-13 01:27:45 -07:00

test_filter.py

Fix linting issues and ground/power filtering in inter-module mapper

2026-02-13 01:27:45 -07:00

test_inter_module.py

Add Sugiyama-lite layout optimization for inter-module diagrams

2026-02-13 02:01:06 -07:00

test_netlist_parser.py

Address all critical and important findings from safety review

2026-02-13 01:34:30 -07:00

test_roundtrip.py

Address all critical and important findings from safety review

2026-02-13 01:34:30 -07:00

test_single_module.py

Add star-topology layout optimization for single-module diagrams

2026-02-13 03:07:50 -07:00

test_yaml_emitter.py

Initial project structure for spice2wireviz

2026-02-13 01:24:41 -07:00