Ryan Malloy
95ed08866c
- Gate model/value heuristic output behind --verbose/-v flag (quiet by default) - Add wireviz>=0.4 as dev dependency for roundtrip render tests - Generate SVG/PNG diagram renders for inter_module, single_module, hierarchical - Embed rendered diagrams in README with layout optimization callout
363 lines
9.9 KiB
Markdown
363 lines
9.9 KiB
Markdown
# spice2wireviz
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Convert LTspice SPICE netlists to WireViz wiring diagrams.
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## What it does
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`spice2wireviz` reads SPICE netlist files (`.net`, `.cir`, `.sp`) and LTspice schematics (`.asc`) and generates [WireViz](https://github.com/wireviz/WireViz) YAML that documents the physical wiring: connectors, test points, and inter-module cables.
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Two operating modes:
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- **Single module** -- External interface of one subcircuit (its connectors, test points, port interface)
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- **Inter-module** -- How multiple subcircuits/boards connect to each other
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It also produces **Bill of Materials** output as CSV, and includes layout optimization to minimize cable crossings in rendered diagrams.
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## Install
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```bash
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uv tool install spice2wireviz
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# or
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pip install spice2wireviz
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```
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For `.asc` file metadata extraction (optional):
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```bash
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pip install spice2wireviz[asc]
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```
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## Quick start
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```bash
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# Inter-module wiring (auto-detected from top-level X instances)
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spice2wireviz top_level.net -o wiring.yml
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# Single module external interface
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spice2wireviz design.net -s amplifier_board -o amp.yml
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# Render to SVG/PNG/HTML (requires WireViz installed)
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spice2wireviz design.net -o wiring.yml --render --format sph
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# Component bill of materials
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spice2wireviz design.net --bom
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# Wiring bill of materials (cables, wire counts, endpoints)
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spice2wireviz top_level.net --bom-wiring
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```
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## Rendered diagrams
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### Inter-module wiring
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How multiple boards/modules connect to each other — power supply, amplifier, and I/O board with shared power and signal routing:
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### Single-module interface
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External interface of one subcircuit — the amplifier board's connectors and test points radiating from a central port header:
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### Hierarchical system
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A complex multi-level system with voltage regulator, main board, sensor module, and external connectors:
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These diagrams are generated automatically by piping `spice2wireviz` output through WireViz (`--render` flag). The layout optimizer minimizes cable crossings — notice how parallel wires between the same module pair are bundled into multi-wire cables.
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## Output examples
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### Input: SPICE netlist
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A multi-board system with power supply, amplifier, and I/O board:
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```spice
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.subckt power_supply VCC GND
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J1 AC_IN AC_GND AC_INLET
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.ends power_supply
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.subckt amplifier VIN GND VOUT
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J1 VIN GND INPUT_CONN
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TP1 VOUT
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.ends amplifier
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.subckt io_board SIG_IN SIG_OUT GND CTRL
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J1 SIG_IN SIG_OUT DB9_CONN
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J2 CTRL GND CTRL_CONN
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.ends io_board
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* Top-level instantiation
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X1 VCC GND power_supply
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X2 VCC GND AUDIO_OUT amplifier
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X3 AUDIO_OUT CTRL_SIG GND ENABLE io_board
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* Top-level connectors
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J_CHASSIS GND EARTH chassis_gnd
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TP_VCC VCC
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```
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### Output: Inter-module WireViz YAML
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```bash
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spice2wireviz multi_board.net
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```
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```yaml
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metadata:
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title: 'Wiring diagram: multi_board'
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source: multi_board.net
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generator: spice2wireviz 2026.2.14
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connectors:
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J_CHASSIS:
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type: chassis_gnd
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pinlabels:
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- EARTH
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- GND
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notes: 'SPICE ref: J_CHASSIS'
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TP_VCC:
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type: TP
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style: simple
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pinlabels:
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- VCC
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notes: 'SPICE ref: TP_VCC'
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X1:
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type: power_supply
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pinlabels:
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- VCC
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- GND
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notes: 'SPICE instance: X1 (power_supply)'
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X2:
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type: amplifier
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pinlabels:
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- VIN
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- GND
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- VOUT
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notes: 'SPICE instance: X2 (amplifier)'
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X3:
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type: io_board
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pinlabels:
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- GND
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- SIG_IN
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- SIG_OUT
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- CTRL
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notes: 'SPICE instance: X3 (io_board)'
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cables:
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W1:
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colors:
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- BK
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wirelabels:
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- GND
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W3:
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colors:
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- RD
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wirelabels:
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- VCC
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W5:
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category: bundle
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colors:
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- BK
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- RD
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wirelabels:
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- GND
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- VCC
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W8:
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wirecount: 1
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wirelabels:
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- AUDIO_OUT
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connections:
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- - TP_VCC: 1
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- W3: 1
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- X1: 1
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- - X1: [2, 1]
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- W5: [1, 2]
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- X2: [2, 1]
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- - X2: 3
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- W8: 1
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- X3: 2
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```
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Every connector includes a `notes` field tracing back to the original SPICE reference or instance. Ground wires are colored black (`BK`), power wires red (`RD`). Parallel wires between the same module pair are grouped into multi-wire cables (like `W5` above).
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### Output: Single-module WireViz YAML
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```bash
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spice2wireviz simple_board.net -s amplifier_board
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```
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```yaml
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connectors:
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amplifier_board:
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type: Module Interface
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pinlabels:
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- VIN
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- GND
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- VOUT
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- SIGNAL_IN
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notes: 'SPICE subcircuit: .subckt amplifier_board'
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J1:
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type: PWR_CONN
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pinlabels:
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- VIN
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- GND
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J2:
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type: SIG_CONN
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pinlabels:
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- VOUT
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- SIGNAL_IN
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TP1:
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type: TP
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style: simple
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pinlabels:
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- N001
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cables:
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W_J1:
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category: bundle
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colors: ['', BK]
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wirelabels: [VIN, GND]
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W_J2:
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category: bundle
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wirecount: 2
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wirelabels: [VOUT, SIGNAL_IN]
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connections:
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- - amplifier_board: [1, 2]
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- W_J1: [1, 2]
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- J1: [1, 2]
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- - amplifier_board: [3, 4]
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- W_J2: [1, 2]
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- J2: [1, 2]
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```
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Single-module mode generates a central "module header" connector representing the subcircuit's port interface, with star-topology cables radiating out to each boundary component (J*, TP*, P*).
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### Output: Component BOM
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```bash
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spice2wireviz simple_board.net --bom
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```
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```csv
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Reference,Prefix,Value,Pins,Subcircuit,Attributes
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J1,J,PWR_CONN,2,amplifier_board,
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J2,J,SIG_CONN,2,amplifier_board,
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TP1,TP,,1,amplifier_board,
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```
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Component BOM lists all boundary components (connectors, test points) with their reference, value, pin count, and which subcircuit they belong to. Works even on `.asc` files without connectivity data.
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### Output: Wiring BOM
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```bash
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spice2wireviz multi_board.net --bom-wiring
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```
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```csv
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Cable,Wirecount,Nets,From,To
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W1,1,GND,J_CHASSIS,X1
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W3,1,VCC,TP_VCC,X1
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W5,2,"GND, VCC",X1,X2
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W6,1,GND,X1,X3
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W8,1,AUDIO_OUT,X2,X3
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```
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Wiring BOM lists every cable with wire count, net names, and connected endpoints. Useful for generating cut lists and wire pull schedules.
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## Inspection commands
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Preview what's in a netlist before generating diagrams:
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```bash
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# List subcircuit definitions
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$ spice2wireviz multi_board.net --list-subcircuits
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amplifier: ports=[VIN, GND, VOUT], boundary_components=2
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io_board: ports=[SIG_IN, SIG_OUT, GND, CTRL], boundary_components=2
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power_supply: ports=[VCC, GND], boundary_components=1
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# Dry run (connector/cable/connection counts)
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$ spice2wireviz multi_board.net --dry-run
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Mode: inter
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Connectors: 5
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Cables: 5
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Connection sets: 5
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Connector names: J_CHASSIS, TP_VCC, X1, X2, X3
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```
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## Filtering
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Cherry-pick what appears in the diagram:
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```bash
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--include-prefixes J,TP # Only these component types (default: J,TP,P,X)
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--exclude-prefixes X # Hide subcircuit modules
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--exclude-refs X3,J_DEBUG # Hide specific references
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--include-nets "SIG_*" # Glob patterns for net names
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--exclude-nets "*_DEBUG" # Exclude debug nets
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--no-ground # Hide GND connections
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--no-power # Hide VCC/VDD connections
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--no-group # Don't bundle parallel wires into multi-wire cables
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```
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## LTspice .asc support
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LTspice `.asc` schematic files are supported with tiered netlist resolution:
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1. **Companion netlist** (automatic) -- If a `.net`, `.cir`, or `.sp` file exists alongside the `.asc` (same basename), it's used for full connectivity. LTspice generates these automatically when you run a simulation.
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2. **LTspice generation** (opt-in) -- Pass `--generate-netlist` to invoke LTspice and produce a `.net` file. Use `--ltspice-exe` to specify the LTspice binary path if it's not auto-detected.
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3. **Metadata only** -- Without a netlist, only component refs/values are available. Diagram generation is blocked, but `--list-components` and `--bom` still work.
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```bash
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# .asc with companion .net in the same directory
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spice2wireviz schematic.asc -s amplifier_board -o amp.yml
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# No companion .net -- invoke LTspice to generate one
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spice2wireviz schematic.asc --generate-netlist -o wiring.yml
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# Specify LTspice binary path (Linux/wine, macOS, Windows)
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spice2wireviz schematic.asc --generate-netlist --ltspice-exe /path/to/ltspice
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# Component BOM from .asc (no .net required)
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spice2wireviz schematic.asc --bom
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```
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## Layout optimization
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Both mappers apply layout optimization to minimize cable crossings in rendered diagrams:
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- **Inter-module**: Sugiyama-lite layered graph drawing -- external connectors are placed at the left edge, modules are layered by BFS distance, barycenter ordering reduces crossings, and pins are reordered to group connections to the same neighbor.
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- **Single-module**: Star topology optimization -- boundary components are ordered by their connection pattern to the module header, header pins are grouped by target component, and pin sequences are parallelized.
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This is automatic and requires no configuration.
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## How it works
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```
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.net/.cir/.sp ─────┐
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├─→ Parser ─→ ParsedNetlist ─→ Filters ─→ Mapper ─→ WireViz YAML
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.asc (+ companion) ┘ │ │
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│ └─→ Wiring BOM CSV
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└─→ Component BOM CSV
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```
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The parser extracts subcircuit definitions (`.subckt`), instances (`X*`), and boundary components (`J*`, `TP*`, `P*`) from SPICE netlists. Filters remove unwanted elements. The mapper converts the remaining structure into WireViz connector/cable/connection format. The emitter serializes to deterministic YAML (byte-identical output for identical input) or CSV.
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## Development
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```bash
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uv sync --extra dev --extra asc
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uv run pytest # 194 tests
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uv run ruff check src/ tests/
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```
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LTspice integration tests require LTspice installed and are marked:
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```bash
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uv run pytest -m ltspice # Run only LTspice tests
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uv run pytest -m "not ltspice" # Skip LTspice tests (CI default)
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```
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## Repository
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[git.supported.systems/warehack.ing/spice2wireviz](https://git.supported.systems/warehack.ing/spice2wireviz)
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