4 Commits

Author	SHA1	Message	Date
Ryan Malloy	95ed08866c	Add verbose flag, WireViz dev dep, and rendered diagram examples ... - Gate model/value heuristic output behind --verbose/-v flag (quiet by default) - Add wireviz>=0.4 as dev dependency for roundtrip render tests - Generate SVG/PNG diagram renders for inter_module, single_module, hierarchical - Embed rendered diagrams in README with layout optimization callout	2026-02-13 09:19:18 -07:00
Ryan Malloy	fd822e07ce	Expand README with output examples, BOM docs, architecture diagram ... Add real YAML/CSV output examples generated from test fixtures, document --bom/--bom-wiring flags, layout optimization, inspection commands, and LTspice --ltspice-exe option.	2026-02-13 07:09:53 -07:00
Ryan Malloy	08c92bfefb	Add tiered .asc parser with companion netlist resolution ... Implement three-tier resolution for LTspice .asc schematic files: 1. Companion netlist - finds .net/.cir/.sp beside the .asc (automatic) 2. LTspice generation - invokes LTspice binary (opt-in via --generate-netlist) 3. Metadata-only fallback - extracts component refs/values without connectivity Safety: DataCompleteness enum forces callers to check completeness. CLI blocks diagram generation on METADATA_ONLY with clear remediation. Metadata enrichment is additive-only with protected field guards. Also: update project URLs to Gitea, add .asc usage docs to README, fix pre-existing ruff warning in test_single_module.py.	2026-02-13 04:59:03 -07:00
Ryan Malloy	eb3ad60bd1	Fix linting issues and ground/power filtering in inter-module mapper ... - Use CalVer dot notation (2026.2.13) for PEP 440 compliance - Filter pinlabels for top-level components when ground/power hidden - Fix unused variables, long lines, import ordering (ruff clean) - Use StrEnum for PinDirection (Python 3.11+) - Add .gitignore and README.md - All 105 tests pass including WireViz roundtrip validation	2026-02-13 01:27:45 -07:00