Ryan Malloy
5252d1d73c
Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint, 3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep. NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference manual. Cortex-M4 96MHz MCU running the G2 firmware. Reyax RYS352A GPS module: datasheet and PAIR command guide. GPS receiver on the G2 board (used for auto-location/satellite lookup). All extracted as markdown + page images + vector SVGs for LLM context. Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.
307 lines
46 KiB (Stored with Git LFS)
XML
307 lines
46 KiB (Stored with Git LFS)
XML
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<text xml:space="preserve" transform="matrix(1 0 0 1 150 54)" font-size="12" font-family="HelveticaLTStd" font-weight="bold"><tspan y="10.11719" x="15.3 22.632 29.304 36.636 39.972 46.644 49.980005 56.652006 63.324007 67.32001 73.992008 80.664 93 102.996 111.66 120.996 124.332 135 142.332 149.664 156.336 163.008 166.344 173.676 177.672 181.008 188.34 195.672 202.344 207.012 213.68399 217.68 221.01599 228.34799 235.68 239.01599 243.012 249.68399 257.016 264.348 268.344 271.68 279.012 286.344 293.016 300.348">Table 25-18.MCG modes of operation (continued)</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 56.5 76)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="7.83789" x="1.998 9.495001 14.994001 20.493002">Mode</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 157.3 76)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="7.83789" x="1.998 8.496 13.500001 18.504002 23.508004 27.009003 29.511004 35.010004 38.007005 40.509004 46.008005">Description</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 56.25 92)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="0 6.0030004 10.503 15.507001 20.511002 25.011002 29.511002 34.515005 39.519006 42.021005 47.025007 52.029008 58.527009 61.029008 67.032009 72.036 78.534008 83.538">Bypassed Low Power</tspan><tspan y="18.83789" x="0 2.5020004 7.506001 10.008001 15.012002 18.009003 23.013005 28.017006 30.015007 32.517007 35.514009 41.517007 46.521009 52.52401 55.02601">Internal (BLPI)</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 157.05 92)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="0 6.0030004 10.503 15.507001 20.511002 25.011002 29.511002 34.515005 39.519006 42.021005 47.025007 52.029008 58.527009 61.029008 67.032009 72.036 78.534008 83.538 86.535 89.037 91.539 96.543 99.045 104.048999 107.046 112.049999 117.05399 119.051998 121.55399 124.550998 130.554 135.558 141.561 144.063 147.06 149.562 157.05899 162.06299 167.06699 172.07099 174.57299 176.57099 181.07099 183.57299 188.57698 193.58098 196.08298 201.08698 204.08397 209.08797 214.09197 216.59397 223.09197 228.09597 233.09996 238.10396 240.60596 245.60996 247.60796 249.60596 252.10796 254.60996 259.61396 264.61796 267.11997 269.62199 274.62599 276.62397 278.62196 283.62596 290.12394 292.12193 297.12593 302.1299 304.63194 309.13194 314.13594 319.13993 324.14393 326.1419 328.64393 330.6419 335.6459 340.6499 345.1499 347.65193 352.6559 357.1559 361.6559 366.6599 369.65693">Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur:</tspan><tspan y="24.23789" x="14.85 24.003 30.501002 35.505 38.007 44.505 49.509004 55.512 61.515 64.017 66.519 71.522998 73.520999 76.022998 80.522998 83.024997 88.02899 91.02599 96.02999 98.53199 105.02999 108.02699 110.024997 112.52699 115.02899 120.03299 125.03699 127.53899 130.04099 135.04499 137.54698 142.55098">•C1[CLKS] bits are written to 01</tspan><tspan y="40.63789" x="14.85 24.003 30.501002 35.505 38.007 40.509 47.007 53.010004 58.509004 64.512 67.014 69.516 74.52 76.518 79.02 81.521999 83.52 88.02 90.521999 97.02 100.017 102.015 104.517 107.019 112.022998 117.02699 119.52899 122.03099 127.03499 129.53699">•C1[IREFS] bit is written to 1</tspan><tspan y="57.037889" x="14.85 24.003 30.501002 35.505 38.007 44.010004 49.014005 54.018007 60.021005 62.523004 65.025 70.029 72.027 74.529 77.031 79.029 83.529 86.031 92.529 95.526 97.524 100.026 102.528 107.532 112.535999 115.037998 117.53999 122.54399 125.04599">•C6[PLLS] bit is written to 0</tspan><tspan y="73.43789" x="14.85 24.003 30.501002 35.505 38.007 43.011 49.014 51.516 54.017999 59.022 61.02 63.522 66.024 68.022 72.522 75.024 81.522 84.519008 86.517009 89.019008 91.521 96.525 101.529 104.031 106.533 111.536998 114.038997">•C2[LP] bit is written to 1</tspan><tspan y="99.83789" x="0 2.5020004 7.506001 10.008001 16.011002 21.015004 27.018004 29.520005 32.022005 39.519006 44.523008 49.527009 54.53101 57.03301 59.535009 67.032009 73.53001 80.532009 87.534008 94.032009 99.531009 106.02901 111.033008 117.036 119.538 121.536 126.036 128.53801 133.542 138.546 141.543 143.541 148.041 153.045 158.049 160.551 163.053 166.04999 171.05399 178.55098 181.05298 183.55498 188.55898 193.56298 196.06497 198.06298 203.06697 205.56897 210.57297 213.56996 218.57396 223.57796 225.57596 228.07796 231.07495 236.07895 238.58095 243.58495 246.58194 251.58594 256.58995 261.08995 266.09394 268.59596 273.09596 275.09394 280.09794 284.59794 289.09794 291.59996 294.10197 299.60096 304.60496 309.60896 312.11097 317.60997 322.61396 327.61796 330.11997 332.11796 336.61796 339.11997 344.12397 346.12196 350.62196 355.62596 360.62995 362.62794 367.63194 372.63594 375.13795 380.14195 385.14595">In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled and</tspan><tspan y="110.83789" x="0 6.0030004 11.007001 16.011002 18.513003 20.511002 25.011002 27.513003 32.517004 34.515005 39.015005 44.019006 49.023008 51.021009 56.02501 61.02901 63.53101 68.53501 73.03501 78.03901 83.04301 85.545009 87.54301 90.045009 92.547008 95.049 100.053 105.057 107.559 114.057 119.061 121.562999 127.565998 132.56999 137.57399 144.07199 149.07599 155.079 161.082 167.58 172.584 175.086 177.588 179.586 184.086 186.588 191.088 196.092 198.594 201.096 203.59799 208.60199 211.10399 216.10799">PLL is disabled even if the C5[PLLCLKEN0] is set to 1.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 56.25 210.5)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="0 6.0030004 10.503 15.507001 20.511002 25.011002 29.511002 34.515005 39.519006 42.021005 47.025007 52.029008 58.527009 61.029008 67.032009 72.036 78.534008 83.538">Bypassed Low Power</tspan><tspan y="18.83789" x="0 6.0030004 10.503 13.005001 18.009003 21.006003 26.010003 31.014004 33.012006 35.514005 38.511007 44.514009 49.51801 55.52101 61.52401">External (BLPE)</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 157.05 210.5)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="0 6.0030004 10.503 15.507001 20.511002 25.011002 29.511002 34.515005 39.519006 42.021005 47.025007 52.029008 58.527009 61.029008 67.032009 72.036 78.534008 83.538 86.535 89.037 95.04 99.54 102.042 107.046 110.043 115.047 120.050998 122.048999 124.550998 127.548 133.551 138.555 144.558 150.561 153.558 156.06 163.55699 168.56099 173.56499 178.56899 181.07099 183.06899 187.56899 190.07099 195.07498 200.07898 202.58098 207.58498 210.58197 215.58597 220.58997 223.09197 229.58997 234.59397 239.59796 244.60196 247.10396 252.10796 254.10596 256.10395 258.60597 261.10798 266.11198 271.11598 273.61799 276.12 281.124 283.12199 285.11997 290.12397 296.62196 298.61994 303.62394 308.62794 311.12995 315.62995 320.63395 325.63795 330.64195 332.63993 335.14195 337.13993 342.14393 347.14793 351.64793 354.14994 359.15394 363.65394 368.15394 373.15794 376.15495">Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur:</tspan><tspan y="24.23789" x="14.85004 24.00304 30.501042 35.505044 38.007043 44.505044 49.509046 55.512048 61.515047 64.017047 66.51904 71.52304 73.52104 76.02304 80.52304 83.02504 88.02904 91.02604 96.03004 98.532039 105.03004 108.02704 110.02504 112.52704 115.02904 120.033039 125.03703 127.53903 130.04103 135.04503 137.54703 142.55103">•C1[CLKS] bits are written to 10</tspan><tspan y="40.63789" x="14.85004 24.00304 30.501042 35.505044 38.007043 40.50904 47.007043 53.01004 58.50904 64.51204 67.01404 69.51604 74.520038 76.518039 79.020038 81.52203 83.520038 88.020038 90.52203 97.020038 100.01704 102.01504 104.51704 107.019039 112.02303 117.02703 119.52903 122.03103 127.03503 129.53704">•C1[IREFS] bit is written to 0</tspan><tspan y="57.037889" x="14.85004 24.00304 30.501042 35.505044 38.007043 43.011045 49.014047 51.516046 54.018045 59.022047 61.020048 63.522047 66.02405 68.02205 72.52205 75.02405 81.52205 84.51905 86.51705 89.01905 91.52105 96.52505 101.529048 104.031047 106.53304 111.53704 114.03904">•C2[LP] bit is written to 1</tspan><tspan y="83.43789" x=".00005054474 2.5020509 7.5060517 10.008052 16.011052 21.015053 27.018054 33.021055 35.523054 43.020055 48.024057 53.028059 58.03206 60.534059 63.036058 70.53306 77.03106 84.03306 91.03506 97.53306 103.03206 109.53006 114.53406 120.537059 123.039058 125.037059 129.53705 132.03905 137.04305 142.04705 145.04404 147.04204 151.54204 156.54604 161.55004 164.05204 166.55403 169.55103 174.55503 182.05202 184.55402 187.05602 192.06002 197.06401 199.56601 206.56801 212.57102 219.06902 225.07202 231.07503 236.07903 238.58103 243.58502 248.08502 250.58702 255.59102 258.588 263.592 268.596 270.594 273.096 276.09303 281.09703 283.59904 288.60304 291.60005 296.60404 301.60804 306.10804 311.11204 313.61405 318.11405 320.11204 325.11604 329.61604 334.11604 336.61805 339.12007 344.61906 349.62306 354.62705 357.12907 362.62806 367.63206 372.63606 375.13807 377.13606">In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is</tspan><tspan y="94.43789" x=".000080544738 5.0040814 7.0020816 11.502081 16.50608 21.510083 23.508084 28.512085 33.516088 36.018087 41.022089 46.02609 51.03009 53.53209 59.535089 64.539089 69.54308 72.04508 74.04308 78.54308 81.04508 86.04908 88.04708 92.54708 97.55108 102.55508 104.55308 109.557079 114.56107 117.06307 122.06707 126.56707 131.57108 136.57508 139.07707 141.07508 143.57707 146.07907 148.58107 153.58507 158.58907 161.09107 167.58907 172.59307 175.09506 181.09807 186.10207 191.10607 197.60407 202.60807 208.61107 214.61408 221.11208 226.11608 228.61808 231.12007 233.11808 237.61808 240.12007 244.62007 249.62407 252.12607 254.62807 257.13008 262.13407 264.63609 269.64009">disabled and PLL is disabled even if the C5[PLLCLKEN0] is set to 1.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 56.25 312.6)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="0 6.0030004 8.505001 13.509002">Stop</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 157.05 312.6)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="0 6.0030004 11.007001 13.509001 18.513 21.51 26.514 31.518002 34.02 40.518 45.522005 50.526006 55.530008 60.534009 65.03401 70.03801 73.03501 75.53701 78.03901 83.04301 88.047008 90.549 98.046009 104.54401 111.04201 113.54401 118.548007 123.552 126.054 131.058 134.055 138.555 141.05699 146.06099 148.56299 154.566 157.068 162.07199 167.07599 169.57799 174.07799 176.57999 181.58399 184.08599 189.08998 191.59198 194.09398 199.59297 204.59697 209.60097 212.10297 217.10697 222.11096 228.60897 233.61296 236.60996 239.11196 246.60895 251.61295 256.61695 261.62095 266.12095 268.62297 273.62696 276.62397 281.62797 284.12998 288.62998 293.63398 295.63197 300.63597 303.13798 307.63798 312.64198 317.64598 322.14598 324.14396 326.64598 328.64396 333.14396 335.64598 338.14799 343.64698 348.65098 351.64799 354.15 359.154 364.158 370.65599 375.65998">Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power</tspan><tspan y="18.83789" x=".00004 7.4970409 12.501041 17.505043 22.509045 25.011046 30.015046 34.515047 39.015047 41.013048 46.017049 51.02105 58.51805 63.522054 68.526058 71.02805 75.52805 78.03005 80.53205 85.03205 90.03605 95.04005 97.542049 100.044048 105.04804 110.05204 112.55404 117.05404 122.05804 127.062038 132.06604 134.56804 139.57204 142.56903 145.07103 147.57303 152.57703 157.58103 160.08303 162.58502 167.58902 172.59302 177.09302 181.59302 184.59001 186.58802 191.59201 196.59601 201.09601 203.598 208.602 213.606 220.104 222.606 230.103 235.107 240.111 245.11499 247.11299 252.11699 256.617 259.11903 264.12303 267.12004 272.12403 274.62605 279.12605 284.13005 289.13404 291.63606 293.63404 298.63804 303.64204 306.63905 311.64305 316.64704 319.14906 324.15306 329.15705 334.16105 336.66307 344.16007 350.65806 357.66007 360.16209 365.16609 370.17008 375.17408 380.17808 384.67808 386.67607 391.68006">mode assignments, see the chapter that describes how modules are configured and MCG behavior</tspan><tspan y="29.83789" x=".00004 5.0040409 10.008041 13.005041 15.003041 20.007042 25.011044 27.513045 33.516046 36.018045 41.022047 46.026048 48.528047 51.525049 56.52905 61.02905 66.03305 70.53305 75.53705 78.53405 83.03405 85.53605 88.03805 94.041049 99.045047 101.54704 106.55104 109.54804 111.54604 116.55004 121.55404 124.05604 130.05904 132.56104 137.56504 142.56903 145.07103 152.56803 157.57202 162.57602 167.58002 170.08202 172.58402 175.08602 180.09001 185.09401 187.59601 193.095 198.099 203.103 205.605 207.603 212.103 214.605 219.609 221.607 226.107 231.111 236.11499 238.11299 243.11699 248.12099 250.62299 253.12499 258.129 263.133 268.137 270.639 275.643 277.641 279.63899 282.141 289.638 296.136 303.138 305.64 310.14 312.138 317.142 321.642 326.142 328.644 333.144 335.142 340.146 345.15 350.154 352.15199 356.65199 359.154 364.158 367.155 372.159 374.661 379.161 381.66304 386.66703 389.16905 391.16703">during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static</tspan><tspan y="40.83789" x=".00004 5.0040409 9.504041 14.004041 19.008042 24.012043 26.514044 29.016045 31.014046 36.018049 38.520048 41.022047 46.026048 51.03005 53.532049 56.034048 61.038049 63.03605 65.03405 70.03805 76.53605 78.53405 83.53805 88.542049 91.044048 95.544048 100.54804 105.04804 110.05204">except in the following case:</tspan><tspan y="57.237894" x=".00004 7.4970409 13.995041 20.997042 27.000042 32.004045 37.008047 43.506048 48.510049 54.513048 57.015047 59.013048 63.513048 66.015048 71.01904 75.51904 78.02104 80.01904 84.51904 89.52304 92.02504 94.02304 99.02704 101.52904 108.02704 113.03104 116.02804 123.52504 128.52904 130.52704 133.02904 139.03205 141.53404 146.53804 151.54204 154.04404 161.54103 166.54503 171.54903 176.55303 179.05503 185.55303 190.55702 195.56102 200.56502 203.06702 209.07003 214.07402 219.07802 225.08103 230.58002 236.58303 243.08103 248.33702">MCGPLLCLK is active in Normal Stop mode when PLLSTEN=1</tspan><tspan y="73.63789" x=".00004 7.4970409 13.995041 20.997042 23.499043 29.997044 36.495046 41.499048 47.502046 50.004045 52.002046 56.502046 59.004045 64.00804 68.50804 71.01004 73.00804 77.50804 82.51204 85.01404 87.01204 92.01604 94.518039 101.01604 106.020038 109.01704 116.51404 121.518039 123.51604 126.018039 132.02104 134.52304 139.52704 144.53104 147.03304 154.53003 159.53403 164.53803 169.54203 172.04402 178.54203 183.54602 188.55002 193.55402 196.05602 201.06002 203.05802 205.05602 207.55802 210.06002 215.06401 220.06801 222.57 225.072 230.076 232.074 234.072 239.076 245.574 247.572 252.576 257.58003 260.08204 264.58204 269.58604 274.59004 279.59403 281.592 284.09403 286.092 291.096 296.1 300.6 303.10203 308.10603 313.11003 317.61003 322.614 330.11103 335.11503 337.61705 340.11906 343.11607 348.12007 353.12406">MCGIRCLK is active in Normal Stop mode when all the following conditions become true:</tspan><tspan y="90.037899" x="14.85006 24.003062 30.501063 35.505064 38.00706 40.50906 47.00706 53.505064 58.509065 64.51206 70.51506 77.01306 79.51506 82.01706 87.273059 89.775058">•C1[IRCLKEN] = 1</tspan><tspan y="106.4379" x="14.85006 24.003062 30.501063 35.505064 38.00706 40.50906 47.00706 53.010065 58.509065 64.51206 70.01106 76.01406 82.51206 85.01406 87.51606 92.772068 95.27406">•C1[IREFSTEN] = 1</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 157.05 437.6)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="7.83789" x=".00007 6.4980709 13.500071 18.999072 25.002072">NOTE:</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 192.13565 437.6)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="14.85007 24.00307 32.49907 37.50307 42.507074 47.511075 50.013074 55.017076 60.021078 62.523077 67.52708 70.52408 72.52208 77.52608 82.530078 85.032077 90.03607 95.04007 101.53807 104.04007 110.04307 115.047069 121.54507 126.549068 129.54607 132.04807 138.05107 140.55307 145.55707 150.56107 153.06307 160.56006 165.56406 170.56806 175.57205 180.07205 182.57405 185.57105 190.57505 195.57904 201.58205 204.08405 209.08805 212.08504 214.58704 220.59004 225.59404 231.59705 237.60005 240.59705 243.09905 245.60105 248.59804 253.60204 261.09904 263.60105 269.60404 275.60704 281.61003 284.11204 291.60905 296.61305 301.61705 306.62104 309.12306 311.62507 316.62907 321.63307 324.13508 329.13908 333.63908 335.63706 338.13908 340.64109 343.1431 348.1471">•When entering Low Power Stop modes (LLS or VLPS) from PEE mode, on exit the</tspan><tspan y="18.83789" x="24.00306 31.500061 37.998064 45.00006 47.50206 52.00206 54.00006 59.004064 63.504064 68.00406 70.50606 78.00306 83.00706 88.011058 93.01505 95.51705 97.51505 102.01505 104.51705 107.01905 112.02305 115.02005 119.52005 124.52405 129.52805 132.03005 134.53205 139.53604 142.03804 148.04105 154.04405 160.04706 162.54906 167.04906 169.04706 174.05106 178.55106 183.05106 185.55306 193.05005 198.05405 203.05805 208.06204 210.56404 213.06604 219.56404 224.56804 227.07004 233.56804 238.57204 244.57505 250.57805 253.08005 255.58205 260.58607 265.59007 270.59407 273.09608 279.09907 281.60108 288.09907 293.10307 299.10606 305.10905 310.60804 313.11006 315.61207 322.11006 324.10804 326.10603 328.104 330.60603 335.61003">MCG clock mode is forced to PBE clock mode. C1[CLKS] and S[CLKST] will be</tspan><tspan y="29.83789" x="24.00306 28.50306 33.50706 38.511064 41.01306 43.011064 48.015066 53.019067 56.016069 61.02007 66.02407 68.52607 71.02807 76.03207 78.534069 83.53806 85.536067 90.54006 95.54406 100.54806 103.05006 108.054058 113.05805 118.06205 120.56405 126.56705 129.06905 134.07305 141.07505 147.57305 153.57605 158.58005 161.08205 163.58405 168.58805 170.58605 173.08805 175.59004 182.08805 184.08605 186.08405 188.08205 190.58405 195.58805 200.59204 203.09404 207.59404 209.59204 214.59604 219.60004 222.59703 227.60103 232.60503 235.10703 241.60503 243.60303 246.10503 251.10903 256.11305 261.11705 263.61906 266.12107 270.62107 275.62507 278.12709 280.6291 282.62709 287.63108 292.63508 295.1371 301.14009 303.6421 308.6461 315.6481 320.6521 326.6551 331.6591 334.1611">configured to 2’b10 and S[LOCK0] bit will be cleared without setting S[LOLS0].</tspan><tspan y="46.237894" x="14.8500399 24.00304 32.49904 37.50304 42.507043 47.511045 50.013044 55.017045 60.021047 62.523046 67.52705 70.52405 72.52205 77.52605 82.530048 85.03204 91.530048 96.53404 99.531047 107.028049 112.03204 114.030048 116.53204 122.53504 125.03704 130.04105 135.04505 137.54705 145.04404 150.04804 155.05204 160.05603 162.55803 165.06003 168.05702 173.06102 180.55802 183.06002 189.06302 195.06603 201.06903 203.57103 211.06803 216.07202 221.07602 226.08002 228.58202 233.58602 238.59001 243.59401 246.09601 248.09401 250.59601 253.098 259.596 264.6 267.10203 273.105 278.109 283.113 289.116 294.615 300.61799 307.11598 312.11997 314.62199 319.878 324.882 327.384 329.88603 334.89 339.894 342.39604 347.40003 351.90003 353.898">•When entering Normal Stop mode from PEE mode and if C5[PLLSTEN0]=0, on exit</tspan><tspan y="57.237894" x="24.003029 26.50503 31.50903 36.51303 39.01503 46.51203 53.010034 60.01203 62.51403 67.01403 69.01203 74.01603 78.51603 83.01603 85.51803 93.01503 98.01903 103.023029 108.02702 110.52902 112.52702 117.02702 119.52902 122.03102 127.03502 130.03202 134.53202 139.53601 144.54001 147.042 149.544 154.548 157.05 163.05301 169.05602 175.05902 177.56102 185.05802 190.06201 195.06601 200.07 202.572 205.074 207.576 212.58 217.584 220.086 226.584 231.588 234.09 240.588 245.592 251.595 257.598 260.1 262.60203 267.60603 272.61003 277.614 280.11604 286.11903 288.62104 295.11903 300.12303 306.126 312.129 317.628 320.13 322.63203 329.13 331.128 333.12599 335.12397 337.62599 342.62998">the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will be</tspan><tspan y="68.23789" x="24.003069 28.503069 33.50707 38.51107 41.01307 43.01107 48.01507 53.019075 56.016077 61.020078 66.02408 68.52608 71.028079 76.032077 78.53407 83.53807 85.53607 90.54007 95.54407 100.548069 103.050067 108.05406 113.05806 118.06206 120.56406 126.567058 129.06906 134.07306 141.07506 147.57306 153.57607 158.58007 161.08206 163.58406 168.58806 170.58606 173.08806 175.59006 182.08806 184.08606 186.08406 188.08206 190.58406 195.08406 197.08206 202.08606 207.09006 210.08705 212.58905 219.08705 221.08506 223.58705 228.59105 233.59505 238.59905 241.10105 243.60305 248.10305 253.10704 255.60904 258.11106 260.10905 265.11305 270.11705 272.61906 278.62205 281.12406 286.12806 293.13008 298.13407 304.13706 309.14106 311.64308 314.14509 316.6471 319.1491">configured to 2’b10 and S[LOCK0] bit will clear without setting S[LOLS0]. If</tspan><tspan y="79.23789" x="24.003069 30.50107 35.50507 38.00707 44.01007 49.014074 54.018075 60.021074 65.52007 71.52307 78.02107 83.02507 85.52707 90.783069 95.78706 98.28906 100.79106 103.29306 108.29706 113.301059 115.803058 121.80605 124.30805 129.31206 136.31406 142.81206 148.81507 153.81906 156.32106 158.82306 163.82706 165.82506 168.32706 170.82906 177.32706 179.32506 181.32306 183.32106 185.82306 190.82706 195.83106 198.33306 200.83506 205.83905 210.84305 213.34505 215.84705 220.34705 222.34505 227.34905 232.35305 235.35004 240.35404 245.35803 247.86003 252.86403 257.86805 262.87205 265.37406 270.37806 275.38206 277.88407 282.88807 287.38807 289.38606 291.88807 294.39009 296.8921 301.8961 306.9001 309.4021 316.8991 323.3971 330.3991 332.90113 339.3991 341.3971 343.39509">C5[PLLSTEN0]=1, the S[LOCK0] bit will not get cleared and on exit the MCG will</tspan><tspan y="90.23789" x="24.0031 28.5031 33.5071 38.5111 41.0131 43.0111 48.015104 53.019105 58.023107 60.525106 63.027105 68.031108 70.533107 73.530109 78.5341 83.5381 86.0401 88.0381 93.0421 95.5441 101.5471 107.550098 113.55309 116.05509 123.55209 128.55609 133.56009 138.56409">continue to run in PEE mode.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.000017 555.9)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="0 5.0040009">1.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 69.12002 555.9)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="0 2.5020004 5.0040009 7.506001 12.510002 17.514004 20.016005 25.020005 28.017004 30.015004 35.019006 40.023008 42.525007 48.528009 53.53201 59.53501 66.03301 68.53501 76.03201 81.03601 86.04001 91.04401 93.546009 96.048007 103.545009 110.04301 117.045009 119.547008 124.551 129.55501 134.05501 136.557 139.059 144.063 146.565 151.569 156.573 159.075 163.575 168.579 173.583 176.08499 178.083 183.08699 188.09099 191.08798 196.09198 201.09598 203.59798 208.60198 213.60597 218.60997 221.11197 226.11597 231.11997 233.62197 238.62596 241.62296 244.12496 250.12796 255.13196 261.13496 267.13795 269.63996 277.13697 282.14097 287.14497 292.14897 294.65098 299.65498 302.65199 305.154 311.15699 316.16099 322.16398 324.666 327.168 334.665 339.669 344.673 349.677 352.17903 358.677 360.675 363.177 368.181 370.683 373.18504 378.18904 383.19303 385.69505 391.19404 396.19804 400.69804 403.20005 405.70207 408.20408 414.70207 421.20005 423.70207 428.20207 430.20005 435.20405 439.70405 444.20405 446.70606 451.20606 456.21006 458.20805 463.21205 467.71205 470.21406 475.21806">If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the Fast IRC clock selected</tspan><tspan y="18.83789" x="0 2.997 9.495001 14.4990019 17.001002 19.503003 26.001004 32.499006 38.502008 41.004007 46.260007 51.264009 54.26101 56.76301 59.265008 65.268009 67.770008 70.272 75.276 78.273 80.775 82.773 85.275 87.777 92.781 97.784999 100.286998 105.29099 108.287998 112.787998 115.28999 121.29299 126.29699 132.29999 138.79799 141.29999 148.79698 153.80098 158.80498 163.80898 166.31098 168.81298 175.31098 178.30797 180.30597 182.80797 187.81197 192.31197 194.81397 197.31597 202.31996 204.82196 209.82596 214.82996 219.32996 221.83196 226.83596 229.33795 231.83995 234.34195 239.34595 244.34995 246.85195 254.34894 260.84693 267.84895 270.35096 274.85096 279.85496 284.85896 287.36097 290.35798 295.36198 297.35997 299.86198 302.85899 307.86299 312.86698 314.86497 319.36497 321.86698 326.87098 329.86799 334.36799 336.87 339.372 344.376 349.38 351.88203 354.38404 358.88404 363.88804 368.89204 371.39405 375.89405 380.89805 385.90205 390.40205 395.40605 397.90806 402.91206 407.91606 410.41807 417.91508 424.41307 431.41508 433.91709 438.41709 440.41508 445.41908 449.91908 454.41908 456.92109 464.4181 469.4221 474.4261">(C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG clock mode</tspan><tspan y="29.83789" x="0 4.5 10.998001 12.996001 15.498001 19.998002 25.002003 27.504004 30.006005 35.010007 37.512006 42.516008 45.018007 50.022008 55.02601 60.03001 62.53201 64.53001 69.534008 76.032009 78.534008 83.538 88.542 95.04 100.044 103.041 105.543 110.043 112.041 117.045 121.545 126.045 128.547 136.04399 141.04799 146.05199 151.05599 153.55799 161.05498 166.05898 170.55898 173.06098 175.56298 180.56697 185.57097 188.07297 193.07697 197.57697 202.58097 204.57897 209.58296 214.58696 219.59096">switch to a non low power clock mode must be avoided.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.00002 54)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="556.53677" x="232.551 242.659 253.551 262.10499">NOTE</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.00002 54)" font-size="14" font-family="TimesLTStd"><tspan y="581.15" x="71.99899 79.783 86.783 91.445 94.945 98.837 105.837 112.053 115.553 121.769008 128.76902 132.66101 139.66101 144.32302 149.76902 156.76902 162.98502 169.20102 173.09302 177.75502 181.64702 187.86302 191.36302 202.25502 209.25502 216.25502 222.47103 227.91703 231.41703 238.41703 243.07903 246.57903 253.57903 260.57905 266.79505 271.45704 277.67304 281.56504 285.45704 292.45704 299.45704 302.95704 306.45704 311.90306 318.11906 324.33506 327.83506 331.72706 338.72706 344.94306 348.44306 355.44306 362.44306 372.55107 378.76707">For the chip-specific modes of operation, see the power</tspan><tspan y="597.15" x="71.99899 82.89099 89.106998 96.106998 102.323 109.323 115.539 126.431 132.647 139.647 143.539 147.039 153.255 160.255 166.47101 173.47101 177.363 183.57901 188.24102 191.74102 198.74102 203.40302 206.90302 210.79502 217.79502 221.68701 227.13301 230.63301 243.07901 252.417 262.525">management chapter of this MCU.</tspan></text>
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<path transform="matrix(1,0,0,1,54.00002,24.56929)" stroke-width=".8" stroke-linecap="butt" stroke-miterlimit="4" stroke-linejoin="miter" fill="none" stroke="#666666" d="M16-6.4 536.8 0V16H-6.4L16-6.4Z"/>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.00002 18)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="25.87323" x="0 5.499 10.998 16.497 21.501 24.498 27 32.499 37.998 43.002004 45.504 48.006 54.504 59.508005 64.512 69.516 73.017 75.519 81.018 84.015 86.517 92.016">Functional Description</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.00002 734.93869)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="130.005 137.225 142.785 148.345 151.125 157.795 163.905 170.015 173.345 179.455 185.015 193.905 196.685 199.465 205.025 207.805 215.025 220.58499 223.915 229.47499 233.36499 238.92499 245.03499 250.59499 256.155 258.935 267.26499 272.82499 278.93498 285.04496 290.60496 293.38496 296.16496 298.94496 306.16496 311.72496 317.28495 320.06495 322.84495 328.40495 331.18495 336.74494 342.85493 348.9649 351.7449 357.3049 362.8649 368.4249">K60 Sub-Family Reference Manual, Rev. 2 Jun 2012</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.00002 751.756)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="-.00102 5.0029809 10.006981">586</tspan></text>
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<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 220.32003 751.756)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="58.45 65.12 69.01 74.57 77.35 80.13 89.02 91.799999 97.909999 103.46999 107.35999">Preliminary</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 391.68 751.756)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="44.775 50.274003 53.271005 58.275007 63.279008 67.77901 72.27901 77.283008 79.281009 84.285 86.787 92.79 97.794 105.291 107.289 111.789 116.793 121.797 126.800998 131.805 136.305 138.80699 143.81099 146.80799 149.30998 151.81198 154.31398 159.31798 163.81798">Freescale Semiconductor, Inc.</tspan></text>
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<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 54 763.756)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="180.87 188.65 194.20999 200.31999 205.87999 209.76999 215.32999 218.10999 220.88999 228.10999 234.21999 239.77999 242.55998 248.66999 254.22998 259.78999 265.34999 268.12998 270.90998 277.01997 280.34996 286.45994 290.34996 299.23997 304.79997 308.12995 310.90995 317.01994">General Business Information</tspan></text>
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