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Ryan Malloy 5252d1d73c Add hardware reference docs (A3981, K60, RYS352A) 
Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint,
3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep.

NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference
manual. Cortex-M4 96MHz MCU running the G2 firmware.

Reyax RYS352A GPS module: datasheet and PAIR command guide.
GPS receiver on the G2 board (used for auto-location/satellite lookup).

All extracted as markdown + page images + vector SVGs for LLM context.
Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.
2026-02-14 18:36:42 -07:00

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36 KiB (Stored with Git LFS)
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="16" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.65625" x="0 8.896001 17.792002 22.240002 31.136002 35.584005">28.5.3</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 112.65332 54)" font-size="16" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.65625" x="0 15.104001 24.000002 28.448002 33.776 38.224004 47.120004 52.448 61.344 66.672008 75.56801">Wait states</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="33.85" x=".002 9.340001 15.556002 21.772004 27.988003 34.988004 40.434003 46.65 50.15 54.042005 61.042005 67.258 70.758 76.97401 83.97401 88.63601 94.85201 98.35201 101.85201 108.068019 112.73002 119.73002 125.17602 130.62203 137.62203 143.83803 148.50003 152.00003 157.44603 167.55403 171.44603 175.33803 181.55403 188.55403 192.05403 195.55403 201.77004 208.77004 215.77004 219.27004 226.27004 233.27004 238.71604 242.21604 253.10803 259.32405 264.77006 268.66206 274.87806 279.54005 284.98606 288.48606 294.70207 300.91807 307.91807 311.41807 318.41807 324.63407 328.13407 334.35008 338.24208 345.24208 351.45808 358.45808 364.67408 371.67408 375.17408 381.39009 385.28208 388.78208 394.99809 398.49809 405.49809 409.39009 416.39009 423.39009 429.60609 434.26808 437.76808 442.43006 447.09205 453.30805 460.30805 467.30805 473.52406 480.52406 486.74006">Because the core, crossbar switch, and bus masters can be clocked at a higher frequency</tspan><tspan y="49.85" x=".00203 3.8940304 10.894031 17.110032 24.110032 27.610032 31.502032 38.50203 44.71803 48.21803 52.880029 56.77203 62.98803 68.43403 75.43403 78.93403 85.15003 89.04203 96.04203 102.25803 109.25803 112.75803 116.25803 120.92004 124.812038 131.02803 136.47403 143.47403 146.97403 157.86603 164.08203 174.97403 181.97403 186.63603 193.63603 197.13603 203.35204 209.56804 215.78404 222.00005 227.44605 232.89205 239.10805 244.55405 248.05405 251.94605 258.94606 265.16206 269.05406 272.55406 279.55406 286.55406 290.05406 297.05406 304.05406 307.94606 311.44606 318.44606 322.33805 326.23005 329.73005 333.62205 340.62205 344.12205 348.01405 355.01405 361.23005 364.73005 370.17607 377.17607 383.39207 389.60807 396.60807 400.50007 406.71607 410.60807 414.50007 421.50007 428.50007 432.00007 439.00007 446.00007 450.66206 455.32405 461.54005 466.20204 469.70204 476.70204">than the flash clock, flash memory accesses that do not hit in the speculation buffer or</tspan><tspan y="65.85" x=".00203 6.2180306 12.434031 18.650032 25.650032 31.866032 35.36603 42.36603 47.81203 54.81203 61.02803 64.92003 68.81203 75.81203 79.31203 83.97403 90.19003 97.19003 104.19003 108.08203 112.74403 118.96004 122.46004 132.56804 138.78404 142.67604 146.56804 150.06804 155.51404 159.40604 165.62204 169.51404 175.73004 181.17604 184.67604 188.17604 196.73004 203.73004 209.94605 213.44605 220.44605 227.44605 238.33805 245.33805 251.55405 256.21604 259.71604 266.71604 271.37803 274.87803 284.98603 291.20204 295.09403 298.98603 302.48603 307.93205 311.82405 318.04005 321.93205 328.14805 333.59407 337.09407 344.09407 350.31007 357.31007 363.52607 370.52607 377.52607 382.97209 386.47209 393.47209 400.47209 403.97209 410.97209 417.97209 421.86408 428.86408 432.36408 439.36408 444.02607 447.52607 451.41807 458.41807">cache usually require wait states. The number of wait states depends on both of the</tspan><tspan y="81.85" x=".00203 4.66403 11.66403 15.55603 19.44803 26.44803 36.55603 40.448034 47.448034 54.448034">following:</tspan><tspan y="97.85" x="7.50603 14.50603 23.998032 27.890032 34.89003 41.10603 44.60603 49.26803 55.484029 59.37603 63.268033 70.268039 73.768039 80.768039 85.43004 88.93004 92.82204 99.82204 106.03804 109.53804 115.75404 122.75404 127.416049 133.63205 137.13205 143.34806 147.24005 154.24005 160.45606 167.45606 170.95606 174.84806 181.84806 185.34806 189.24005 196.24005 202.45606 205.95606 210.61806 214.51006 220.72606 226.17206 233.17206 236.67206 242.88806 246.78006 253.78006 259.99607 266.99607 270.49607 273.99607 280.21208 287.21208">1.the ratio of the core clock to the flash clock, and</tspan><tspan y="113.85" x="7.50602 14.50602 23.99802 27.89002 34.890024 41.10602 44.60602 51.60602 58.60602 64.82202 70.26802 76.484027 79.984027 84.64603 90.86203 94.75403 100.97003 104.86203 108.75403 115.75403 122.75403 128.20003 135.20003 139.09203 146.09203 149.59203 156.59203 161.25403 164.75403 168.64603 175.64603 181.86203 185.36203 191.57804 198.57804 203.24004 209.45604 212.95604 219.17205 223.06404 230.06404 236.28005 243.28005 246.78005 252.99605 259.99604 266.99604 270.49604 275.15803 279.05003 285.26603 290.71205 297.71205 301.21205 307.42805 311.32005 318.32005 324.53605 331.53605 335.03605 341.25205 345.14405 348.64405 352.53605 359.53605 365.75205 369.25205 373.14405 377.03605 387.92805 394.14405 397.64405 401.53605 408.53605 414.75205 418.25205 422.91404 429.13005 435.34605 442.34605 445.84605 449.73805">2.the phase relationship of the core clock and flash clock at the time the read is</tspan><tspan y="129.85" x="23.99804 28.66004 34.87604 41.87604 48.87604 55.09204 60.53804 64.43004 70.64604 77.64604">requested.</tspan><tspan y="155.85" x=".0020389558 8.556039 15.556039 21.77204 25.27204 29.93404 36.15004 40.04204 43.934045 50.934045 54.434045 61.434045 66.09605 69.59605 73.488048 80.488048 86.70405 90.20405 96.42005 103.42005 108.082057 114.29806 117.79806 124.01406 127.90606 134.90607 141.12207 148.12207 151.62207 155.51407 162.51407 166.01407 169.90607 176.90607 183.12207 186.62207 191.28408 195.17607 201.39208 206.83808 213.83808 217.33808 223.55408 227.44608 234.44608 240.66208 247.66208 251.16208 255.05408 260.5001 264.0001 270.2161 277.2161 284.2161 290.4321 294.3241 297.8241 301.7161 308.7161 312.2161 316.1081 323.1081 329.3241 332.8241 339.8241 346.0401 349.9321 356.9321 363.1481 366.6481 373.6481 378.3101 381.8101 389.5941 397.37809 406.7161 413.7161 423.0541 432.39213 437.0541 446.39213 453.39213 462.73014 475.94615 483.73014 493.06816">The ratio of the core clock to the flash clock is equal to the value of PFB0CR[B0RWSC]</tspan><tspan y="171.85" x=".0020889557 7.898089 11.398088 18.398089 21.898089 26.56009 33.56009 38.222089 41.722089 48.722089 54.938089 61.938089 68.93809 72.43809 79.43809 82.93809 89.15409 96.15409 103.15409 106.65409 110.54609 117.54609 121.04609 124.93809 131.93808 138.15409 141.65409 148.65409 154.87009 158.76209 165.76209 171.97809 175.47809 182.47809 187.14009 190.64009 198.42409 206.20809 215.54608 222.54608 231.88408 241.22208 245.88408 255.22208 262.22209 271.5601 284.7761 292.5601 301.8981 306.5601 310.0601 317.9561 321.4561 328.4561 331.9561 336.61808 343.61808 348.28007 351.78007 358.78007 364.99607 371.99607 378.99607 382.49607 389.49607">+ 1 for bank 0 and to the value of PFB1CR[B1RWSC] + 1 for bank 1.</tspan><tspan y="196.25" x=".0020889557 7.78609 14.78609 19.44809 22.94809 29.16409 36.16409 42.38009 53.27209 60.27209 64.16409 70.3801 73.8801 77.3801 81.272098 88.272098 91.772098 97.9881 101.4881 106.9341 113.9341 119.3801 123.272098 129.4881 140.3801 143.8801 153.9881 157.8801 161.7721 168.7721 172.2721 178.4881 181.9881 188.9881 192.8801 199.8801 203.3801 209.5961 216.5961 221.2581 227.4741 232.13611 236.0281 243.0281 247.69011 252.35211 256.2441 262.4601 267.90614 274.90614 278.40614 284.62214 288.51414 295.51414 301.73014 308.73014 312.23014 316.89213 323.10813 327.00013 330.89213 337.89213 341.39213 344.89213 351.10813 354.60813 359.2701 365.4861 371.70213 378.70213 382.20213 386.09413 393.09413 399.31013 403.20213 406.70213 413.70213 420.70213 426.91813 432.36415 435.86415 442.86415 449.86415 453.75614 457.25614 464.25614 468.14814 472.04014 475.54014 479.43214">For example, in a system with a 4:1 core-to-flash clock ratio, a read that does not hit in</tspan><tspan y="212.25" x=".0020889557 3.8940895 10.89409 17.11009 20.61009 26.056092 33.05609 39.27209 45.48809 52.48809 56.380094 62.596094 66.48809 70.38009 77.38009 84.38009 87.88009 94.88009 101.88009 106.54209 111.204097 117.4201 122.0821 125.5821 132.58209 137.2441 140.7441 144.6361 151.6361 157.8521 161.3521 167.5681 173.7841 180.0001 187.0001 193.21611 196.71611 202.93212 209.14812 216.14812 219.64812 223.54012 229.75612 236.75612 242.97212 246.47212 253.47212 259.6881 263.5801 273.6881 279.9041 286.12013 293.12013 296.62013 303.62013 307.12013 313.33613 320.33613 327.33613 330.83613 337.83613 341.33613 347.55213 354.55213 359.2141 365.4301 368.9301 375.14613 379.03813 386.03813 392.25413 399.25413 402.75413 408.97013 415.97013 422.18614 426.07814 432.29414 437.74015 441.24015 445.13215">the speculation buffer or the cache can take between 4 and 7 core clock cycles to</tspan><tspan y="228.25" x=".0021189557 6.2181198 13.21812 24.11012 31.11012 35.00212 41.21812 45.110124 51.326124">complete.</tspan><tspan y="244.25" x="13.106119 23.99812 32.55212 39.55212 45.76812 49.26812 56.26812 62.48412 67.93012 71.82212 76.48412 82.70013 88.91613 94.36213 100.57813 104.07813 109.52413 115.740139 121.95614 128.95615 135.17215 139.83415 143.72615 150.72615 154.22615 158.11815 163.56415 167.06415 173.28015 176.78015 183.78015 189.99616 194.65816 198.55016 205.55016 212.55016 216.05016 223.05016 227.71216 231.21216 238.21216 241.71216 247.92816 254.92816 259.59016 265.80616 269.30616 275.52217 279.41416 286.41416 292.63017 299.63017 303.13017 309.34617 316.34617 322.56217 326.45417 332.67018 338.11619 341.61619 348.61619 354.83219 361.0482 367.2642 374.2642 379.7102 385.9262 389.4262 395.6422 399.1422 403.8042 410.0202 416.2362 423.2362 426.7362 431.3982 436.06019 443.06019 453.95219 457.45219 461.34419 468.34419">&#x2022;The best-case scenario is a period of 4 core clock cycles because a read from the</tspan><tspan y="260.25" x="23.99816 28.66016 32.552164 38.76816 44.21416 51.21416 54.71416 65.60616 71.82217 82.714168 89.714168 94.37617 101.37617 104.87617 108.768169 114.98417 121.98417 128.20017 133.64617 137.14617 144.14617 147.64617 152.30817 156.20017 162.41617 167.86217 174.86217 178.36217 184.57817 188.47017 195.47017 201.68618 208.68618 212.18618 215.68618 225.79418 232.79418 236.68618 242.90218 249.90218 253.40218 257.2942 261.95619 268.17219 275.17219 280.6182 284.5102 290.7262 294.6182 300.8342 306.2802 309.7802 313.6722 320.6722 324.1722 331.1722 334.6722 340.8882 347.8882 352.5502 358.7662 362.2662 368.4822 372.3742 379.3742 385.5902 392.5902 398.03623">flash memory takes 1 flash clock, which translates to 4 core clocks.</tspan><tspan y="276.25" x="13.10615 23.99815 32.55215 39.55215 45.76815 49.26815 59.376153 66.37615 71.038158 76.48415 80.37615 85.038158 91.25416 97.47016 102.91616 109.132167 112.632167 118.07816 124.29417 130.51016 137.51016 143.72617 148.38817 152.28017 159.28017 162.78017 166.67217 172.11817 175.61817 181.83417 185.33417 192.33417 198.55017 203.21218 207.10417 214.10417 221.10417 224.60417 231.60417 236.26618 239.76618 246.76618 250.26618 256.48219 263.48219 268.14418 274.36018 277.86018 284.07618 287.96818 294.96818 301.18418 308.18418 311.68418 317.90019 324.90019 331.11619 335.00819 341.22419 346.6702 350.1702 353.6702 359.8862 366.8862 373.8862 379.3322 383.2242 388.67024 392.56224 396.45423 403.45423 410.45423 413.95423 420.95423 425.6162 429.1162 436.1162 439.6162 445.8322 452.8322 459.04823 462.94023 469.15623 474.60224 478.10224 482.76423 489.76423">&#x2022;The worst-case scenario is a period of 7 core clock cycles, consisting of 4 cycles for</tspan><tspan y="292.25" x="23.99816 27.89016 34.89016 41.10616 44.60616 49.268159 55.484159 61.700159 68.70016 72.20016 79.20016 86.20016 92.41616 97.07816 103.29417 107.186168 111.07816 118.07816 125.07816 128.57816 134.79416 141.79416 148.79416 152.29416 159.29416 162.79416 169.01016 176.01016 182.22617 186.11817 192.33417 197.78017 201.28017 208.28017 212.94217 216.44217 223.44217 229.65818 233.55017 239.76618 246.76618 250.26618 254.15818 261.15818 264.65818 270.87419 274.76618 278.65818 285.65818 292.65818 296.15818 300.05018 307.05018 313.26618 316.76618 322.98219 329.98219 334.64418 340.86018 344.36018 350.57618 357.57618 364.57618 368.07618 372.73817 376.63017 382.84617 388.29219 395.29219 398.79219 405.00819 408.90019 415.90019 422.11619 429.11619 434.5622">the read operation and 3 cycles of delay to align the core and flash clocks.</tspan><tspan y="308.25" x="37.10215 47.994153 58.102155 61.602155 68.60216 74.81816 78.71016 84.92616 91.92616 95.42616 99.31816 106.31816 109.81816 116.034168 119.92616 123.81816 130.81816 137.81816 141.31816 145.21016 152.21016 158.42617 161.92617 168.14217 175.14217 179.80417 186.02017 189.52017 195.73618 202.73618 209.73618 213.23618 217.89818 221.79018 228.00618 233.45218 240.45218 243.95218 250.16819 254.06018 261.06019 267.27619 274.27619 279.7222 283.2222 294.1142 298.0062 305.0062 312.0062 315.8982 319.3982 326.3982 332.6142 338.8302 345.8302 350.4922 353.9922 360.9922 367.2082 373.4242 379.6402 386.6402 392.0862 398.30223 401.80223 408.80223 415.80223 422.80223 426.30223 432.51823 438.73423 445.73423 449.23423 453.8962 460.1122 467.1122 474.1122 480.32823 485.77424 489.66624 493.16624">&#x2022;A delay to align the core and flash clocks might occur because you can request a</tspan><tspan y="324.25" x="47.99417 52.65617 58.87217 65.08817 72.08817 75.58817 81.80418 88.80418 95.02018 98.91218 105.12818 108.62818 115.62818 122.62818 126.12818 132.34418 139.34418 146.34418 149.84418 156.06018 163.06018 167.72219 173.93819 177.43819 183.65419 187.54619 194.54619 200.76219 207.76219 211.26219 217.4782 224.4782 231.4782 237.6942 241.1942 244.6942 251.6942 258.6942 262.5862 266.0862 269.9782 276.9782 283.1942 287.0862 290.5862 296.80223 303.80223 310.80223 317.01823 320.51823 327.51823 334.51823 340.73423 346.18025 349.68025 356.68025 363.68025 367.57225 371.07225 378.07225 384.28825 390.50425 396.72026 402.16627 407.61228 413.82829 418.49028 422.38227 426.27427 433.27427 436.77427 442.99028 446.88227 450.77427 457.77427 464.77427 468.27427 478.38227 482.27427 486.16627 493.16627 496.66627">read cycle on any core clock edge, but that edge does not necessarily align with a</tspan><tspan y="340.25" x="47.99417 52.65617 56.548173 62.76417 68.210178 75.210178 78.710178 84.92618 88.81818 95.81818 102.03418 109.03418 112.53418 118.75018 125.75018 132.75019 138.96619 142.46619 152.57419 159.57419 165.79019 170.4522 176.6682 180.1682 184.0602 191.0602 197.2762 200.7762 205.4382 211.6542 217.87021 224.87021 228.37021 234.58621 240.80222 247.80222 251.30222 256.74824 260.64024 266.85624 271.51823 275.41023">flash clock edge where the read can start.</tspan><tspan y="356.25" x="37.10218 47.994184 52.65618 59.65618 63.15618 67.04818 74.04818 77.94018 83.38618 86.88618 93.10218 99.318187 104.76418 110.98019 114.48019 117.98019 121.872188 128.8722 135.0882 138.5882 143.2502 149.4662 155.6822 162.6822 166.1822 173.1822 180.1822 186.39821 191.06021 197.27622 201.16822 205.06021 212.06021 219.06021 222.56021 226.45221 231.89821 235.39821 242.39821 248.61421 252.50621 258.7222 265.7222 271.9382 278.9382 282.4382 289.4382 296.4382 299.9382 306.1542 309.6542 316.6542 323.6542 334.5462 341.5462 347.7622 352.4242 355.9242 362.9242 367.58619 371.08619 377.3022 384.3022 388.96418 395.18019 398.68019 404.89619 408.78819 415.78819 422.00419 429.00419 434.4502 437.9502 444.1662 451.1662 458.1662 464.3822 468.2742 471.7742 475.6662 482.6662 486.1662 490.0582 497.0582">&#x2022;In this case, the read operation is delayed by a number of core clocks equal to the</tspan><tspan y="372.25" x="47.9942 54.2102 61.2102 65.8722 72.0882 76.750209 80.642208 87.642208 92.30421 96.96621 100.85821 107.07421 112.52021 119.52021 123.02021 129.2362 133.1282 140.1282 146.34421 153.34421 156.84421 161.50621 167.72222 171.61421 175.50621 182.50621 186.00621 196.89821 200.7902 207.7902 214.7902 220.2362 223.7362 230.7362 237.7362 243.95221 247.84421 251.34421 258.3442 261.8442 266.5062 270.0062 277.0062 280.5062 288.4022 291.9022 298.9022 302.4022 305.9022 314.45619 321.45619 327.67219 331.56419 335.06419 338.95619 344.4022 347.9022 351.4022 358.4022 361.9022 368.1182 375.1182 382.1182 386.0102 389.9022 393.7942 400.7942 407.7942 414.0102 417.9022 421.4022 427.6182 434.6182 439.28019 445.4962 448.9962 455.2122 459.1042 466.1042 472.3202">core-to-flash clock ratio minus one: 4 - 1 = 3. That is, 3 additional core clock</tspan><tspan y="388.25" x="47.9942 54.2102 61.2102 67.4262 71.3182 77.5342 82.9802 86.4802 92.696208 97.35821 103.57421 107.07421 111.73621 117.95222 124.95222 131.95221 135.84421 140.50621 146.72222 153.72222 157.22222 161.11421 168.11421 171.61421 177.06021 184.06021 191.06021 197.27622 204.27622 208.93822 215.93822 222.93822 226.83022 233.04622 239.26222 242.76222 246.65422 253.65422 259.8702 263.3702 269.5862 273.4782 280.4782 286.6942 293.6942 299.14024 302.64024 309.64024 315.85624 320.51823 327.51823 332.1802 338.3962 341.8962 345.7882 352.7882 359.0042 362.5042 367.1662 373.3822 379.5982 386.5982 390.0982 397.0982 404.0982 410.3142 414.9762 421.1922 425.0842 428.9762 435.9762 442.9762 446.4762 452.6922 458.9082 465.9082 469.4082 474.85423 478.74623 484.96223 489.6242 493.5162">cycles are required to synchronize the clocks before the read operation can start.</tspan><tspan y="414.25" x=".0022125245 10.110213 14.0022139 17.894215 21.394215 31.502217 37.718217 41.610219 45.50222 49.00222 54.44822 58.34022 64.55622 68.44822 74.66422 80.11022 83.61022 89.826229 96.826229 103.826229 107.326229 112.772228 119.772228 126.772228 132.98822 139.98822 144.65023 151.65023 158.65023 162.54222 168.75823 174.97423 178.86623 182.75823 189.75823 196.75823 200.25823 207.25823 213.47423 217.36623 223.58223 230.58223 236.02823 239.52823 245.74423 250.40624 256.62223 260.12223 267.12223 273.33824 280.33824 287.33824 291.23023 297.44624 304.44624 307.94624 314.16224 321.16224 325.05424 332.05424 342.94624 349.16224 353.05424 356.94624 363.16224 369.37825 373.27024 377.16224 384.16224 387.66224 394.66224 401.66224 405.16224 409.05424 416.05424 422.27024 425.77024 433.55424 437.44624 443.66224 449.10826">All wait states and synchronization delays are handled automatically by the Flash</tspan><tspan y="430.25" x=".0022125245 12.448214 18.664216 29.556218 36.556219 41.218217 48.218217 51.718217 61.056219 68.05621 75.05621 78.94821 83.610218 90.610218 94.50221 98.39421 104.610218 109.27222 112.77222 116.27222 126.38022 133.38022 136.88022 143.88022 147.77222 152.43422 158.65023 164.86623 168.75823 172.25823 179.25823 184.70423 190.92023 195.58223 199.08223 205.29824 212.29824 219.29824 223.96024 227.85224 234.85224 241.85224 246.51424 252.73024 256.62226 260.51426 267.51426 274.51426 278.01426 281.90626 287.35227 290.85227 295.51426 301.73027 308.73027 315.73027 319.62226 324.28425 330.50025 337.50025 341.00025 348.00025 352.66224 356.16224 362.37825 369.37825 375.59425 382.59425 386.09425 392.31025 396.20225 400.09425 407.09425 417.20225 423.41825 430.41825 433.91825 437.81025 444.81025 448.31025 453.75627 459.97227 463.86427 467.36427 474.36427 481.36427 484.86427 488.75627 495.75627">Memory Controller. No direct user configuration is required or even allowed to set up the</tspan><tspan y="446.25" x=".0022125245 4.6642129 8.556213 14.772214 20.218214 27.218214 30.718214 40.826215 47.042215 50.934217 54.826219 58.326219 63.772218 67.664218 73.88022 77.77222 83.98822 89.43422">flash wait states.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 541.8)" font-size="16" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.65625" x=".00619 8.902191 17.798192 22.246191 31.142193 35.590196">28.5.4</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 112.65332 541.8)" font-size="16" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.65625" x=".00619 10.678191 20.454192 29.350193 38.246194 48.022195 52.470197 61.366197 66.6942 71.1422 80.0382 88.934207 93.3822 99.6062 108.502208 117.39821 127.17421">Speculative reads</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="525.05" x=".0042 8.5582 15.5582 21.7742 25.2742 33.0582 45.504205 54.842206 58.342206 65.34221 71.55821 77.00421 80.50421 86.720218 90.220218 95.666217 99.55821 106.55821 113.55821 117.45021 123.666217 127.166217 134.16622 141.16622 145.82822 150.49022 156.70623 161.36823 164.86823 168.76023 175.76023 181.97623 185.86823 189.36823 194.03023 200.24623 206.46224 213.46224 218.90824 222.40824 228.62424 235.62424 241.84024 248.05625 255.05625 258.55625 262.44825 269.44825 272.94825 276.84025 283.84025 290.05625 293.55625 300.55625 306.77226 313.77226 317.66426 321.16426 331.27226 338.27226 342.93424 349.93424 353.43424 357.32624 364.32624 367.82624 371.71824 378.71824 384.93424 388.43424 393.09623 396.98823 403.20423 408.65025 415.65025 419.15025 430.04225 436.25825 447.15025 454.15025 458.81224 465.81224 469.31224 473.20423">The FMC has a single buffer that reads ahead to the next word in the flash memory if</tspan><tspan y="541.05" x=".00421 3.8962105 10.896211 17.112212 21.774212 27.990212 31.490212 35.382215 40.828214 44.328214 50.544214 57.544214 61.044214 64.93621 71.93621 75.82821 82.04421 85.54421 91.760219 98.760219 104.97622 108.86822 115.08422 118.58422 122.08422 129.86823 136.86823 143.08423 149.30023 156.30023 160.19223 166.40824 170.30023 174.19223 181.19223 187.40824 190.90824 197.90824 202.57024 208.78624 213.44824 219.66425 223.55625 229.77225 236.77225 240.66425 247.66425 254.66425 258.16426 262.05625 267.50227 271.00227 278.00227 282.66426 289.66426 296.66426 301.32624 307.54225 318.43424 329.32624 335.54225 342.54225 346.43424 352.65025 356.15025 360.81224 367.81224 372.4742 375.9742 382.19023 388.40623 394.62223 401.62223 405.12223 412.12223 418.33824 425.33824 432.33824 435.83824 440.5002 447.5002">there is an idle cycle. Speculative prefetching is programmable for each bank for</tspan><tspan y="557.05" x=".00421 3.8962105 10.896211 16.34221 20.234211 24.896212 31.896212 38.112215 42.004217 45.896219 52.896219 59.896219 63.396219 69.61222 76.61222 83.61222 87.50422 94.50422 99.16622 102.66622 109.66622 115.882228 119.77422 125.99023 129.49024 135.70624 141.92224 148.13825 154.35425 159.80025 165.24625 171.46225 176.90825 180.40825 187.40825 192.85425 196.74625 203.74625 210.74625 214.24625 218.13825 225.13825 231.35425 234.85425 244.19225 251.19225 261.30024 269.08424 277.6382 281.1382 287.35423 294.35423 301.35423 304.85423 314.19224 321.19224 325.85423 333.6382 342.1922 345.6922 350.3542 354.2462 360.4622 364.3542 371.3542 376.8002 380.3002 387.3002 391.9622 395.4622 403.2462 411.03019 420.3682 427.3682 436.7062 446.04423 449.54423 455.76023 462.76023 469.76023 473.26023 477.15223 484.15223">instruction and/or data accesses using the B0DPE and B0IPE fields of PFB0CR and the</tspan><tspan y="573.05" x=".00426 9.342261 16.342263 26.450264 34.234266 42.788267 46.288267 52.504266 59.504266 66.504268 70.004268 79.34227 86.34227 91.00427 98.78828 107.34228 110.84228 115.50428 119.39628 125.61228 129.50429 136.50429 141.95029 145.45029 152.45029 157.11229 160.61229 168.39629 176.18029 185.51828 192.51828 201.85628 211.19428 214.69428 218.19428 227.53227 233.74828 239.96428 246.18029 253.18029 258.62629 264.8423 268.3423 279.23429 285.4503 292.4503 299.4503 302.9503 309.1663 316.1663 323.1663 329.3823 332.8823 339.0983 345.3143 351.5303 357.7463 363.19233 368.63835 374.85435 380.30036 383.80036 390.01637 394.67835 400.89436 404.39436 409.84037 416.05638 423.05638 430.05638 436.27238 443.27238 447.16438 451.05638 457.27238 461.16438 464.66438 468.16438 475.16438 480.61039 484.50239 491.50239">B1DPE and B1IPE fields of PFB1CR. Because many code accesses are sequential, using</tspan><tspan y="589.05" x=".0043099999 3.8963104 10.896311 17.112313 20.612313 26.058314 33.05831 39.27431 45.49031 52.49031 56.382314 62.598314 66.49031 70.38231 77.38231 83.59831 87.09831 94.09831 98.760318 104.97632 109.63832 115.854328 119.74632 125.962329 132.96233 136.46233 143.46233 150.46233 155.12433 159.78633 166.00234 170.66434 174.16434 178.05634 188.94834 195.94834 200.61034 207.61034 214.61034 220.82634 226.27234 229.77234 236.77234 242.98834 247.65035 252.31235 259.31236 263.97434 274.86634 281.08235 288.08235 294.29835 300.51435 304.01435 307.90635 314.90635 318.40635 329.29835 336.29835 341.74436 345.63636 349.13636 355.35237 361.56837 367.01438 373.23039 378.6764">the speculative prefetch buffer improves performance in most cases.</tspan><tspan y="613.45" x=".00434 13.220341 20.22034 26.43634 33.43634 36.93634 42.38234 49.38234 55.59834 61.81434 68.81434 72.70634 78.92234 82.81434 86.70634 93.70634 99.92234 103.42234 108.08434 114.30035 120.51635 127.51635 132.96236 136.46236 142.67836 147.34037 153.55637 157.05637 163.27237 170.27237 176.48838 183.48838 187.38037 193.59638 200.59638 204.09638 207.59638 211.48838 218.48838 224.70438 228.20438 235.98838 248.43437 257.77238 261.27238 265.16438 276.05638 286.94837 293.16438 300.16438 304.05638 310.27238 314.16438 320.38038 324.27238 331.27238 334.77238 339.43437 345.65037 352.65037 359.65037 365.86637 371.31239 375.20439 380.6504 384.1504 388.0424 395.0424 401.2584 404.7584 411.7584 417.9744 424.9744 428.8664 432.3664 437.8124 444.0284 451.0284 458.0284 464.24443 471.24443 475.1364 479.0284 485.24443">When speculative reads are enabled, the FMC immediately requests the next sequential</tspan><tspan y="629.45" x=".0043099999 6.2203109 13.22031 20.22031 24.88231 31.098313 36.54431 41.99031 45.49031 51.70631 56.36831 60.26031 66.47631 71.13831 74.63831 80.85432 84.35432 89.01632 95.23232 101.448329 108.448329 111.948329 118.16433 125.16433 136.05634 143.05634 146.94834 153.16434 157.05634 163.27234 168.71834 172.21834 175.71834 185.05634 192.05634 195.55634 200.21834 206.43434 213.43434 220.43434 226.65035 232.09635 235.98834 239.88034 246.88034 253.88034 257.38035 261.27235 268.27235 274.48835 277.98835 284.98835 291.20436 298.20436 302.09635 305.59635 315.70436 322.70436 327.36634 334.36634 337.86634 341.75834 352.65034 363.54234 369.75834 376.75834 380.65034 386.86634 390.75834 396.97434 400.86634 407.86634 411.36634 414.86634 420.31236 427.31236 433.52836 439.74436 446.74436 450.63636 456.85237 460.74436 464.63636 471.63636">address after a read completes. By requesting the next word immediately, speculative</tspan><tspan y="645.45" x=".0043099999 4.6663105 10.882311 17.098313 24.098313 29.544314 33.04431 39.26031 45.47631 52.47631 55.97631 62.97631 69.192317 73.08431 80.08431 83.58431 87.47631 94.47631 97.97631 102.63831 108.85432 115.85432 122.85432 129.07032 135.28632 138.78632 145.78632 150.44832 153.94832 160.16432 167.16432 173.38033 180.38033 183.88033 190.09633 193.98833 197.88033 208.77233 212.66432 219.66432 225.88033 229.77233 235.98833 239.48833 249.59633 255.81233 259.70436 263.59635 267.09635 272.54237 276.43437 282.65037 286.54237 292.75837 298.20439 301.70439 311.81239 318.81239 325.02839 332.02839 335.52839 341.7444 347.9604 354.1764 360.3924 365.8384 371.28443 375.17643 382.17643 389.17643 392.67643 398.12245 404.33845 411.33845 418.33845 424.55445 431.55445 435.44645 439.33845 445.55445 449.44645 452.94645 459.16246 466.16246 473.16246">reads can help to reduce or even eliminate wait states when accessing sequential code</tspan><tspan y="661.45" x=".0043099999 6.2203109 13.22031 20.22031 24.11231 31.11231 35.77431 39.27431 46.27431 52.49031 56.382314 62.598314">and/or data.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 18)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="25.87323" x="0 5.499 10.998 16.497 21.501 24.498 27 32.499 37.998 43.002004 45.504 48.006 53.505 58.509004 63.513006 68.517009 72.018009 74.520008 80.019008 83.01601 85.518009 91.017009">Functional description</tspan></text>
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