Ryan Malloy
5252d1d73c
Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint, 3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep. NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference manual. Cortex-M4 96MHz MCU running the G2 firmware. Reyax RYS352A GPS module: datasheet and PAIR command guide. GPS receiver on the G2 board (used for auto-location/satellite lookup). All extracted as markdown + page images + vector SVGs for LLM context. Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.
111 lines
32 KiB (Stored with Git LFS)
XML
111 lines
32 KiB (Stored with Git LFS)
XML
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="11.85" x="48.006 57.344 64.344 69.006008 79.114009 88.45201 96.236019 104.790019 111.790019 121.89802 131.23603 139.02002 143.68202 147.18202 154.18202 158.07402 161.96602 167.41202 170.91202 174.80402 181.80402 185.30402 192.30402 194.82402 201.82402 208.82402 215.82402 219.32402 223.98603 230.98603 235.64803 239.14803 245.36403 248.86403 258.97203 268.31004 278.41804 281.91804 288.91804 295.91804 299.81004 306.81004 313.81004 317.70204 321.20204 325.864 330.526 336.742 343.742 350.742 356.958 363.958 370.174 377.174 380.674 387.674 392.336 395.836 402.836 409.836 413.336 425.782 435.89 442.10603 445.60603 449.10603 453.768 458.43 461.93 468.146 471.646 478.646 482.538 489.538 496.538">C4[DRST_DRS] bits to 2'b10 for a DCO output frequency of 60 MHz. If a high-</tspan><tspan y="27.85" x="48.00602 52.66802 58.884019 65.88402 72.88402 79.10002 82.60002 90.384029 98.93803 107.49203 110.99203 121.884029 128.88404 132.77603 136.66803 140.56003 147.56003 151.45203 155.34403 161.56003 166.22203 169.72203 176.72203 181.38404 184.88404 191.88404 198.88404 205.88404 212.88404 216.38404 220.27603 225.72203 229.22203 236.22203 242.43804 247.88404 251.77603 256.43803 262.65403 269.65403 273.15403 277.04603 284.04603 289.49205 293.38404 299.60005 305.81605 312.81605 316.31605 319.81605 325.26206 331.47807 335.37007 338.87007 342.76206 349.76206 355.97807 359.47807 368.81608 375.81608 380.47807 390.58607 399.92408 407.70808 416.26206 423.26206 433.37007 442.70808 450.49208 455.15406 458.65406 465.65406 469.54606 473.43806 478.88407 482.38407 486.27607">range FLL multiplier of 2560 is desired instead, set the C4[DRST_DRS] bits to</tspan><tspan y="43.85" x="48.00602 55.00602 57.52602 64.52602 71.52602 78.52602 82.02602 86.68802 93.68802 98.35002 101.85002 108.066028 111.566028 121.67403 131.01203 141.12003 144.62003 151.62003 158.62003 162.51203 169.51203 176.51203 180.40402 183.90402 188.56603 193.22803 199.44403 206.44403 213.44403 219.66004 226.66004 232.87604 239.87604 243.37604 250.37604 255.03804 258.53804 265.53804 272.53804 276.03804 288.48405 298.59205 304.80805">2'b11 for a DCO output frequency of 80 MHz.</tspan><tspan y="68.25" x="37.10003 48.00603 61.22203 68.22203 74.438037 81.438037 84.938037 91.938037 97.38403 101.27603 108.27603 115.27603 118.77603 124.992038 128.49204 135.49204 142.49204 145.99204 152.99204 159.99204 166.99204 170.49204 177.49204 187.60004 193.81604 197.31604 203.53205 210.53205 214.42404 220.64005 225.30205 232.30205 238.51805 242.41005 245.91005 250.57205 256.78807 261.45005 267.66606 272.32804 278.54405 285.54405 291.76005 297.97605 301.47605 304.97605 308.86805 313.53004 317.03004 320.92204 327.92204 334.13804 337.63804 348.53004 354.74604 361.74604 365.63804 376.53004 383.53004 394.42204 397.92204 401.81404 408.81404 418.92204 423.584 428.246 434.462 441.462 448.462 454.678 458.178 468.286 477.62403">•When using a 32.768 kHz external reference, if the maximum low-range DCO</tspan><tspan y="84.25" x="48.00605 52.66805 57.330049 63.546049 70.54605 77.54605 83.762058 90.762058 96.97806 103.97806 107.47806 111.370059 118.370059 124.58606 128.47806 131.97806 138.19406 144.41007 151.41007 154.91007 161.91007 168.12607 171.62607 177.84207 184.05808 191.05808 194.95008 201.16608 208.16608 214.38208 221.38208 224.88208 234.99008 238.88208 242.77408 249.77408 253.27408 259.49009 262.99009 269.99009 276.99009 280.49009 287.49009 294.49009 301.49009 304.99009 311.99009 322.09809 328.3141 331.8141 336.47608 342.69209 347.35408 353.57008 358.23207 364.44807 371.44807 377.66407 383.88008 387.38008 391.27207 396.71809 400.21809 407.21809 413.43409 418.8801 422.7721 427.43409 433.6501 440.6501 444.1501 447.6501 453.0961 459.3121">frequency that can be achieved with a 32.768 kHz reference is desired, set</tspan><tspan y="100.25" x="48.00605 57.34405 64.344058 69.00606 79.11406 88.45206 96.23606 104.79006 111.79006 121.89806 131.23607 139.02007 143.68207 147.18207 154.18207 158.07407 161.96607 167.41207 170.91207 174.80406 181.80406 185.30406 192.30406 194.82407 201.82407 208.82407 215.82407 219.32407 225.54007 232.54007 239.54007 243.04007 248.48607 254.70207 258.5941 262.0941 271.4321 278.4321 283.0941 293.2021 305.6481 315.7561 322.7561 329.7561 334.4181 337.9181 344.9181 348.8101 352.7021 356.2021 360.0941 367.0941 370.5941 377.5941 381.0941 384.5941 393.14808 400.14808 406.36408 409.86408 414.52607 420.74208 426.18809 433.18809 437.08009 440.97209 444.86408 451.86408 458.86408 462.36408 472.47209 481.8101">C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO</tspan><tspan y="116.25" x="48.00605 55.00605 62.00605 65.89805 72.89805 79.89805 83.79005 87.29005 91.95205 104.39805 113.73605 123.844058 133.95206 144.06006 152.61406 161.95206 170.50606 180.61406 185.27606 188.77606 193.43807 198.10007 204.31607 211.31607 218.31607 224.53208 231.53208 237.74808 244.74808 248.24808 258.35609 262.24809 266.14009 273.14009 276.64009 280.53208 287.53208 293.74809 297.24809 304.24809 310.46409 320.57209 324.07209 334.96409 341.96409 345.85609 349.74809 353.64009 360.64009 364.53208 368.42408 374.64009 379.30207 382.80207 389.80207 394.46406 397.96406 404.96406 411.96406 418.96406 422.46406 432.57206 436.46406 440.35606 444.24806 447.74806 454.74806 460.96406 464.46406 471.46406">output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24</tspan><tspan y="132.25" x="48.00608 60.45208 70.56008 76.776088">MHz.</tspan><tspan y="156.65" x="37.10009 48.006093 61.22209 68.22209 74.438098 81.438098 84.938098 91.938098 97.384098 101.27609 108.27609 115.27609 118.77609 124.992099 128.4921 135.4921 142.4921 145.9921 152.9921 159.9921 166.9921 170.4921 177.4921 187.6001 193.8161 197.3161 203.5321 210.5321 214.4241 220.6401 225.30211 232.30211 238.51811 242.41011 245.91011 250.57212 256.78813 261.4501 267.6661 272.3281 278.5441 285.5441 291.7601 297.9761 301.4761 304.9761 308.8681 313.5301 317.0301 320.9221 327.9221 334.1381 337.6381 348.5301 354.7461 361.7461 365.6381 376.5301 383.5301 394.4221 397.9221 408.8141 412.7061 419.7061 424.36808 429.03007 435.24607 442.24607 449.24607 455.46208 458.96208 469.07008 478.40809">•When using a 32.768 kHz external reference, if the maximum mid-range DCO</tspan><tspan y="172.65" x="48.00611 52.66811 57.33011 63.54611 70.54611 77.54611 83.762119 90.762119 96.97812 103.97812 107.47812 111.37012 118.37012 124.58612 128.47812 131.97812 138.19412 144.41013 151.41013 154.91013 161.91013 168.12613 171.62613 177.84214 184.05814 191.05814 194.95014 201.16614 208.16614 214.38214 221.38214 224.88214 234.99015 238.88214 242.77414 249.77414 253.27414 259.49015 262.99015 269.99015 276.99015 280.49015 287.49015 294.49015 301.49015 304.99015 311.99015 322.09815 328.31416 331.81416 336.47615 342.69215 347.35414 353.57014 358.23213 364.44813 371.44813 377.66413 383.88014 387.38014 391.27214 396.71815 400.21815 407.21815 413.43415 418.88017 422.77217 427.43415 433.65016 440.65016 444.15016 447.65016 453.09617 459.31217">frequency that can be achieved with a 32.768 kHz reference is desired, set</tspan><tspan y="188.65" x="48.00614 57.344144 64.34415 69.00615 79.11415 88.45215 96.23615 104.79015 111.79015 121.898159 131.23616 139.02016 143.68216 147.18216 154.18216 158.07416 161.96616 167.41216 170.91216 174.80416 181.80416 185.30416 192.30416 194.82416 201.82416 208.82416 215.82416 219.32416 225.54016 232.54016 239.54016 243.04016 248.48616 254.70217 258.59419 262.09419 271.4322 278.4322 283.09419 293.20219 305.6482 315.7562 322.7562 329.7562 334.41819 337.91819 344.91819 348.81019 352.70219 356.20219 360.09419 367.09419 370.59419 377.59419 381.09419 384.59419 393.14817 400.14817 406.36418 409.86418 414.52616 420.74217 426.18818 433.18818 437.08018 440.97218 444.86418 451.86418 458.86418 462.36418 472.47218 481.81019">C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO</tspan><tspan y="204.65" x="48.00614 55.00614 62.00614 65.89814 72.89814 79.89814 83.79014 87.29014 91.95214 104.39814 113.736148 123.84415 133.95215 144.06015 152.61415 161.95215 170.50615 180.61415 185.27616 188.77616 193.43816 198.10016 204.31616 211.31616 218.31616 224.53217 231.53217 237.74817 244.74817 248.24817 258.35618 262.24818 266.14018 273.14018 276.64018 280.53218 287.53218 293.74818 297.24818 304.24818 310.46418 320.57218 324.07218 334.96418 341.96418 345.85618 349.74818 353.64018 360.64018 364.53218 368.42417 374.64018 379.30216 382.80216 389.80216 394.46415 397.96415 404.96415 411.96415 418.96415 425.96415 429.46415 439.57215 443.46415 447.35615 451.24815 454.74815 461.74815 467.96415 471.46415 478.46415">output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48</tspan><tspan y="220.65" x="48.006174 60.45217 70.56017 76.77618">MHz.</tspan><tspan y="245.04999" x="37.100175 48.006177 61.222177 68.222179 74.43818 81.43818 84.93818 91.93818 97.38418 101.27618 108.27618 115.27618 118.77618 124.99218 128.49219 135.49219 142.49219 145.99219 152.99219 159.99219 166.99219 170.49219 177.49219 187.60019 193.8162 197.3162 203.5322 210.5322 214.4242 220.6402 225.3022 232.3022 238.5182 242.4102 245.9102 250.5722 256.7882 261.4502 267.6662 272.3282 278.5442 285.5442 291.7602 297.9762 301.4762 304.9762 308.8682 313.53019 317.03019 320.92219 327.92219 334.13819 337.63819 348.53019 354.7462 361.7462 365.63819 376.53019 383.53019 394.42219 397.92219 408.81419 412.70619 419.70619 423.20619 430.20619 434.09819 441.09819 448.09819 452.76017 457.42216 463.63816 470.63816 477.63816">•When using a 32.768 kHz external reference, if the maximum mid high-range</tspan><tspan y="261.05" x="48.006196 58.114198 67.452198 77.560199 81.060199 85.7222 90.3842 96.600208 103.600208 110.600208 116.81621 123.81621 130.03221 137.03221 140.53221 144.42421 151.42421 157.64022 161.53221 165.03221 171.24822 177.46422 184.46422 187.96422 194.96422 201.18022 204.68022 210.89623 217.11223 224.11223 228.00423 234.22023 241.22023 247.43624 254.43624 257.93623 268.04423 271.93623 275.82823 282.82823 286.32823 292.54423 296.04423 303.04423 310.04423 313.54423 320.54423 327.54423 334.54423 338.04423 345.04423 355.15223 361.36824 364.86824 369.5302 375.74623 380.4082 386.6242 391.2862 397.5022 404.5022 410.7182 416.9342 420.4342 424.3262 429.77223 433.27223 440.27223 446.48823 451.93424 455.82624 460.48823 466.70423 473.70423 477.20423 480.70423 486.15025 492.36625">DCO frequency that can be achieved with a 32.768 kHz reference is desired, set</tspan><tspan y="277.05" x="48.006196 57.344198 64.34419 69.006198 79.1142 88.452198 96.2362 104.7902 111.7902 121.8982 131.2362 139.0202 143.6822 147.1822 154.1822 158.0742 161.9662 167.4122 170.9122 174.8042 181.8042 185.3042 192.3042 194.8242 201.8242 208.8242 215.8242 219.3242 225.5402 232.5402 239.5402 243.0402 248.4862 254.70221 258.5942 262.0942 271.43223 278.43223 283.0942 293.2022 305.64823 315.75624 322.75624 329.75624 334.4182 337.9182 344.9182 348.8102 352.7022 356.2022 360.0942 367.0942 370.5942 377.5942 381.0942 384.5942 393.1482 400.1482 406.3642 409.8642 414.52619 420.7422 426.1882 433.1882 437.0802 440.9722 444.8642 451.8642 458.8642 462.3642 472.4722 481.8102">C4[DRST_DRS] bits to 2'b10 and set C4[DMX32] bit to 1. The resulting DCO</tspan><tspan y="293.05" x="48.006166 55.006166 62.006166 65.89816 72.89816 79.89816 83.79016 87.29016 91.95216 104.39816 113.73616 123.84416 133.95217 144.06017 152.61417 161.95217 170.50617 180.61417 185.27617 188.77617 193.43817 198.10018 204.31618 211.31618 218.31618 224.53218 231.53218 237.74819 244.74819 248.24819 258.35618 262.24818 266.14018 273.14018 276.64018 280.53218 287.53218 293.74818 297.24818 304.24818 310.46418 320.57218 324.07218 334.96418 341.96418 345.85618 349.74818 353.64018 360.64018 364.53218 368.42417 374.64018 379.30216 382.80216 389.80216 394.46415 397.96415 404.96415 411.96415 418.96415 425.96415 429.46415 439.57215 443.46415 447.35615 451.24815 454.74815 461.74815 467.96415 471.46415 478.46415">output (MCGOUTCLK) frequency with the new multiplier of 2197 will be 72</tspan><tspan y="309.05" x="48.006196 60.452196 70.560199 76.7762">MHz.</tspan><tspan y="333.44999" x="37.100206 48.006208 61.222208 68.222209 74.43821 81.43821 84.93821 91.93821 97.38421 101.27621 108.27621 115.27621 118.77621 124.99221 128.49222 135.49222 142.49222 145.99222 152.99222 159.99222 166.99222 170.49222 177.49222 187.60022 193.81623 197.31623 203.53223 210.53223 214.42423 220.64023 225.30223 232.30223 238.51824 242.41024 245.91024 250.57224 256.78825 261.45024 267.66624 272.32823 278.54423 285.54423 291.76023 297.97624 301.47624 304.97624 308.86824 313.5302 317.0302 320.9222 327.9222 334.1382 337.6382 348.5302 354.74623 361.74623 365.6382 376.5302 383.5302 394.4222 397.9222 404.9222 408.8142 415.8142 422.8142 427.4762 432.13819 438.3542 445.3542 452.3542 458.5702 462.0702 472.1782 481.5162">•When using a 32.768 kHz external reference, if the maximum high-range DCO</tspan><tspan y="349.44999" x="48.006227 52.668226 57.330224 63.546224 70.54622 77.54622 83.76222 90.76222 96.978229 103.978229 107.478229 111.370227 118.370227 124.58623 128.47823 131.97823 138.19423 144.41024 151.41024 154.91024 161.91024 168.12624 171.62624 177.84224 184.05825 191.05825 194.95024 201.16625 208.16625 214.38225 221.38225 224.88225 234.99025 238.88225 242.77425 249.77425 253.27425 259.49024 262.99024 269.99024 276.99024 280.49024 287.49024 294.49024 301.49024 304.99024 311.99024 322.09825 328.31425 331.81425 336.47624 342.69224 347.35423 353.57023 358.2322 364.4482 371.4482 377.6642 383.88023 387.38023 391.27223 396.71824 400.21824 407.21824 413.43424 418.88026 422.77226 427.43424 433.65025 440.65025 444.15025 447.65025 453.09626 459.31227">frequency that can be achieved with a 32.768 kHz reference is desired, set</tspan><tspan y="365.44999" x="48.006227 57.344228 64.34422 69.006229 79.11423 88.452228 96.23623 104.79023 111.79023 121.89823 131.23624 139.02024 143.68224 147.18224 154.18224 158.07424 161.96623 167.41223 170.91223 174.80423 181.80423 185.30423 192.30423 194.82424 201.82424 208.82424 215.82424 219.32424 225.54024 232.54024 239.54024 243.04024 248.48624 254.70224 258.59425 262.09425 271.43226 278.43226 283.09425 293.20225 305.64826 315.75627 322.75627 329.75627 334.41825 337.91825 344.91825 348.81025 352.70225 356.20225 360.09425 367.09425 370.59425 377.59425 381.09425 384.59425 393.14823 400.14823 406.36424 409.86424 414.5262 420.74223 426.18824 433.18824 437.08024 440.97224 444.86424 451.86424 458.86424 462.36424 472.47224 481.81025">C4[DRST_DRS] bits to 2'b11 and set C4[DMX32] bit to 1. The resulting DCO</tspan><tspan y="381.44999" x="48.006227 55.006227 62.006227 65.898227 72.898227 79.898227 83.79022 87.29022 91.952228 104.398227 113.73622 123.84422 133.95223 144.06023 152.61423 161.95223 170.50623 180.61423 185.27623 188.77623 193.43824 198.10024 204.31624 211.31624 218.31624 224.53224 231.53224 237.74825 244.74825 248.24825 258.35624 262.24824 266.14024 273.14024 276.64024 280.53224 287.53224 293.74824 297.24824 304.24824 310.46424 320.57225 324.07225 334.96424 341.96424 345.85624 349.74824 353.64024 360.64024 364.53224 368.42424 374.64024 379.30223 382.80223 389.80223 394.4642 397.9642 404.9642 411.9642 418.9642 425.9642 429.4642 439.5722 443.4642 447.3562 451.2482 454.7482 461.7482 467.9642 471.4642 478.4642">output (MCGOUTCLK) frequency with the new multiplier of 2929 will be 96</tspan><tspan y="397.44999" x="48.006227 60.452226 70.56023 76.77623">MHz.</tspan><tspan y="421.84999" x="7.5042345 14.504234 23.996235 37.212236 43.428236 47.320238 51.21224 54.71224 59.374238 66.37424 71.03624 74.53624 78.42824 85.42824 91.64424 95.14424 102.928249 111.48225 120.03625 123.53625 127.428249 134.42826 140.64426 147.64426 151.14426 155.03626 158.92826 169.82025 176.03626 179.53626 183.42826 190.42826 193.92826 200.92826 207.92826 214.14426 218.80626 225.02227 232.02227 235.91426 242.13027 248.34627 251.84627 259.63029 268.18428 276.73826 280.23826 284.13026 289.57627 293.07627 297.73826 304.73826 311.73826 318.73826 322.63026 329.63026 336.63026 340.13026 346.34626 350.23826 353.73826 360.73826 366.95426 377.06227 380.56227 389.90028 396.90028 401.56227 411.67027 421.00828 428.79228 437.34626 444.34626 454.45426 463.79228 471.57627 476.23826 479.73826 485.95426 492.95426">5.Wait for the FLL lock time to guarantee FLL is running at new C4[DRST_DRS] and</tspan><tspan y="437.84999" x="23.996245 33.334245 40.334245 44.996244 55.104246 67.55025 77.65825 84.65825 91.65825 96.32025 99.82025 106.82025 111.482257 118.482257 125.482257 130.14426 136.36026 147.25226 158.14426 164.36026 171.36026 174.86026 179.52227 184.18427 190.40027 197.40027 204.40027 210.61627 217.61627 223.83228 230.83228">C4[DMX32] programmed frequency.</tspan><tspan y="472.24998" x=".00026512147 8.554265 15.554265 19.054265 25.270264 32.270265 38.486265 45.486265 52.486265 58.702264 62.202264 66.864269 71.52627 78.52627 89.41827 92.91827 100.70227 109.25627 113.918277 117.418277 123.63428 127.526279 134.52628 140.74228 147.74228 151.24228 162.13428 169.13428 176.13428 182.35028 185.85028 189.74228 196.74228 200.24228 208.02628 217.36428 222.02628 225.52628 231.74228 235.63428 242.63428 248.85028 255.85028 259.35029 270.24229 277.24229 284.24229 290.45829 293.95829 297.45829 302.12028 309.12028 313.01228 316.90428 323.90428 334.01228 337.51228 341.40428 348.40428 352.29627 357.74229 361.24229 368.24229 372.90428 379.90428 386.12028 392.33628 399.33628 406.33628 410.99827 417.21427">To change from FEI clock mode to FBI clock mode, follow this procedure:</tspan><tspan y="496.64997" x="7.5042555 14.504255 23.996256 33.33426 40.33426 46.55026 53.55026 60.55026 66.76626 70.26626 79.60426 86.60426 91.266269 100.60426 109.158267 119.266269 127.05027 131.71227 135.21227 142.21227 146.10427 149.99626 155.44226 158.94226 162.83426 169.83426 173.33426 182.67226 189.67226 193.17226 197.83426 204.05027 211.05027 214.94226 220.38826 224.28026 230.49626 235.15827 238.65827 242.55027 249.55027 253.05027 260.05027 262.57026 269.57026 276.57026 283.57026 287.07026 292.51628 299.51628 303.01628 306.90827 313.90827 320.12428 324.01628 327.51628 331.40827 338.40827 344.62428 348.12428 352.01628 359.01628 362.90827 369.12428 373.78627 380.78627 387.00227 390.89427 394.39427 399.05625 405.27226 409.93424 416.15025 420.81224 427.02824 434.02824 440.24424 446.46025 449.96025 456.17625 460.06825 467.06825 473.28425 480.28425 483.78425 487.67625">1.Change C1[CLKS] bits in C1 register to 2'b01 so that the internal reference clock is</tspan><tspan y="512.64999" x="23.996296 29.442297 35.6583 39.5503 45.7663 51.9823 55.874303 62.0903 69.0903 72.5903 78.806308 84.252307 87.752307 91.6443 98.6443 104.860309 108.360309 113.806308 120.806308 126.252307 130.1443 136.3603 147.2523 150.7523 156.9683 160.8603 167.8603 174.07631 181.07631 184.57631 190.02231 197.02231 204.02231 208.68431 214.90032 221.11632">selected as the system clock source.</tspan><tspan y="537.0499" x="7.5042955 14.504295 23.996296 37.212297 43.428297 47.320299 51.2123 54.7123 59.3743 66.3743 71.0363 74.5363 82.320308 86.98231 96.32031 104.87431 114.982318 122.76632 131.32032 135.98232 139.48232 146.48232 150.37432 154.26631 159.71231 163.21231 167.10431 174.10431 177.60431 181.4963 188.4963 194.71231 198.21231 210.65831 219.9963 230.10431 233.60431 239.05031 242.9423 249.15831 253.05031 260.0503 265.4963 268.9963 273.6583 279.8743 286.8743 290.7663 296.2123 300.1043 306.3203 310.9823 314.4823 318.3743 325.3743 328.8743 335.0903 342.0903 348.3063 355.3063 362.3063 368.5223 372.0223 375.9143 382.9143 386.4143 393.4143 395.9343 402.9343 409.9343 416.9343 420.4343 423.9343 427.8263 434.8263 441.8263 445.7183 451.9343 458.1503 462.0423 465.9343 472.9343">2.Wait for S[CLKST] bits in the MCG status register to change to 2'b01, indicating</tspan><tspan y="553.0499" x="23.996296 27.888297 34.888299 41.104299 44.9963 48.4963 52.3883 59.3883 65.6043 69.1043 72.9963 79.9963 83.8883 90.1043 94.766307 101.766307 107.98231 111.874309 115.374309 120.03631 126.25231 130.9143 137.13031 141.79232 148.00832 155.00832 161.22432 167.44033 170.94033 177.15633 181.04833 188.04833 194.26433 201.26433 204.76433 211.76433 217.98033 223.42633 226.92633 233.92633 240.14234 246.35834 253.35834 256.85835 263.07435 270.07435 277.07435 281.73634 288.73634 295.73634 300.39833 304.2903 310.50633 314.39833 320.61433 324.50633 331.50633 335.00633 340.45234 346.66835 350.56034 356.77635 362.99235 366.88435 373.10035 380.10035">that the internal reference clock has been appropriately selected.</tspan><tspan y="577.44998" x="7.504307 14.504307 23.996308 37.212308 41.874307 45.766309 49.65831 55.87431 59.37431 63.26631 70.26631 73.76631 77.65831 84.65831 90.87431 94.37431 103.71231 110.71231 114.21231 118.87431 125.09032 132.09032 135.98232 141.42832 145.32032 151.53632 156.19832 159.69832 163.59032 170.59032 174.09032 181.09032 187.30632 191.19832 197.41432 202.07633 212.96833 216.86032 223.86032 230.07633 233.57633 237.46833 244.46833 250.68433 254.18433 258.8463 268.18434 277.52235 285.30635 288.80635 295.80635 302.80635 306.69834 313.69834 320.69834 324.59034 328.09034 332.75233 337.4143 346.75233 356.09034 363.87434 373.21235 381.76634 391.87434 396.53633 400.03633 404.6983 409.3603 415.5763 422.5763 429.5763 435.7923 442.7923 449.0083 456.0083 459.5083 464.1703 470.3863 477.3863 484.3863 490.6023">3.Write to the C2 register to determine the IRCS output (IRCSCLK) frequency range.</tspan><tspan y="601.85" x="37.10032 48.00632 57.344324 64.34432 67.84432 74.84432 81.060329 85.72233 91.93833 98.93833 102.83033 106.72233 110.22233 113.72233 123.83033 127.72233 131.61434 138.61434 142.11434 151.45233 158.45233 163.11434 167.77634 177.11434 186.45233 194.23633 198.89833 202.39833 208.61434 212.50634 218.72234 224.93834 229.60034 235.81635 242.81635 246.31635 250.20835 257.20835 260.70835 267.70835 271.20835 274.70835 278.60035 285.60035 291.81636 295.31636 299.97834 309.31636 318.65437 326.43836 329.93836 335.38438 341.60038 345.49238 351.70838 357.92439 361.81639 368.03239 375.03239 378.53239 385.53239 392.53239 396.42439 403.42439 410.42439 414.31639 417.81639 424.03239 427.92439 434.92439 441.14039 448.14039 451.64039 455.53239 460.9784 464.4784 468.3704 475.3704">•By default, with C2[IRCS] cleared to 0, the IRCS selected output clock is the</tspan><tspan y="617.85" x="48.00631 53.45231 57.34431 64.344318 74.45232 77.95232 81.844318 88.844318 92.73631 98.95232 103.61432 110.61432 116.83032 120.72232 124.22232 128.88433 135.10033 139.76233 145.97834 150.64034 156.85634 163.85634 170.07234 176.28835 179.78835 186.00435 189.89635 196.89635 203.11235 210.11235 213.61235 218.27436 225.27436 232.27436 235.77436 242.77436 252.88236 259.09837 262.59837 267.26036 276.59837 285.93638 290.59837 294.09837 297.59837 302.26036 306.92234 310.42234 314.31434 321.31434 327.53034 331.03034 335.69233 341.90834 347.35435 351.24635 357.46235 362.12434 365.62434 370.28633 379.62434 388.96235 392.46235 396.35435 401.80036 405.30036 412.30036 418.51637 423.96238 427.85438 432.51637 438.73237 445.73237 449.23237 452.73237 458.17839 464.39439">slow internal reference clock (32 kHz IRC). If the faster IRC is desired, set</tspan><tspan y="633.85" x="48.00631 57.34431 64.344318 69.00632 73.66832 83.00632 92.344318 100.12832 104.79032 108.29032 115.29032 119.18232 123.07432 126.57432 130.46633 137.46633 140.96633 147.96633 151.46633 156.12833 163.12833 167.79033 171.29033 177.50634 181.00634 185.66834 195.00634 204.34433 212.12833 215.62833 221.84433 225.73633 232.73633 238.95233 245.95233 249.45233 256.45234 262.66835 267.33033 271.22233 278.22233 284.43833 291.43833 294.93833 299.6003 304.2623 311.2623 322.1543 325.6543 329.5463 336.5463 342.7623 346.2623 353.2623 356.7623 369.2083 379.3163 385.53233 389.03233 393.6943 403.03233 412.37034 415.87034 421.31636 428.31636 435.31636 439.97834 446.19435 452.41035">C2[IRCS] bit to 1 for a IRCS clock derived from the 4 MHz IRC source.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 18)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="25.87323" x="0 2.5020004 8.001 10.503 13.5 16.002 21.006 23.508002 26.010003 30.510003 35.514005 38.511007 41.013006 46.512006 52.011007 54.513006 57.015005 59.517004 66.015 71.514 77.013 79.515 82.017 87.020999 92.024997 95.021999 97.523998 103.022998 108.521999 111.023998 113.52599 119.024997 122.021999 127.520999 131.022 139.02301 144.02701 147.024 149.526 155.025">Initialization / Application information</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 734.93869)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="130.014 137.23401 142.794 148.354 151.134 157.804 163.914 170.024 173.354 179.464 185.024 193.914 196.694 199.474 205.034 207.814 215.034 220.594 223.924 229.484 233.374 238.93399 245.04399 250.60399 256.164 258.944 267.274 272.83399 278.94398 285.05397 290.61396 293.39396 296.17396 298.95396 306.17396 311.73396 317.29396 320.07395 322.85395 328.41395 331.19395 336.75395 342.86393 348.9739 351.7539 357.3139 362.8739 368.4339">K60 Sub-Family Reference Manual, Rev. 2 Jun 2012</tspan></text>
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