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Ryan Malloy 5252d1d73c Add hardware reference docs (A3981, K60, RYS352A) 
Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint,
3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep.

NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference
manual. Cortex-M4 96MHz MCU running the G2 firmware.

Reyax RYS352A GPS module: datasheet and PAIR command guide.
GPS receiver on the G2 board (used for auto-location/satellite lookup).

All extracted as markdown + page images + vector SVGs for LLM context.
Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.
2026-02-14 18:36:42 -07:00

111 lines
34 KiB (Stored with Git LFS)
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Raw Blame History

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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="11.85" x="0 8.554 15.554 19.054 25.27 32.27 38.486 45.486 52.486 58.702 62.202 66.864 71.526 78.526 89.418 92.918 100.702 109.256008 113.91801 117.41801 128.31002 135.31002 142.31002 148.52602 152.02602 155.91802 162.91802 166.41802 174.20201 182.75601 191.31002 194.81002 201.81002 206.47202 209.97202 217.75601 227.09401 235.64801 239.14801 250.04001 257.04 264.04 270.256 275.70204 279.20204 282.70204 287.364 294.364 298.256 302.148 309.148 319.256 322.756 326.648 333.648 337.54 342.98603 346.48603 353.48603 358.148 365.148 371.364 377.58003 384.58003 391.58003 396.242 402.458">To change from FEI mode to FEE or FBE modes, follow this procedure:</tspan><tspan y="36.25" x="7.50402 14.504021 23.996022 32.550024 39.550024 45.76602 52.76602 56.658025 62.874025 66.37402 70.26602 77.26602 83.482028 86.982028 93.19803 100.19803 104.09003 110.30603 114.96803 121.96803 128.18404 132.07604 135.57604 141.79204 145.68404 152.68404 158.90004 165.90004 169.40004 174.84604 181.84604 188.84604 193.50804 199.72405 205.94005 209.44005 216.44005 223.44005 226.94005 232.38605 238.60205 242.49405 246.38605 250.27805 257.27806 264.27806 267.77806 271.67005 278.67005 284.88606 288.38606 294.60206 301.60206 308.60206 313.26405 320.26405 327.26405 331.92604 335.81803 342.03404 345.92604 352.14204 355.64204 362.64204 366.53404 370.42604 375.87205 379.37205 383.26405 390.26405 393.76405 403.10206 410.10206 413.60206 418.26405 424.48005 431.48005 435.37205 440.81806 444.71006 450.92607 455.58805">1.Enable the external clock source by setting the appropriate bits in C2 register.</tspan><tspan y="60.65" x="7.5040504 14.50405 23.996052 37.21205 41.87405 45.766054 49.658056 55.874055 59.374055 63.266057 70.26605 73.76605 83.10405 90.10405 93.60405 98.26605 104.482059 111.482059 115.374057 120.82005 124.71205 130.92806 135.59006 139.09006 142.98206 149.98206 153.48206 158.92806 165.14406 169.03606 175.25206 181.46807 185.36006 188.86006 192.75206 199.75206 205.96807 209.46807 215.68407 219.57607 226.57607 232.79207 239.79207 243.29207 254.18407 261.18409 268.18409 274.4001">2.Write to C1 register to select the clock mode.</tspan><tspan y="85.05" x="37.10003 48.00603 52.66803 57.33003 60.83003 67.04603 74.04603 77.93803 84.15403 88.81603 92.70803 99.70803 106.70803 110.20803 117.992038 126.546039 135.10004 138.60004 149.49204 156.49204 163.49204 169.70804 173.20804 176.70804 182.15404 188.37004 192.26204 195.76204 205.10004 212.10004 216.76204 224.54604 233.88404 243.99204 248.65404 258.76203 263.424 266.924 273.14 280.14 287.14 291.802 298.802 305.802 310.464 314.356 320.572 324.464 330.68 334.572 341.572 345.072 348.572 354.788 358.68 364.896 371.112 375.774 379.274 383.166 390.166 396.382 399.882 409.22 416.22 420.882 425.54399 434.882 443.43598 451.21998 459.00398 463.66596 467.16596 474.16596 478.05796 481.94996 485.44996 489.34196">&#x2022;If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit to</tspan><tspan y="101.05" x="48.00602 53.45202 63.56002 67.45202 71.34402 77.56002 84.56002 88.06002 91.95202 98.95202 102.45202 106.34402 113.34402 119.56002 123.06002 129.27602 136.27602 140.16802 146.38402 151.04602 158.04602 164.26203 168.15402 171.65402 176.31603 182.53203 187.19403 193.41004 198.07204 204.28804 211.28804 217.50405 223.72005 227.22005 230.72005 236.93605 243.93605 250.93605 254.43605 258.32807 264.54408 270.76008 277.76008 283.97608 287.47608 291.36808 298.36808 304.58409 308.08409 317.4221 324.4221 329.08409 338.4221 346.97608 357.08409 364.86808 369.53007 373.03007 380.03007 383.92207 387.81407 393.26008 396.76008 402.97608 406.86808 410.36808 417.36808 419.88807 426.88807 433.88807 440.88807 444.38807 449.83409 456.83409 460.33409 464.22608 471.22608 477.44209 481.33409 484.83409 488.72608 495.72608">switch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that the</tspan><tspan y="117.05" x="48.00605 55.00605 62.00605 65.89805 72.89805 79.89805 83.79005 87.29005 94.29005 98.95205 102.45205 106.34405 113.34405 119.56005 123.06005 130.84406 139.39806 147.95206 151.45206 155.34406 160.79006 164.29006 169.73606 175.95206 179.84406 186.06006 192.27606 196.16806 202.38407 209.38407 212.88407 219.10007 224.54607 228.04607 231.93807 238.93807 245.15407 248.65407 254.10007 261.10008 266.54609 270.43809 276.65409 287.54609 291.04609 297.2621 301.15409 308.15409 314.3701 321.3701 324.8701 330.3161 337.3161 344.3161 348.9781 355.1941 361.4101">output of the FLL is selected as the system clock source.</tspan><tspan y="141.45001" x="37.10003 48.00603 52.66803 57.33003 60.83003 67.04603 74.04603 77.93803 84.15403 88.81603 92.70803 99.70803 106.70803 110.20803 117.992038 127.33003 135.88404 139.38404 142.88404 149.10004 152.99204 159.20804 165.42404 170.08605 173.58605 177.47805 184.47805 190.69405 194.19405 203.53205 210.53205 215.19405 219.85605 229.19405 237.74805 245.53205 253.31604 257.97804 261.47804 268.47804 272.37004 276.26203 279.76203 283.65403 290.65403 294.15403 299.60005 309.70805 313.60005 317.49205 323.70805 330.70805 334.20805 338.10005 345.10005 348.60005 352.49205 359.49205 365.70805 369.20805 375.42405 382.42405 386.31605 392.53205 397.19404 404.19404 410.41004 414.30204 417.80204 422.46403 428.68003 433.342 439.558 444.22 450.436 457.436 463.652 469.868 473.368 479.584 486.584">&#x2022;If entering FBE, clear the C1[IREFS] bit to switch to the external reference and</tspan><tspan y="157.45001" x="48.00602 54.22202 61.22202 67.43802 74.43802 81.43802 87.65402 91.15402 95.04602 102.04602 108.262027 111.762027 121.10002 128.10002 132.76203 142.10002 150.65402 160.76203 168.54602 173.20803 176.70803 183.70803 187.60002 191.49202 196.93802 200.43802 204.33002 211.33002 214.83002 221.83002 224.35002 231.35002 238.35002 245.35002 248.85002 254.29602 261.29603 264.79603 268.68803 275.68803 281.90403 285.79603 289.29603 293.18803 300.18803 306.40403 309.90403 316.12004 323.12004 327.01203 333.22804 337.89 344.89 351.10603 354.99803 358.49803 363.16 369.376 374.038 380.254 384.916 391.132 398.132 404.348 410.564 414.064 420.28 424.172 431.172 437.388 444.388 447.888 451.78">change the C1[CLKS] bits to 2'b10 so that the external reference clock is</tspan><tspan y="173.45001" x="48.00602 53.45202 59.66802 63.56002 69.776027 75.99203 79.884029 86.10003 93.10003 96.60003 102.81603 108.26203 111.76203 115.65403 122.65403 128.87003 132.37003 137.81603 144.81603 150.26203 154.15402 160.37003 171.26203 174.76203 180.97803 184.87003 191.87003 198.08603 205.08603 208.58603 214.03203 221.03203 228.03203 232.69403 238.91004 245.12604 248.62604 252.12604 260.68003 267.68003 273.89604 277.39604 286.73405 293.73405 298.39604 306.18003 315.51805 325.62605 330.28804 340.39604 345.058 348.558 355.558 359.45 363.342 368.78804 372.28804 377.73405 384.73405 391.73405 398.73405 402.62605 409.62605 413.12605 419.34205 423.23405 428.68006 435.68006 439.18006 446.18006 452.39607 455.89607 461.34208 467.55809">selected as the system clock source. The C1[FRDIV] bits should also be set</tspan><tspan y="189.45001" x="48.00602 54.22202 61.22202 68.222019 72.88402 79.88402 86.88402 91.54602 95.43802 101.65402 105.54602 111.762027 115.65402 122.65402 126.15402 133.15402 139.37003 144.03203 150.24803 153.74803 159.96404 166.18004 172.39604 179.39604 184.05805 191.05805 194.95005 201.95005 208.95005 212.45005 216.34204 223.34204 226.84204 230.73404 237.73404 243.95005 247.45005 253.66605 260.66606 264.55805 270.77406 275.43605 282.43605 288.65205 292.54405 296.04405 300.70603 306.92204 311.584 317.80003 322.462 328.678 335.678 341.894 348.11003 351.61003 356.272 360.934 367.15 374.15 381.15 387.366 394.366 400.582 407.582 411.082 414.974 421.974 425.474 432.474 438.69 444.906 451.906 455.406 459.298 466.298 472.514 476.014 483.798 492.352">appropriately here according to the external reference frequency to keep the FLL</tspan><tspan y="205.45001" x="48.00602 52.66802 58.884019 63.546018 69.76202 74.42402 80.64002 87.64002 93.856029 100.07203 103.57203 109.78803 113.68003 120.68003 126.896038 133.89603 137.39603 141.28803 148.28803 151.78803 155.68003 162.68003 168.89603 172.39603 177.05803 183.27404 190.27404 197.27404 203.49004 206.99004 213.99004 218.65204 222.15204 229.15204 236.15204 239.65204 246.65204 253.65204 257.15205 264.15205 274.26005 280.47605 283.97605 287.86805 294.86805 298.36805 305.36805 312.36805 315.86805 322.86805 329.86805 336.86805 343.86805 347.36805 354.36805 364.47605 370.69206 374.19206 377.69206 387.80006 391.69206 395.58406 402.58406 409.58406 416.58406 423.58406 430.58406 434.08406 437.97605 444.97605 451.19206 454.69206 462.47605 471.03004 479.584 483.084 486.976">reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is</tspan><tspan y="221.45001" x="48.00602 55.00602 62.00602 69.00602 75.22202 80.66802 86.11402 92.330028 99.330028 102.830028 106.330028 110.22202 114.11402 117.61402 121.50602 126.95202 130.45203 135.89803 139.79003 143.68202 147.57402 151.46602 154.96602 161.96602 168.96602 172.46602 176.35802 183.35802 186.85802 194.64202 203.98001 212.53401 216.03401 226.92601 233.92601 240.92601 247.14202">bypassed, it is still on in FBE mode.</tspan><tspan y="245.85" x="37.10003 48.00603 56.56003 63.56003 69.77603 73.27603 77.16803 84.16803 88.06003 94.27603 98.938037 105.938037 112.15404 116.046039 119.546039 124.20804 130.42404 135.08605 141.30205 145.96405 152.18006 159.18006 165.39606 171.61206 175.11206 181.32807 187.54407 194.54407 198.04407 205.04407 212.04407 215.93607 219.82807 226.82807 233.82807 240.04407 243.93607 247.82807 254.82807 258.32807 265.32807 271.54408 275.04408 282.04408 288.26008 295.26008 299.15208 302.65208 307.31407 314.31407 321.31407 328.31407 332.20606 339.20606 346.20606 349.70606 356.70606 363.70606 367.20606 372.65208 378.86808 382.76008 386.65208 390.54408 397.54408 404.54408 408.04408 411.93608 418.93608">&#x2022;The internal reference can optionally be kept running by setting the</tspan><tspan y="261.85" x="48.00602 57.34402 64.344028 69.00603 73.66803 83.00603 92.344028 100.898029 111.00603 119.56003 129.66803 134.33003 137.83003 144.83003 148.72203 152.61403 156.11403 159.61403 168.16803 175.16803 179.06003 184.50603 188.00603 191.89803 197.34403 200.84403 207.84403 213.29003 219.50603 224.16803 231.16803 235.06003 238.56003 242.45203 247.11403 250.61403 254.50603 261.50605 267.72206 271.22206 277.43806 284.43806 291.43806 295.33006 299.22206 305.43806 311.65406 315.54606 319.43806 326.43806 333.43806 336.93806 347.04606 350.93806 354.83006 358.72206 362.22206 367.66807 377.77607 381.66807 385.56007 391.77607 398.77607 402.27607 409.27607 415.49208 421.70808 428.70808 432.20808 438.42408 445.42408 452.42408 455.92408 460.58607 467.58607 472.24806 476.14006">C1[IRCLKEN] bit. This is useful if the application will switch back and forth</tspan><tspan y="277.85" x="48.00602 55.00602 61.22202 65.11402 75.22202 81.43803 87.65403 94.65403 98.15403 102.04603 109.04603 112.93803 119.15403 123.81603 130.81604 137.03205 140.92404 144.42404 150.64005 157.64005 164.64005 168.14005 174.35605 181.35605 185.24805 191.46405 196.12606 203.12606 209.34206 213.23406 216.73406 227.62606 234.62606 241.62606 247.84206 253.28806 256.78807 260.28807 268.07206 275.07206 279.73405 283.23405 294.12605 298.01805 305.01805 308.91004 319.80204 326.80204 337.69404 341.19404 348.19404 355.19404 365.30204 371.51805 376.18003 379.68003 385.89604 392.89604 399.89604 405.34205 412.34205 423.23405 430.23405 434.12605 438.01805 445.01805 452.01805 455.51805 459.01805 462.91004 469.12605 475.34205 482.34205">between internal and external modes. For minimum power consumption, leave</tspan><tspan y="293.85" x="48.00602 51.89802 58.89802 65.11402 68.61402 72.50602 79.50602 83.39802 89.61402 94.276027 101.276027 107.49203 111.384029 114.884029 119.54603 125.76203 130.42403 136.64003 141.30204 147.51804 154.51804 160.73404 166.95005 170.45005 177.45005 181.34204 186.78804 193.00405 200.00405 203.89604 210.11205 217.11205 220.61205 230.72005 237.72005 241.61205 245.50405 251.72005 255.22005 259.11207 266.11207 269.61207 275.82807 282.82807 286.32807 292.54408 299.54408 303.43608 309.65208 314.31407 321.31407 327.53007 331.42207 334.92207 341.13807 345.03007 352.03007 358.24607 365.24607 368.74607 379.63807 386.63807 393.63807 399.85408">the internal reference disabled while in an external clock mode.</tspan><tspan y="318.24998" x="7.5040209 14.504021 23.996022 34.104024 41.104024 47.320024 53.536024 57.036024 60.928026 67.928028 74.14403 77.64403 84.64403 89.30603 96.30603 103.30603 109.52203 114.18404 117.68404 123.90004 130.90004 137.90004 142.56204 146.45404 153.45404 160.45404 165.11605 171.33205 175.22405 179.11605 186.11605 193.11605 196.61605 203.61605 207.50804 211.40004 216.84604 220.34604 227.34604 233.56204 240.56204 246.77805 250.27805 257.27806 263.49406 269.71006 276.71006 280.21006 285.65608 291.87208 295.76408 299.26408 302.76408 312.87208 319.08808 322.98008 326.87208 330.37208 335.03407 342.03407 346.69606 350.19606 354.08805 361.08805 367.30406 370.80406 377.02006 381.68205 386.34403 392.56004 398.77604 402.66804 408.88404 415.88404 419.38404 426.38404 430.27604 434.16804 439.61405 443.11405 447.00605 454.00605 457.50605 461.39805 468.39805">3.Once the proper configuration bits have been set, wait for the affected bits in the</tspan><tspan y="334.24998" x="23.996062 36.442064 45.780065 55.888067 59.388067 64.83407 68.72607 74.94207 78.83407 85.83407 91.28007 94.78007 99.44207 105.65807 112.65807 116.55007 121.99607 125.88807 132.10407 136.76607 140.26607 144.15807 151.15807 154.65807 161.65807 167.87407 171.37407 177.59008 184.59008 190.80608 197.80608 204.80608 211.02208 218.02208 221.52208 227.73809 234.73809 241.73809 246.40009 253.40009 260.4001 265.06208 268.95408 275.17008 279.06208 285.27809 289.17008 296.17008 299.67008 303.17008 307.83207 314.04808 318.71006 322.60206 328.81806 335.03407 338.92607 342.81806 349.81806 356.81806 360.31806 364.21006 371.21006 377.42607 381.31806 384.81806 388.71006 395.71006 401.92607 405.42607 417.87208 427.21009 437.31809 440.81809 447.81809 454.0341 459.4801 462.9801 473.8721 480.8721 487.8721 494.0881">MCG status register to be changed appropriately, reflecting that the MCG has moved</tspan><tspan y="350.24998" x="23.996062 27.888062 34.88806 38.780065 45.780065 49.280065 53.172067 60.172067 66.38807 69.88807 76.88807 81.55007 88.55007 95.55007 101.766078 106.42808 109.92808 120.820079 127.820079 134.82007 141.03607">into the proper mode.</tspan><tspan y="374.64997" x="37.10007 48.006074 52.66807 57.33007 60.83007 64.72207 71.72207 77.93807 81.43807 93.88407 103.22208 113.33008 116.83008 120.72208 126.168079 129.66808 133.56008 140.56008 144.06008 151.84407 160.39807 168.95207 172.45207 175.95207 183.73607 193.07407 201.62807 205.12807 208.62807 216.41207 224.96607 233.52007 237.02007 240.52007 248.30406 257.64207 266.19606 269.69606 273.19606 280.19606 284.85804 288.35804 297.69606 306.25004 314.03404 322.588 326.088 336.98 343.98 350.98 357.196 360.696 364.196 370.41203 377.41203 384.41203 387.91203 397.25004 404.25004 408.91203 417.466 426.80403 435.358 443.142 450.926 457.926 462.58799 466.08799 476.19599 482.412">&#x2022;If the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and C2[EREFS0] was</tspan><tspan y="390.64997" x="48.006093 54.22209 58.114095 63.560094 70.56009 74.06009 79.50609 85.72209 89.61409 93.11409 97.00609 104.00609 107.50609 112.95209 116.844089 123.06009 130.06009 133.56009 140.56009 144.06009 147.56009 157.66809 163.8841 167.7761 171.66809 175.16809 182.16809 188.3841 193.0461 199.2621 202.7621 207.4241 214.4241 219.0861 222.5861 230.3701 235.0321 245.1401 252.9241 262.26213 266.9241 277.0321 281.6941 290.24809 297.24809 301.91007 305.41007 312.41007 316.30207 320.19407 323.69407 327.58607 334.58607 338.08607 345.08607 351.30207 357.51808 364.51808 375.41007 381.62608 385.12608 390.57209 396.7881 400.68009 404.18009 408.07209 415.07209 422.07209 425.96409 432.18009 438.3961 442.2881 446.18009 453.18009 460.18009 463.68009 467.57209 474.57209 480.7881">also set in step 1, wait here for S[OSCINIT0] bit to become set indicating that</tspan><tspan y="406.64997" x="48.006124 51.898126 58.898126 65.11413 68.61413 74.83013 81.83013 85.72213 91.93813 96.600139 103.600139 109.81614 113.70814 117.20814 123.42414 127.31614 134.31613 140.53214 147.53214 151.03214 156.47814 163.47814 170.47814 175.14014 181.35614 187.57215 191.07215 198.07215 204.28815 209.73415 213.23415 217.89615 221.78815 228.78815 232.68015 238.12615 245.12615 251.34215 258.34217 261.84217 265.73417 269.62617 275.07218 278.57218 282.46418 289.46418 293.35618 297.24818 301.14018 307.35618 311.24818 315.14018 321.35618 327.57218 331.46418 335.35618 342.35618 349.35618 352.85618 359.07218 366.07218 372.28819 376.18019 382.39619 387.8422 391.3422 397.5582 404.5582 411.5582 415.0582 420.5042 424.3962 430.6122 437.6122 441.5042 445.3962 449.2882 455.5042 461.7202 468.7202">the external clock source has finished its initialization cycles and stabilized.</tspan><tspan y="431.04997" x="37.100133 48.006135 52.668134 57.33013 60.83013 64.72213 71.72213 75.22213 83.006137 91.560138 100.114139 103.614139 114.506137 121.506137 128.50614 134.72214 138.22214 141.72214 147.93814 154.93814 161.15415 167.37015 174.37015 177.87015 181.76215 188.76215 192.26215 203.15415 209.37015 216.37015 222.58615 226.08615 231.53215 238.53215 243.19416 249.41016 252.91016 256.80216 263.80216 270.01817 273.51817 281.30216 285.96415 290.62614 299.96415 308.51814 316.30213 324.08613 332.6401 337.3021 340.8021 347.8021 351.6941 355.5861 359.0861 362.9781 368.4241 371.9241 378.1401 382.0321 388.2481 394.4641 399.1261 405.3421 412.3421 415.8421 422.8421 429.0581 433.7201 440.7201 445.38209 451.59809 455.09809 465.99009 472.99009 479.99009 483.88209 490.88209">&#x2022;If in FEE mode, check to make sure the S[IREFST] bit is cleared before moving</tspan><tspan y="447.04997" x="48.006155 55.006155 62.006155">on.</tspan><tspan y="471.44996" x="37.10015 48.006155 52.66815 57.33015 60.83015 64.72215 71.72215 75.22215 83.00616 92.34416 100.89816 104.39816 115.29016 122.29016 129.29016 135.50617 139.00617 142.50617 148.72217 155.72217 161.93817 168.15418 175.15418 178.65418 182.54618 189.54618 193.04618 203.93817 210.15418 217.15418 223.37018 226.87018 232.31618 239.31618 243.97818 250.19419 253.69419 257.58619 264.58619 270.8022 274.3022 282.08619 286.74818 291.41017 300.74818 309.30216 317.08616 324.87016 333.42414 338.08613 341.58613 348.58613 352.47813 356.37013 359.87013 363.76213 369.20814 372.70814 378.92414 382.81614 389.03215 395.24815 399.91014 406.12614 413.12614 416.62614 422.84214 429.84214 436.84214 440.34214 448.12614 452.78813 462.12614 470.6801 480.78813 488.5721 497.1261">&#x2022;If in FBE mode, check to make sure the S[IREFST] bit is cleared and S[CLKST]</tspan><tspan y="487.44996" x="48.00618 55.00618 58.898183 62.790185 68.23618 71.73618 78.73618 84.95219 91.95219 98.16819 101.66819 107.88419 114.88419 121.1002 128.10019 135.10019 141.3162 148.3162 151.8162 155.70819 162.70819 166.20819 173.20819 175.7282 182.7282 189.7282 196.7282 200.2282 204.1202 211.1202 218.1202 222.01219 228.2282 234.4442 238.3362 242.2282 249.2282 256.2282 259.7282 263.6202 270.6202 276.8362 280.3362 286.55223 293.55223 297.4442 303.66023 308.3222 315.3222 321.5382 325.4302 328.9302 333.5922 339.8082 344.47019 350.6862 355.34819 361.56419 368.56419 374.78019 380.9962 384.4962 390.7122 394.6042 401.6042 407.8202 414.8202 418.3202 425.3202 431.5362 436.9822 440.4822 447.4822 453.6982 459.9142">bits have changed to 2'b10 indicating the external reference clock has been</tspan><tspan y="503.44996" x="48.00618 54.22218 61.22218 68.22218 72.884189 79.884189 86.884189 91.54619 95.43819 101.65419 105.54619 111.76219 115.65419 122.65419 126.15419 131.60019 137.8162 141.70819 147.9242 154.1402 158.0322 164.2482 171.2482 174.7482 178.2482 188.3562 192.2482 196.1402 203.1402 210.1402 217.1402 224.1402 231.1402 234.6402 238.5322 245.5322 251.7482 255.2482 263.0322 271.58619 280.14018 283.64018 287.53218 292.97819 296.47819 303.47819 310.47819 317.47819 323.69419 329.1402 334.5862 340.80223 347.80223 351.30223 354.80223 358.6942 362.5862 366.0862 369.9782 375.42424 378.92424 384.37025 388.26225 392.15425 396.04624 399.93824 403.43824 410.43824 417.43824 420.93824 424.83024 431.83024 435.33024 443.11424 452.45225 461.00624 464.50624 475.39823 482.39823 489.39823 495.61424">appropriately selected. Although the FLL is bypassed, it is still on in FBE mode.</tspan><tspan y="527.8499" x="7.504158 14.504158 23.996159 37.21216 41.874158 45.76616 49.65816 55.87416 59.37416 63.266164 70.26616 73.76616 77.65816 84.65816 90.87416 94.37416 103.71216 110.71216 114.21216 118.87416 125.090167 132.09017 135.98217 141.42816 145.32016 151.53617 156.19817 159.69817 163.59017 170.59017 174.09017 181.09017 187.30617 191.19817 197.41417 202.07617 212.96817 216.86017 223.86017 230.07617 233.57617 237.46817 244.46817 250.68418 254.18418 264.29219 273.6302 283.7382 287.2382 294.2382 301.2382 305.1302 312.1302 319.1302 323.0222 326.5222 331.18418 343.6302 352.9682 363.0762 370.8602 379.41419 387.96818 397.30619 405.86018 415.96818 420.63017 424.13017 428.79216 433.45414 439.67015 446.67015 453.67015 459.88615 466.88615 473.10215">4.Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency</tspan><tspan y="543.8499" x="23.996148 28.658148 34.87415 41.87415 48.87415 55.09015">range.</tspan><tspan y="568.24996" x="37.100149 48.00615 57.34415 64.34415 67.84415 74.84415 81.06015 85.72215 91.938159 98.938159 102.830158 106.72215 110.22215 113.72215 123.830158 127.72215 131.61415 138.61415 142.11415 151.45215 158.45215 163.11415 173.22216 185.66815 195.77616 202.77616 209.77616 214.43816 217.93816 224.15416 228.04616 234.26216 240.47817 245.14017 251.35617 258.35618 261.85618 265.74818 272.74818 276.24818 283.24818 286.74818 290.24818 294.14018 301.14018 307.35618 310.85618 318.64018 327.19416 335.74815 339.24815 350.14015 357.14015 361.03215 364.92414 368.81614 375.81614 379.70814 383.60014 389.81614 394.47813 397.97813 402.6401 409.6401 414.3021 417.8021 421.6941 428.6941 434.9101 438.4101 448.5181 457.8561">&#x2022;By default, with C4[DMX32] cleared to 0, the FLL multiplier for the DCO</tspan><tspan y="584.24996" x="48.006158 55.006158 62.006158 65.898159 72.898159 79.898159 83.79015 87.29015 91.18215 96.62815 100.12815 107.12815 114.12815 121.12815 124.62815 128.12815 135.91214 142.91214 147.57415 151.07415 158.07415 162.73615 168.95215 175.16815 179.06015 185.27616 189.93816 193.43816 198.10016 201.99216 208.20816 215.20816 219.10016 226.10016 229.99216 233.88416 237.77616 241.66815 248.66815 252.16815 255.66815 259.56016 264.22215 267.72215 273.93815 277.43815 288.33015 292.22215 299.22215 303.88414 307.77613 314.77613 324.88414 329.5461 334.2081 340.4241 347.4241 354.4241 360.6401 364.1401 371.9241 380.4781 389.03208 392.53208 403.42408 410.42408 414.31608 418.20808 422.10008 429.10008 432.99208 436.88407 443.10008 447.76206 451.26206 458.26206 462.92405 466.42405 473.42405 480.42405 487.42405">output is 640. For greater flexibility, if a mid-low-range FLL multiplier of 1280</tspan><tspan y="600.24996" x="48.006189 51.89819 57.34419 60.84419 67.84419 74.060199 79.506198 83.39819 88.060199 94.2762 101.2762 104.7762 108.6682 115.6682 121.1142 125.006198 131.2222 137.4382 144.4382 147.9382 151.4382 156.8842 163.1002 166.9922 170.4922 179.8302 186.8302 191.4922 201.6002 210.9382 218.7222 227.2762 234.2762 244.3842 253.7222 261.5062 266.16819 269.66819 276.66819 280.56019 284.45219 289.8982 293.3982 297.2902 304.2902 307.7902 314.7902 317.31019 324.31019 331.31019 338.31019 341.81019 346.47218 353.47218 358.13417 361.63417 367.85017 371.35017 381.45817 390.79618 400.90419 404.40419 411.40419 418.40419 422.29618 429.29618 436.29618 440.18818 443.68818 448.35017 453.01216 459.22816 466.22816 473.22816 479.44416 486.44416 492.66017">is desired instead, set C4[DRST_DRS] bits to 2'b01 for a DCO output frequency</tspan><tspan y="616.24996" x="48.006189 55.006189 59.668188 63.168188 70.16818 77.16818 80.66818 93.11418 103.22218 109.43819 112.93819 116.43819 121.10019 125.76219 129.26219 135.4782 138.9782 149.8702 153.76219 160.76219 164.26219 171.26219 175.15419 182.15419 189.15419 193.8162 198.4782 204.6942 211.6942 218.6942 224.9102 228.4102 236.1942 244.7482 253.3022 256.8022 267.69419 274.69419 278.58619 282.47819 286.37019 293.37019 297.26219 301.15419 307.37019 312.03218 315.53218 322.53218 327.19416 330.69416 337.69416 344.69416 351.69416 358.69416 362.19416 366.08616 371.53218 375.03218 382.03218 388.24818 393.69419 397.58619 402.24818 408.46418 415.46418 418.96418 422.85618 429.85618 435.3022 439.19419 445.4102 451.6262 458.6262 462.1262 465.6262 471.0722 477.2882 481.1802 484.6802 488.5722 495.5722">of 40 MHz. If a mid high-range FLL multiplier of 1920 is desired instead, set the</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 18)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="26.01031" x="296.469 302.96699 308.46598 313.46998 318.96897 321.96598 326.96998 330.47099 332.973 337.977 342.981 345.483 352.98 358.479 360.98103 363.97804 366.48005 371.97904 377.47804 380.97904 386.47804 391.97703 396.98103 401.98503 404.48704 410.98503 413.48704 418.98603 423.99003 428.99403 431.49604 438.49806 443.50205 449.00105 454.00505 457.50605 462.51005 465.50706 471.00605 474.50706 477.00907 480.00608 487.50309 494.00108 501.00309">Chapter 25 Multipurpose Clock Generator (MCG)</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 734.93869)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="130.01 137.23 142.79 148.34999 151.12999 157.79999 163.90999 170.01999 173.34999 179.45999 185.01999 193.90999 196.68999 199.46999 205.02999 207.80998 215.02999 220.58998 223.91999 229.47998 233.36998 238.92998 245.03998 250.59998 256.15998 258.93998 267.26997 272.82997 278.93995 285.04994 290.60993 293.38993 296.16993 298.94993 306.16993 311.72993 317.28993 320.06993 322.8499 328.4099 331.1899 336.7499 342.8599 348.96989 351.74989 357.30989 362.86988 368.42988">K60 Sub-Family Reference Manual, Rev. 2 Jun 2012</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 751.756)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x=".00401 5.5030105 8.5000109 13.504011 18.50801 23.00801 27.50801 32.512014 34.510015 39.514017 42.016016 48.019014 53.023015 60.520017 62.518018 67.01802 72.02202 77.02602 82.030017 87.03401 91.53401 94.03601 99.04001 102.03701 104.53901 107.04101 109.54301 114.547008 119.047008">Freescale Semiconductor, Inc.</tspan></text>
<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 220.32 751.756)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="58.45 65.12 69.01 74.57 77.35 80.13 89.02 91.799999 97.909999 103.46999 107.35999">Preliminary</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 391.68 751.756)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="151.308 156.312 161.316">591</tspan></text>
<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 54 763.756)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="180.87 188.65 194.20999 200.31999 205.87999 209.76999 215.32999 218.10999 220.88999 228.10999 234.21999 239.77999 242.55998 248.66999 254.22998 259.78999 265.34999 268.12998 270.90998 277.01997 280.34996 286.45994 290.34996 299.23997 304.79997 308.12995 310.90995 317.01994">General Business Information</tspan></text>
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