Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint, 3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep. NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference manual. Cortex-M4 96MHz MCU running the G2 firmware. Reyax RYS352A GPS module: datasheet and PAIR command guide. GPS receiver on the G2 board (used for auto-location/satellite lookup). All extracted as markdown + page images + vector SVGs for LLM context. Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.
635 lines
60 KiB (Stored with Git LFS)
XML
635 lines
60 KiB (Stored with Git LFS)
XML
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="11.85" x="13.104 23.996003 28.658003 35.658006 39.158006 43.050008 50.050008 56.266008 59.766008 63.65801 68.32001 74.53601 81.53601 85.42801 89.32001 93.212009 100.212009 107.212009 113.42801 117.32001 120.82001 127.82001 134.03601 137.92801 144.14402 147.64402 158.53601 165.53601 172.53601 178.75202 189.64402 195.86002 202.86002 206.75202 210.25202 216.46802 223.46802 230.46802 234.36002 240.57602 247.57602 251.46802 254.96802 258.46803 265.46803 271.68403 276.346 281.008 288.008 292.66999 303.56199 309.77799 316.77799 322.994 329.21 332.71 336.602 342.048 345.548 352.548 358.764 364.21003 368.10203 371.60203 377.81803 384.81803 391.81803 396.48 402.696 408.14204 413.58805 419.80406 426.80406 430.30406 436.52006 441.96607 445.46607 449.35807 456.35807 462.57408 466.07408 473.07408 479.29008 485.50608">•In the traditional data movement context, performance is best expressed as the peak</tspan><tspan y="27.85" x="23.99601 30.99601 37.21201 41.10401 47.32001 50.82001 54.712015 59.374013 65.59001 72.59001 78.03601 82.69801 88.91402 93.57602 97.07602 101.73802 107.954029 111.84602 118.06203 123.508029 127.008029 133.22403 139.44004 146.44004 150.33203 156.54804 163.54804 169.76404 176.76404 180.26404 187.26404 192.71004 196.60204 203.60204 210.60204 214.10204 217.99404 224.99404 231.21004 234.71004 240.92604 251.03404 263.48005 273.58805 277.08805 280.58805 285.25004 292.25004 295.75004 306.64204 313.64204 319.08805 322.98005 326.48005 330.37205 341.26405 348.26405 352.15605 358.37205 369.26405 375.48005 382.48005 386.37205 392.58805 396.48005 400.37205 407.37205 414.37205 419.81806 423.31806 426.81806 430.71006 437.71006 441.60206 447.04808 450.54808 454.44007 459.10206 465.31806 472.31806 477.76408 482.42607 488.64207">data transfer rates achieved using the eDMA. In most implementations, this transfer</tspan><tspan y="43.85" x="23.99601 28.65801 34.874013 38.766016 44.982015 48.482015 52.374017 57.820016 61.320016 65.21201 69.10401 79.99601 83.88801 87.78001 93.99601 100.99601 104.49601 111.49601 118.49601 121.99601 125.88801 132.888 139.104 142.604 148.05 155.05 161.266 167.48201 174.48201 177.98201 184.98201 189.64402 193.14402 197.03601 204.03601 210.25202 213.75202 219.19802 226.19802 233.19802 237.86002 244.07602 250.29203 253.79203 260.00804 267.00804 274.00804 277.50804 284.50804 290.72404 296.17005 300.06205 303.95405 310.95405 317.17005 321.06205 324.95405 331.95405 338.95405 342.45405 348.67005 355.67005 362.67005 367.33204 373.54804 378.99406 384.44007 387.94007 393.38609 400.38609 406.60209 412.81809 419.0341 424.4801">rate is limited by the speed of the source and destination address spaces.</tspan><tspan y="59.85" x="13.10402 23.996022 28.658022 35.65802 39.15802 45.37402 48.87402 54.32002 60.53602 66.75202 73.75202 80.75202 87.75202 91.25202 97.468029 104.468029 111.468029 115.36002 121.57603 128.57602 132.46802 135.96802 146.07602 153.07602 159.29203 163.95403 170.17003 173.67003 180.67003 186.88603 193.88603 197.77803 203.99404 210.21004 214.87204 221.87204 228.08805 234.30405 240.52005 247.52005 251.02005 261.91206 268.91206 275.91206 282.12806 293.02006 299.23606 306.23606 310.12806 313.62806 320.62806 325.29005 328.79005 334.23606 338.12806 345.12806 352.12806 356.02006 362.23606 365.73606 372.73606 378.95207 382.84407 389.06007 392.56007 399.56007 405.77607 409.66807 416.66807 422.88407 428.33009 431.83009 435.72209 442.72209 446.61408 451.27607 455.93806 462.93806">•In a second context where device-paced movement of single data values to/from</tspan><tspan y="75.85" x="23.99606 30.99606 37.21206 41.874059 45.76606 52.76606 59.76606 65.98206 70.644069 76.86007 80.75207 86.19807 89.69807 93.590068 99.036067 102.536067 109.536067 116.536067 127.42806 131.32007 138.32007 144.53607 151.53607 155.42807 158.92807 162.42807 168.64408 172.14408 183.03607 189.25208 195.46808 200.91408 207.91408 212.57608 218.79209 222.29209 229.29209 233.95409 237.45409 241.34609 248.34609 254.56209 258.06208 262.72407 268.94007 275.94007 282.94007 289.15608 294.60209 298.49409 303.9401 307.4401 311.3321 318.3321 324.5481 328.4401 331.9401 338.1561 344.3721 351.3721 354.8721 361.8721 368.0881 371.5881 377.03413 383.25013 387.9121 394.9121 398.8041 405.0201 411.2361 418.2361 421.7361 425.6281 432.6281 436.1281 442.34413 445.84413 450.5061 454.3981 461.3981 467.6141 474.6141 478.1141 482.0061 485.8981 496.7901">peripherals is dominant, a measure of the requests that can be serviced in a fixed time</tspan><tspan y="91.85" x="23.99606 27.88806 33.33406 36.83406 43.05006 46.55006 57.442064 64.44206 69.104068 75.32007 78.82007 83.48207 89.698078 93.59007 99.806079 106.806079 113.02208 120.02208 123.91408 127.41408 138.30608 144.52208 148.41408 153.07608 156.96808 163.18408 166.68408 170.18408 174.84609 181.84609 185.34609 189.23809 196.23809 200.13008 205.57608 209.07608 215.29209 222.29209 229.29209 233.18408 237.84609 244.84609 251.84609 262.7381 268.9541 275.9541 279.8461 283.3461 286.8461 290.7381 297.7381 303.9541 307.4541 312.90013 319.90013 326.11613 332.33213 339.33213 342.83213 349.83213 354.4941 357.9941 361.8861 368.8861 375.1021 378.6021 384.04814 391.04814 398.04814 402.7101 408.92613 415.14213 418.64213 424.85813 431.85813 438.85813 442.35813 449.35813 455.57414 461.02015 464.91215 468.80415 475.80415 482.02015 485.91215 489.80415 496.80415">is a more relevant metric. In this environment, the speed of the source and destination</tspan><tspan y="107.85" x="23.996109 30.212109 37.21211 44.21211 48.874109 55.090108 60.536108 65.98211 69.48211 74.92811 81.92811 88.14411 94.360118 100.57612 106.02212 109.52212 114.18412 120.40012 131.29213 137.50814 141.40013 148.40013 153.84613 157.34613 161.23813 172.13013 179.13013 186.13013 190.79213 194.68413 200.90013 207.90013 211.79213 215.29213 218.79213 228.90013 235.90013 246.00814 252.22414 259.22413 265.44013 270.1021 273.6021 277.1021 280.9941 287.9941 294.2101 297.7101 308.6021 312.4941 318.7101 323.3721 330.3721 336.5881 341.2501 347.4661 354.4661 358.3581 362.2501 368.4661 374.6821 378.5741 385.5741 390.23609 396.4521 399.9521 406.9521 411.61408 415.11408 419.00608 426.00608 432.22209 435.72209 441.93809 452.04609 464.4921 474.6001 478.1001 484.3161 488.2081 493.6541">address spaces remains important. However, the microarchitecture of the eDMA also</tspan><tspan y="123.85" x="23.996109 28.65811 34.87411 41.09011 44.982114 51.982114 56.64411 62.09011 65.59011 71.03611 74.92811 81.92811 88.92811 92.82011 97.48211 101.37411 107.59011 113.806118 120.806118 124.69811 128.59012 135.59012 139.09012 142.98212 149.98212 153.87412 160.87412 164.37412 168.26612 175.26612 181.48212 184.98212 189.64412 195.86013 201.30612 208.30612 212.19812 216.09012 219.98212 226.98212 233.98212 237.48212 248.37412 254.59012 258.48213 263.1441 267.0361 273.2521">factors significantly into the resulting metric.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 220)" font-size="15" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.89648" x=".00211 8.342111 16.682112 20.852112 29.192112 33.362115 41.702116 45.872117">22.4.4.1</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 122.3833 220)" font-size="15" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.89648" x=".00211 10.007111 18.34711 26.68711 35.02711 39.197114 44.192113 50.02711 58.36711 67.53211 75.872119 80.86712 89.20712 95.04212 99.21212 105.04712 113.38712 118.382129 126.72213">Peak transfer rates</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="202.25" x=".0041 8.5581 15.5581 21.774102 25.274102 32.2741 38.4901 44.7061 51.7061 55.2061 59.098104 63.7601 69.976108 76.976108 82.422107 87.08411 93.30011 97.96211 101.46211 106.124118 112.34012 116.23212 122.44812 127.89412 131.39412 136.05612 143.05612 147.71813 151.21813 156.66413 162.88013 169.88013 176.09613 180.75814 186.97414 190.86614 194.36614 201.36614 205.25814 209.92014 214.58214 220.79814 225.46015 231.67615 238.67615 242.56815 246.06815 251.51415 258.51417 265.51417 270.17616 276.39216 282.60816 286.10816 292.32417 299.32417 306.32417 309.82417 316.82417 323.04017 328.48619 332.37818 336.27018 343.27018 349.48619 353.37818 357.27018 364.27018 371.27018 374.77018 378.66218 383.32417 389.54017 396.54017 401.98619 406.64817 412.86418 417.52616 422.97218 426.47218 432.68818 437.35017 443.56617 447.06617 452.51219 459.51219 466.51219 476.62019 483.62019 487.12019 491.01219">The peak transfer rates for several different source and destination transfers are shown in</tspan><tspan y="218.25" x=".0041 3.8961006 10.896101 17.112103 20.612103 25.274104 32.2741 36.166105 40.058107 47.058107 57.166109 61.05811 68.058109 75.058109 78.558109 82.4501 88.66611 95.66611 99.558109 105.77411 111.22011 114.72011 118.22011 126.77411 133.77411 139.99011 145.43611 151.65212 155.15212 159.04412 165.26012 172.26012 176.15212 182.36812 187.81412 191.31412 197.53012 202.97612 208.42212 215.42212 226.31412 232.53012">the following tables. These tables assume:</tspan><tspan y="242.65" x="13.09411 24.00011 28.662112 35.66211 39.55411 45.77011 50.43211 57.43211 63.64811 67.54011 71.04011 78.82411 88.16211 98.27011 110.71611 114.21611 120.43211 126.64812 133.64812 137.14812 144.14812 150.36412 153.86412 160.08013 166.29613 172.51213 178.72814 184.17414 189.62014 195.83614 202.83614 206.33614 216.44414 220.33614 224.22814 231.22814 234.72814 240.94414 247.16014 251.82215 258.82215 262.32215 272.43016 278.64616 282.53816 286.43016 291.09214 296.53816 300.43016 306.64616 310.53816 316.75416 322.20018 325.70018 335.80818 342.80818 349.02418 356.02418 359.52418 366.52418 370.41618 376.63218 386.74018 392.95619 399.95619 403.45619 408.11817 412.78016 419.78016 430.67216 434.17216 438.06416 445.06416 451.28016 454.78016 460.22618 467.22618 472.67219 476.56419 482.78019">•Internal SRAM can be accessed with zero wait-states when viewed from the system</tspan><tspan y="258.65" x="24.00011 31.00011 38.00011 43.44611 46.94611 53.94611 60.16211 64.05411 70.27011 73.77011 80.77011 87.77011 93.986118 99.43211">bus data phase</tspan><tspan y="283.05" x="13.094121 24.000123 34.108125 38.000127 41.892129 45.392129 49.28413 56.28413 60.176134 66.392139 71.05414 78.05414 84.27014 88.16214 91.66214 98.66214 104.87814 109.540149 113.432147 120.432147 127.432147 133.64815 138.31015 144.52616 148.41815 151.91815 158.91815 165.91815 171.36415 174.86415 179.52616 185.74216 191.95816 198.95816 204.40416 207.90416 212.56616 218.78217 225.78217 232.78217 236.67417 241.33617 247.55217 251.05217 254.94417 265.05216 272.05216 275.55216 285.66017 291.87617 295.76817 299.66017 304.32215 309.76817 313.66017 319.87617 323.76817 329.98417 335.43019 338.93019 342.43019 348.64619 355.64619 362.64619 366.14619 370.03819 377.03819 380.93019 387.14619 391.80818 398.80818 405.02418 408.91618 412.41618 419.41618 425.63218 430.29417 434.18617 441.18617 448.18617 454.40217 459.06416 465.28016 469.17216 472.67216 479.67216 486.67216">•All internal peripheral bus reads require two wait-states, and internal peripheral bus</tspan><tspan y="299.05" x="24.000172 34.108175 38.770174 42.662176 46.554178 52.770177 58.216176 61.716176 65.60818 72.60818 77.27018 83.48618 89.70219 93.20219 103.31019 109.52619 113.41819 117.31019 121.97219 127.41819 131.3102 137.5262 141.4182 147.6342 153.0802 156.5802 160.0802 170.1882 177.1882 183.4042 190.4042 193.9042 200.9042 204.7962 211.0122 221.12021 227.33621 234.33621 237.83621 242.49822 247.16022 254.16022 265.05223 268.55223 272.4442 279.4442 285.66023 289.16023 294.60624 301.60624 307.05226 310.94425 317.16026 328.05226 331.55226 338.55226 345.55226 350.99827 354.49827 361.49827 367.71427 371.60627 377.82228 381.32228 388.32228 395.32228 401.53828 406.98429">writes three wait-states, when viewed from the system bus data phase</tspan><tspan y="323.44999" x="13.094182 24.000184 34.108186 38.000188 41.89219 45.39219 49.28419 56.28419 60.176195 66.3922 71.0542 78.0542 84.2702 88.1622 91.6622 98.6622 104.878208 109.54021 113.432209 120.432209 127.432209 133.64821 138.31021 144.52622 148.41822 151.91822 158.91822 165.91822 171.36421 174.86421 181.08022 187.29622 193.51222 199.72823 205.17423 210.62023 216.83623 222.28223 225.78223 231.99823 236.66024 242.87624 246.37624 253.37624 260.37623 265.0382 272.0382 275.9302 279.8222 285.26823 288.76823 292.66023 299.66023 303.16023 308.60624 312.49824 318.71424">•All internal peripheral bus accesses are 32-bits in size</tspan><tspan y="357.84999" x=".0041923525 8.558192 15.558192 19.450194 24.896195 28.396195 32.288198 38.504198 45.504198 49.3962 55.612199 59.112199 66.1122 70.7742 76.990207 82.4362 88.65221 95.65221 99.544208 104.990207 108.490207 114.70621 118.20621 125.20621 131.42221 137.63822 144.63822 148.13822 152.03022 156.69222 162.90822 169.90822 175.35422 180.01622 186.23223 190.89423 194.39423 199.05623 205.27223 209.16423 215.38024 218.88024 225.09624 232.09624 242.98824 249.98824 256.20423 260.8662 264.7582 270.20423 277.20423 284.20423">This table presents a peak transfer rate comparison.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 136.5 424.39997)" font-size="12" font-family="HelveticaLTStd" font-weight="bold"><tspan y="10.11719" x="16.62423 23.95623 30.628232 37.96023 41.296236 47.968236 51.304239 57.97624 64.64824 68.64424 75.31624 81.988239 88.66023 100.99623 107.66823 116.33223 126.32823 134.99224 138.32823 145.66024 152.33223 159.00423 165.67623 169.01222 173.00823 177.67623 184.34822 191.68022 198.35222 202.34822 209.02022 213.68822 217.02422 221.69222 228.36421 232.36022 239.03221 245.70421 249.0402 253.03621 263.0322 270.3642 277.0362 281.0322 287.7042 294.3762 297.7122 304.3842 311.05619 317.72819">Table 22-292.eDMA peak transfer rates (Mbytes/sec)</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 56.5 446.39997)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="17.33789" x="15.741 21.744 26.748002 31.752003 34.749006 39.753007 47.754007 50.256006 56.259004 61.758005 66.762 71.766 77.265 79.767 82.269 90.765 93.267 98.766 101.763">System Speed, Width</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 182.5 446.39997)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="7.83789" x="23.499 26.001002 31.500002 34.497 39.501005 43.002004 48.501005 53.505006 56.007005 58.509004 64.512 71.01 77.508 85.005008 88.00201 90.99901 96.49801">Internal SRAM-to-</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 182.5 446.39997)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="27.09766" x="27.32501 30.105011 36.21501 39.545015 45.105016 48.995016 55.105016 60.665018 63.445016 66.22501 72.89501 80.11501 87.335018">Internal SRAM</tspan></text>
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<g clip-path="url(#clip_3)">
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</g>
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<text xml:space="preserve" transform="matrix(1 0 0 1 308.5 446.39997)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.83789" x="2.484 7.488001 12.492002 17.991002 20.493002 22.995003 28.494004 31.491003 36.495004 39.996004 45.495004 50.499006 53.001005 55.503004 61.002004 66.006008 69.507 72.009 77.508 83.007 88.011 91.512 96.516 99.018 101.52 107.019 112.518 117.521999">32b internal peripheral bus-</tspan><tspan y="22.83789" x="25.00199 27.99899 33.49799 36.49499 38.99699 44.49599 47.492994 52.496995 55.997995 61.496995 66.50099 69.00299 71.50499 77.50799 84.00599 90.50399">to-Internal SRAM</tspan></text>
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<g clip-path="url(#clip_4)">
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<text xml:space="preserve" transform="matrix(1 0 0 1 434.5 446.39997)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="7.83789" x="15.75 18.252 23.751002 26.748002 31.752003 35.253004 40.752004 45.756006 48.258005 50.760004 56.763 63.261 69.759 77.256008 80.253009 83.25001 88.74901 91.74601 96.75001 101.754009">Internal SRAM-to-32b</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 434.5 446.39997)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="27.09766" x="7.59299 10.37299 16.48299 19.81299 25.37299 29.262989 35.37299 40.93299 43.71299 46.49299 52.60299 58.16299 62.05299 64.83299 70.94299 77.05299 82.61299 86.50299 92.06299 94.84299 97.622989 103.73299 109.84299">internal peripheral bus</tspan></text>
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<g clip-path="url(#clip_5)">
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<text xml:space="preserve" transform="matrix(1 0 0 1 56.25 481.39997)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="31.491 36.495 41.499 44.001 49.005 51.507 59.004 65.502 70.002 72.504 75.006 80.009998 85.01399">66.7 MHz, 32b</tspan></text>
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<g clip-path="url(#clip_6)">
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<path transform="matrix(1,0,0,1,54,478.89997)" d="M126.25 .5H251.75V15.5H126.25Z" fill="#ffffff" fill-rule="evenodd"/>
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<text xml:space="preserve" transform="matrix(1 0 0 1 182.25 481.39997)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="49.491 54.495004 59.499006 64.503009 67.005008">133.3</tspan></text>
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<g clip-path="url(#clip_7)">
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<path transform="matrix(1,0,0,1,54,478.89997)" d="M252.25 .5H377.75V15.5H252.25Z" fill="#ffffff" fill-rule="evenodd"/>
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</g>
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<text xml:space="preserve" transform="matrix(1 0 0 1 308.25 481.39997)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="51.993 56.997 62.001005 64.503009">66.7</tspan></text>
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<g clip-path="url(#clip_8)">
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<path transform="matrix(1,0,0,1,54,478.89997)" d="M378.25 .5H503.75V15.5H378.25Z" fill="#ffffff" fill-rule="evenodd"/>
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</g>
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<text xml:space="preserve" transform="matrix(1 0 0 1 434.25 481.39997)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="51.993 56.997 62.001005 64.503009">53.3</tspan></text>
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<g clip-path="url(#clip_9)">
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<path transform="matrix(1,0,0,1,54,494.64997)" d="M.25 .25H125.75V15.25H.25Z" fill="#ffffff" fill-rule="evenodd"/>
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</g>
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<text xml:space="preserve" transform="matrix(1 0 0 1 56.25 496.89997)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="31.491 36.495 41.499 44.001 49.005 51.507 59.004 65.502 70.002 72.504 75.006 80.009998 85.01399">83.3 MHz, 32b</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="541.74996" x="0 4.662 11.662001 15.554001 21.77 26.432002 33.432 39.648 43.54 48.202 55.986 65.324008 75.43201 87.878009 92.54001 96.43201 103.43201 108.09401 111.98601 118.98601 122.878009 129.09401 133.75601 140.75601 146.97202 150.86402 155.52602 163.31002 172.64801 182.75601 195.20201 198.70201 202.59401 207.25601 213.47202 220.47202 225.91802 230.58002 236.79602 241.45803 246.90402 250.40402 257.40403 263.62004 269.83604 276.83604 281.49803 284.99803 291.21403 295.10603 298.60603 302.49803 309.49803 315.71403 319.21403 325.43003 332.43003 337.092 343.308 345.828 351.27403 354.77403 361.77403 367.99003 371.88203 378.09803 385.09803 391.31404 395.20603 402.20603 405.70603 415.81404 419.70603 426.70603 430.59803 437.59803 441.09803 444.59803 452.38203 459.38203 464.044 467.544 473.76 477.652">Internal-SRAM-to-internal-SRAM transfers occur at the core's datapath width. For all</tspan><tspan y="557.74996" x="0 3.8920005 8.554001 14.770001 21.77 27.216002 31.878003 38.094 42.756 48.202 51.702 55.594 62.594 69.594 76.594 80.486 87.486 91.378 98.378 105.378 108.878 112.77 119.77 125.986 129.486 133.37799 140.37799 144.26999 150.486 155.148 162.148 168.364 172.256 175.756 182.756 188.972 193.634 197.526 204.526 211.526 217.742 222.404 228.62001 232.51201 236.01201 243.01201 250.01201 255.45801 258.958 262.458 269.458 276.458 281.12 288.12 292.012 295.904 299.404 303.296 307.95799 314.17399 321.17399 326.62 331.28199 337.498 342.15998 345.65998 351.106 354.998 361.214 367.43 372.876 376.376 382.592 387.254 393.47 396.97 403.97 409.41603 415.63203 422.63203 426.13203 429.63203 434.294 441.294 444.794 451.01 454.902 458.794 462.294 468.51 474.726 480.17204 486.38804 491.83406">transfers involving the internal peripheral bus, 32-bit transfer sizes are used. In all cases,</tspan><tspan y="573.74996" x=".00005 3.8920506 10.892051 17.108052 20.608052 24.500052 29.162053 35.37805 42.37805 47.82405 52.48605 58.70205 63.364049 66.864048 71.52605 77.74205 81.63405 87.85005 91.35005 95.24205 102.24205 108.45805 112.35005 119.35005 126.35005 132.56606 138.01206 141.51206 145.40406 152.40406 158.62006 162.12006 166.01206 169.90406 180.79605 187.01206 190.51206 194.40406 201.40406 204.90406 209.56606 215.78206 221.99806 228.99806 232.49806 236.39006 243.39006 249.60607 253.10607 258.55207 265.55207 272.55207 277.21406 283.43006 289.64607 293.14607 300.14607 304.03807 311.03807 316.48408 319.98408 323.87608 330.87608 337.09208 340.59208 344.48408 348.37608 359.26808 365.48408 368.98408 372.87608 379.87608 383.37608 393.48408 398.14607 402.03807 405.93006 412.14607 415.64607 419.53807 426.53807 432.75407 436.25407 443.25407 449.47007 454.91609 458.80809 462.70008 469.70008 475.91609 479.80809 483.70008 490.70008 497.70008">the transfer rate includes the time to read the source plus the time to write the destination.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 18)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="25.87323" x="0 5.499 10.998 16.497 21.501 24.498 27 32.499 37.998 43.002004 45.504 48.006 53.505 58.509004 63.513006 68.517009 72.018009 74.520008 80.019008 83.01601 85.518009 91.017009">Functional description</tspan></text>
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