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birdcage/docs/K60-refman-vectors/K60-reference-manual_page_189.svg
Ryan Malloy 5252d1d73c Add hardware reference docs (A3981, K60, RYS352A) 
Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint,
3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep.

NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference
manual. Cortex-M4 96MHz MCU running the G2 firmware.

Reyax RYS352A GPS module: datasheet and PAIR command guide.
GPS receiver on the G2 board (used for auto-location/satellite lookup).

All extracted as markdown + page images + vector SVGs for LLM context.
Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.
2026-02-14 18:36:42 -07:00

986 lines
79 KiB (Stored with Git LFS)
XML
Raw Blame History

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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="11.85" x="13.104 23.996003 27.888003 34.888 41.104 44.604 50.82 57.82 62.482 68.698 72.59 78.035999 85.035999 90.481998 94.37399 100.59 111.481998 114.981998 118.481998 126.266 130.158 136.37401 143.37401 152.712 159.712 165.158 168.658 172.158 178.37401 185.37401 192.37401 195.87401 202.87401 209.87401 215.32 218.82 225.03601 228.92801 235.92801 242.14402 249.14402 254.59001 258.09004 264.30604 268.96803 275.18403 278.68403 282.57603 288.79203 294.23805 299.68406 303.18406 307.07606 314.07606 320.29206 327.29206 330.79206 337.79206 342.45405 345.95405 352.17005 359.17005 366.17005 372.38606 376.27806 379.77806 383.67005 390.67005 394.17005 401.17005 404.67005 417.11607 427.22407 433.44007 436.94007 440.44007 446.65608 453.65608">&#x2022;the core/system, FlexBus, and bus clocks are less than or equal to 4 MHz, and</tspan><tspan y="27.85" x="13.104 23.996003 27.888003 34.888 41.104 44.604 49.266 53.158 59.374 64.82 71.82 75.32 86.212 92.428 103.32 110.32 114.982 121.982 125.482 131.698 135.59 142.59 148.806 155.806 159.306 163.198 168.644 172.144 176.036 182.252 187.698 193.144 196.644 200.536 207.536 213.752 220.752 224.252 231.252 235.914 239.414 245.63 252.63 259.63 265.846 269.738 273.238 277.13 284.13 287.63 294.63 298.13 310.57603 320.68403">&#x2022;the flash memory clock is less than or equal to 1 MHz</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="53.63672" x="232.55402 242.66202 253.55402 262.108">NOTE</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="69.85" x="72.002017 85.21802 92.21802 98.43402 105.43402 108.93402 112.82602 119.82602 126.04202 129.54203 141.98802 151.32602 161.43402 164.93402 168.82602 174.27202 177.77202 181.66402 188.66402 192.16402 201.50202 210.05602 217.84001 222.50202 226.00202 232.21802 239.21802 246.21802 249.71802 255.93402 259.82603 266.82603 273.04203 280.04203 283.93403 290.93403 297.93403 301.43403 305.32603 310.77204 314.27204 321.27204 327.48805 332.15003 336.04203 343.04203 349.25804 356.25804 359.75804 364.42 369.082 376.082 386.974 390.474 394.366 401.366">When the MCG is in BLPI and clocking is derived from the</tspan><tspan y="85.85" x="72.00198 79.78599 86.00199 91.44799 95.33999 98.83999 103.50199 112.84 122.17799 125.67799 129.178 133.06999 140.06999 146.286 149.786 156.002 159.894 166.894 173.11 180.11 183.61 190.61 194.502 201.502 205.394 212.394 218.61 223.272 226.772 232.988 239.988 246.988 250.88 255.542 262.542 266.434 271.88 275.38 278.88 291.32603 300.66404 310.77204 317.77204 325.55604 334.89405 339.55604 347.34004 356.67805 366.01606 376.12406 380.78605 390.89405 395.55604 399.05604 405.27204 412.27204">Fast IRC, the clock divider controls, MCG_SC[FCRDIV] and</tspan><tspan y="101.85" x="72.002017 79.78602 84.44802 96.89402 103.89402 113.232028 121.786029 131.89403 142.00203 146.66403 156.77204 163.77204 168.43404 178.54204 188.65004 197.20404 207.31204 211.97405 222.08205 229.08205 233.74405 237.24405 240.74405 251.63605 258.63606 264.08207 267.97407 271.47407 278.47407 284.69007 288.19007 295.19007 299.85206 306.85206 313.85206 318.51405 324.73005 335.62205 346.51405 352.73005 359.73005 363.23005 368.67607 375.67607 381.89207 388.89207 392.39207 396.28407 403.28407 409.50007">SIM_CLKDIV1[OUTDIV4], must be programmed such that</tspan><tspan y="117.85" x="72.002017 75.89401 82.89401 89.110019 92.610019 97.27202 103.48802 108.93402 115.93402 119.82602 123.71802 127.610019 134.61002 141.61002 145.11002 149.77202 153.66402 159.88002 165.32602 172.32602 175.82602 182.04203 185.93402 192.93402 199.15003 206.15003 209.65003 216.65003 223.65003 234.54203 238.43402 245.43402 251.65003 255.54203 259.04203 263.704 268.366 274.582 281.582 288.582 294.798 301.798 308.014 315.014 318.514 322.406 327.85203 331.35203 338.35203 345.35203 352.35203 355.85203 362.85203 372.96003 379.17604 382.67604 389.67604 394.338 397.838 401.73 407.946 413.39204 418.83805">the resulting flash clock nominal frequency is 800 kHz or less.</tspan><tspan y="133.85" x="72.002017 76.66402 83.66402 87.16402 91.056018 98.056018 101.94801 107.39401 110.89401 117.110019 123.32602 128.77202 134.98802 138.48802 141.98802 148.98802 155.98802 162.20403 165.70403 171.92003 178.92003 185.13603 196.02803 203.02803 206.92003 213.13603 216.63603 223.63603 228.29804 231.79804 238.01404 245.01404 249.67604 254.33805 260.55406 266.77006 270.66206 274.16206 280.37806 287.37806 294.37806 299.04005 302.93205 309.93205 316.93205 321.59403 327.81004 331.70204 335.59403 342.59403 349.59403 353.09403 356.98603">In this case, one example of correct configuration is</tspan><tspan y="149.85" x="72.002017 84.44801 93.78601 103.89401 110.89401 118.67802 128.01602 132.67803 140.46202 149.80002 159.13802 169.24602 173.90802 184.01602 188.67803 196.57402 203.57402 210.57402 217.57402 224.57402 228.07402 234.29003 241.29003">MCG_SC[FCRDIV]=000b and</tspan><tspan y="165.85" x="72.002017 79.78602 84.44802 96.89402 103.89402 113.232028 121.786029 131.89403 142.00203 146.66403 156.77204 163.77204 168.43404 178.54204 188.65004 197.20404 207.31204 211.97405 222.08205 229.08205 233.74405 241.64005 248.64005 255.64005 262.64006 269.64006 276.64006 280.14006 283.64006 288.30204 294.51805 299.96406 306.96406 310.85606 314.74806 318.64006 325.64006 332.64006 336.14006 340.03205 347.03205 350.53205 356.74806 360.24806 367.24806 371.14006 378.14006 382.03205 389.03205 395.24806 398.74806 405.74806 412.74806 416.24806">SIM_CLKDIV1[OUTDIV4]=0100b, resulting in a divide by 5</tspan><tspan y="181.85" x="72.002017 77.44801 83.66402 87.556018 91.44801 95.34001 102.34001 109.34001">setting.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 282.2)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x="-.006 9.446001 14.172001">5.6</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 91.80322 282.2)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x="-.006 12.268002 16.994002 27.381 36.833 46.285 51.011 64.237 73.689 79.350009 84.076007 94.463008">Clock Gating</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 54.000017)" font-size="14" font-family="TimesLTStd"><tspan y="265.44999" x=".00401 8.55801 15.55801 21.77401 25.27401 31.49001 35.38201 42.38201 48.59801 55.59801 59.09801 62.990015 69.99001 73.49001 79.70602 85.92202 92.13802 99.13802 102.63802 113.53002 120.53002 127.53002 134.53003 138.42203 144.63803 148.13803 154.35404 160.57004 167.57004 171.07004 178.07004 184.28604 187.78604 191.67804 198.67804 205.67804 209.57004 216.57004 220.46204 227.46204 234.46204 240.67804 244.57004 248.46204 255.46204 258.96205 265.96205 272.17805 276.07005 282.28605 289.28605 292.78605 299.78605 306.78605 310.28605 316.50205 323.50205 330.50205 334.00205 341.00205 345.66404 350.32603 353.82603 360.82603 366.27204 370.16404 377.16404 384.16404 387.66404 391.55604 398.55604 404.77204 408.27204 416.05604 420.71803 433.16404 436.66404 447.55604 454.55604 461.55604 468.55604 472.44804 478.66404 481.18403">The clock to each module can be individually gated on and off using the SIM module's</tspan><tspan y="281.44999" x=".00404 7.7880408 17.126042 27.234044">SCGC</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 54.000017)" font-size="14" font-family="TimesLTStd" font-style="italic"><tspan y="281.44999" x="36.57204">x</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 54.000017)" font-size="14" font-family="TimesLTStd"><tspan y="281.44999" x="42.78804 46.28804 50.95004 57.16604 64.16604 68.05804 73.504039 77.396038 83.61204 88.27404 93.72004 97.22004 100.72004 109.27404 116.27404 122.49004 127.93604 134.15204 137.65204 144.65204 148.54404 152.43604 157.88204 161.38204 167.59804 172.26004 178.47605 181.97605 188.19205 192.08405 198.30005 204.51605 209.17806 215.39406 222.39406 225.89406 232.11006 236.77207 240.66407 246.88007 251.54207 255.04207 261.25807 268.25807 275.25807 278.75807 283.42005 289.63606 295.08207 301.29808 305.19007 308.69007 312.19007 322.29808 329.29808 333.19007 339.40608 346.40608 349.90608 356.90608 360.79808 366.24409 372.46009 379.46009 383.35209 389.56809 395.0141 398.5141 402.4061 409.4061 415.6221 419.1221 425.3381 429.2301 436.2301 442.4461 449.4461 452.9461 456.8381 463.8381 467.3381 471.2301 478.2301"> registers. These bits are cleared after any reset, which disables the clock to the</tspan><tspan y="297.44999" x=".0040397646 6.2200405 13.22004 17.88204 22.54404 28.76004 34.20604 41.20604 48.20604 55.20604 62.20604 66.09804 73.09804 80.09804 83.59804 94.490039 101.490039 108.490039 115.490039 119.382038 125.59804 129.09804 132.99004 139.99004 143.49004 149.70604 156.70604 163.70604 169.15204 175.36804 180.03005 187.03005 193.24605 196.74605 203.74605 210.74605 220.85405 227.07006 231.73206 235.23206 238.73206 246.51605 251.17806 255.07006 262.07008 266.73207 270.23207 274.12406 281.12406 284.62406 288.51606 295.51606 299.40806 303.30006 307.19206 313.40806 317.30006 321.19206 327.40806 331.30006 338.30006 345.30006 348.80006 355.01606 358.51606 369.40806 376.40806 383.40806 390.40806 394.30006 400.51606 404.01606 407.51606 412.96208 419.17808 423.07008 426.57008 430.46208 437.46208">corresponding module to conserve power. Prior to initializing a module, set the</tspan><tspan y="313.44999" x=".0040697648 6.2200706 13.22007 17.88207 22.544072 28.76007 34.20607 41.20607 48.20607 55.20607 62.20607 66.09807 73.09807 80.09807 83.59807 90.59807 94.49007 98.382068 101.882068 105.77406 112.77406 116.27406 124.05807 133.39608 143.50408">corresponding bit in SCGC</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 54.000017)" font-size="14" font-family="TimesLTStd"><tspan y="313.44999" x="159.05808 162.55808 167.22008 173.43608 180.43608 184.32808 189.77408 193.66608 199.88208 204.54409 208.04409 211.93608 218.93608 222.43608 228.65209 235.65209 241.86809 248.86809 252.76009 258.97608 262.47608 266.36808 273.36808 279.58409 283.08409 289.30009 293.19209 300.19209 306.40809 313.40809 316.90809 320.40809 329.7461 335.9621 340.62409 347.62409 352.28608 358.50209 362.00209 365.89408 372.89408 377.55607 384.55607 388.44807 395.44807 402.44807 405.94807 412.94807 417.61006 422.27204 425.77204 429.66404 436.66404 442.88005 446.38005 452.59605 456.48805 463.48805 469.70405 476.70405"> register to enable the clock. Before turning off the clock,</tspan><tspan y="329.44999" x=".0041046144 10.896106 17.112107 24.112107 30.328106 33.828107 39.274106 46.274106 50.936105 57.152105 60.652105 64.544109 71.544109 75.044109 82.044109 85.936107 91.3821 97.59811 104.59811 108.490108 114.70611 118.20611 122.09811 129.09812 135.31412 138.81412 149.70612 156.70612 163.70612 170.70612 174.59812 180.81412">make sure to disable the module.</tspan><tspan y="353.84999" x=".0041046144 10.112105 17.112107 24.112107 27.612107 34.612108 41.612108 47.058107 50.558107 56.774106 62.990106 69.20611 75.42211 80.86811 86.31411 89.81411 93.70611 100.70611 104.20611 110.42211 113.92211 120.92211 127.138118 131.80011 135.69211 142.69211 149.69211 155.90811 160.57012 166.78612 170.67812 174.17812 178.07012 185.07012 191.28612 195.17812 198.67812 205.67812 211.89412 217.34012 220.84012 224.73212 228.62412 234.07012 237.57012 243.78612 247.67812 254.67812 260.8941 267.8941 271.3941 278.3941 282.2861 287.73213 293.94813 300.94813 304.84013 311.05613 318.05613 321.55613 328.55613 334.77214 341.77214 347.98814 352.65013 358.86613 362.75813 368.97413 374.42015 377.92015 384.13615 391.13615 394.63615 400.85215 405.51414 410.17613 417.17613 421.8381 425.3381 429.2301 435.4461 440.1081 451.0001 454.8921 461.8921 468.1081 472.0001 475.8921 482.8921 489.8921">Any bus access to a peripheral that has its clock disabled generates an error termination.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 54)" font-size="14" font-family="TimesLTStd"><tspan y="437.44996" x="-.00387 8.55013 15.55013 21.76613 25.26613 29.928132 36.92813 40.820135 44.712137 51.712137 61.820138 65.712139 72.712139 79.712139 83.212139 87.10413 93.32014 100.32014 104.212139 110.42814 113.92814 119.37414 126.37414 137.26615 148.15814 154.37415 159.03615 162.92815 169.14415 175.36016 180.80615 184.30615 188.19815 195.19815 201.41416 204.91416 211.13016 215.02216 222.02216 228.23816 235.23816 240.68416 244.18416 250.40016 255.84616 261.29219 268.29219 274.50819 278.40019 284.61619 288.50819 294.72419 301.72419 305.22419 315.33219 319.22419 323.11619 330.11619 333.61619 339.83219 346.0482 352.2642 359.2642 362.7642 373.6562 380.6562 387.6562 394.6562 398.5482 404.7642">The following table summarizes the clocks associated with each module.</tspan></text>
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<g clip-path="url(#clip_30)">
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 18)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="26.01034" x="382.482 388.97999 394.47898 399.48298 404.98197 407.97898 412.98298 416.48399 418.986 423.99 426.492 432.99 435.492 440.991 445.995 450.999 453.501 459.999 462.501 467.505 470.502 474.00303 476.50505 482.00404 487.50303 490.50004 493.00205 498.50105">Chapter 5 Clock Distribution</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 734.93869)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="130.01 137.23 142.79 148.34999 151.12999 157.79999 163.90999 170.01999 173.34999 179.45999 185.01999 193.90999 196.68999 199.46999 205.02999 207.80998 215.02999 220.58998 223.91999 229.47998 233.36998 238.92998 245.03998 250.59998 256.15998 258.93998 267.26997 272.82997 278.93995 285.04994 290.60993 293.38993 296.16993 298.94993 306.16993 311.72993 317.28993 320.06993 322.8499 328.4099 331.1899 336.7499 342.8599 348.96989 351.74989 357.30989 362.86988 368.42988">K60 Sub-Family Reference Manual, Rev. 2 Jun 2012</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 751.756)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x=".00401 5.5030105 8.5000109 13.504011 18.50801 23.00801 27.50801 32.512014 34.510015 39.514017 42.016016 48.019014 53.023015 60.520017 62.518018 67.01802 72.02202 77.02602 82.030017 87.03401 91.53401 94.03601 99.04001 102.03701 104.53901 107.04101 109.54301 114.547008 119.047008">Freescale Semiconductor, Inc.</tspan></text>
<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 220.32 751.756)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="58.45 65.12 69.01 74.57 77.35 80.13 89.02 91.799999 97.909999 103.46999 107.35999">Preliminary</tspan></text>
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