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Ryan Malloy 5252d1d73c Add hardware reference docs (A3981, K60, RYS352A) 
Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint,
3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep.

NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference
manual. Cortex-M4 96MHz MCU running the G2 firmware.

Reyax RYS352A GPS module: datasheet and PAIR command guide.
GPS receiver on the G2 board (used for auto-location/satellite lookup).

All extracted as markdown + page images + vector SVGs for LLM context.
Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.
2026-02-14 18:36:42 -07:00

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<text xml:space="preserve" transform="matrix(1 0 0 1 54 72)" font-size="20" font-family="HelveticaLTStd" font-weight="bold"><tspan y="88.19531" x="0 14.4400019 26.660002 37.780004 50.000005 56.660005 67.78001 75.560009 81.12">Chapter 5</tspan><tspan y="110.19531" x="0 14.4400019 20.000002 32.22 43.340005 54.460008 60.020009 74.46001 80.020008 91.14001 97.8 105.58 111.14 123.36 135.58 142.24 147.8 160.02">Clock Distribution</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 221.8)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x="-.00398 9.448021 14.174021">5.1</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 91.80322 221.8)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x="-.00398 4.72202 15.10902 20.77002 27.38302 37.77002 48.15702 58.54402 67.996028 73.65703 78.383029 88.77003">Introduction</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 72)" font-size="14" font-family="TimesLTStd"><tspan y="187.05" x="-.00498 8.54902 15.54902 21.76502 25.26502 37.71102 47.049024 57.157026 60.657026 71.54903 78.54903 85.54903 92.54903 96.441028 102.65703 106.15703 112.37303 119.37303 126.37303 130.26503 134.92704 141.92704 145.81903 151.26503 154.76503 164.87303 171.87303 175.76503 181.98104 188.98104 192.48104 198.69704 202.58904 209.58904 215.80504 222.80504 226.30504 231.75104 238.75104 245.75104 250.41304 256.62904 262.84504 266.34504 270.23704 275.68305 279.18305 286.18305 291.62907 297.84507 304.84507 308.34507 312.23707 319.23707 322.73707 329.73707 335.95307 340.61506 344.50706 351.50706 357.72306 361.22306 365.11506 372.11506 378.33106 381.83106 387.27708 394.27708 399.72309 403.61509 409.8311 420.72309 424.22309 430.4391 434.3311 441.3311 447.5471 454.5471 459.9931 463.4931 466.9931 475.5471 482.5471">The MCG module controls which clock source is used to derive the system clocks. The</tspan><tspan y="203.05" x="-.00498 6.2110207 10.103021 17.10302 23.31902 30.31902 33.81902 40.81902 47.03502 54.03502 60.25102 64.91302 71.12902 75.02102 78.91302 85.91302 92.91302 96.41302 100.305019 107.305019 114.305019 118.197017 124.41302 127.91302 134.91303 138.80503 145.80503 149.69702 156.69702 162.91303 168.35903 171.85903 175.75102 182.75102 188.96703 192.46703 197.91303 204.12903 208.02103 214.23703 220.45304 224.34503 230.56104 237.56104 241.06104 247.27704 251.16904 258.16905 264.38505 271.38505 274.88505 280.33106 287.33106 294.33106 298.99305 305.20906 311.42506 314.92506 318.81706 325.81706 329.70906 336.70906 340.20906 346.42506 349.92506 356.92506 363.14106 367.80305 371.69505 377.91105 381.80305 388.80305 392.30305 399.30305 403.96504 407.46504 413.68104 417.57304 424.57304 430.78904 437.78904 441.28904 448.28904 455.28904 466.18104 472.39704 476.28904 483.28904 488.73506">clock generation logic divides the selected clock source into a variety of clock domains,</tspan><tspan y="219.05" x="-.00498 3.8870204 10.88702 17.10302 20.99502 27.99502 34.995019 38.88702 45.88702 52.88702 56.38702 60.279024 67.27902 73.495029 76.995029 83.21103 87.10303 94.10303 100.31903 107.31903 112.76503 116.26503 120.92703 127.92703 132.58904 136.08904 139.98104 146.98104 153.19704 156.69704 162.14304 169.14304 174.58904 178.48104 184.69704 195.58904 199.08904 206.08904 213.08904 218.53504 222.03504 232.92704 239.14304 244.58904 248.48104 254.69704 259.35905 264.80506 268.30506 271.80506 277.25108 284.25108 289.69709 293.58909 299.80509 310.69709 314.19709 321.19709 328.19709 333.6431 337.1431 342.5891 346.4811 352.6971 359.6971 365.91313 371.35914 374.85914 378.35914 384.57514 391.57514 398.57514 402.07514 406.73713 410.62913 416.84513 422.29115 429.29115 432.79115 443.68315 449.89915 460.79115 467.79115 472.45314 479.45314">including the clocks for the system bus masters, system bus slaves, and flash memory.</tspan><tspan y="235.05" x="-.00498 8.54902 15.54902 21.76502 25.26502 31.481022 35.373025 42.373025 48.589025 55.589025 59.089025 66.08902 72.30502 79.30502 85.52103 90.18303 96.39903 100.29103 104.18303 111.18303 118.18303 121.68303 125.57503 132.57503 139.57503 143.46703 149.68303 153.18303 159.39904 163.29103 168.73703 175.73703 179.23703 183.12903 194.02103 201.02103 204.91303 211.12903 222.02103 228.23703 235.23703 239.12903 244.57503 248.07503 258.96705 265.96705 272.96705 279.96705 283.85905 290.07505 294.73704 300.18305 307.18305 313.39906 319.61506 323.50706 328.16905 332.06105 338.27705 341.77705 347.99305 351.88505 358.88505 365.10105 372.10105 375.60105 382.60105 388.81706 392.70906 396.60105 403.60105 410.60105 414.10105 417.99305 424.99305 428.49305 434.70906 438.60105 442.49305 449.49305">The clock generation logic also implements module-specific clock gating to allow</tspan><tspan y="251.05" x="-.00498 6.99502 11.657021 17.87302 24.87302 31.87302 35.765024 41.98102 46.64302 50.14302 55.58902 62.58902 69.58902 73.48102 80.48102 85.14302 89.80502 93.30502 100.30502 104.967029 108.467029 119.359027 126.359027 133.35903 140.35903 144.25102 150.46703 155.91303">granular shutoff of modules.</tspan><tspan y="275.45" x="-.00498 8.54902 15.54902 21.76502 25.26502 32.265024 36.92702 40.819025 51.711027 57.927026 62.589025 69.58902 73.08902 79.30502 83.19702 90.19702 96.413028 103.413028 108.859027 112.359027 117.02103 124.02103 128.68303 132.18303 136.07503 143.07503 149.29103 152.79103 158.23703 165.23703 170.68303 174.57503 180.79103 191.68303 195.18303 201.39904 206.06104 212.27704 215.77704 222.77704 228.99304 235.99304 242.20905 246.87105 253.08705 256.97908 263.19508 270.19508 273.69508 278.35707 283.01905 290.01905 300.91105 304.41105 308.30305 315.30305 321.51905 325.01905 337.46507 346.80308 356.91108 367.01908 377.12709 385.68107 395.01908 403.57307 413.68107 417.18107 423.39707 427.28907 434.28907 440.50508 447.50508 451.00508 454.50508 463.05906 470.05906">The primary clocks for the system are generated from the MCGOUTCLK clock. The</tspan><tspan y="291.45" x="-.00498 6.2110207 10.103021 17.10302 23.31902 30.31902 33.81902 40.81902 47.03502 54.03502 60.25102 64.91302 71.12902 75.02102 78.91302 85.91302 92.91302 96.41302 102.62902 106.52102 111.18302 117.399028 124.399028 128.29103 132.18303 136.84503 143.84503 147.34503 154.34503 159.00704 166.00704 173.00704 176.89904 183.89904 190.11504 195.56104 199.06104 204.50704 210.72304 217.72304 223.93904 228.60105 234.81705 238.70905 242.20905 248.42505 252.31705 259.31706 265.53306 272.53306 276.03306 283.03306 286.92506 293.92506 297.81706 304.81706 311.03306 315.69505 321.14106 324.64106 328.53306 335.53306 341.74906 345.64106 349.14106 355.35707 359.24906 363.14106 370.14106 380.24906 383.74906 390.74906 394.64106 399.30305 403.96504 410.18104 414.84303 421.05903 428.05903 431.95103 435.45103 442.45103 449.45103 454.113 458.005 461.897 468.897 475.897 481.34303 484.84303 491.84303">clock generation circuitry provides several clock dividers that allow different portions of</tspan><tspan y="307.45" x="-.00498 3.8870204 10.88702 17.10302 20.60302 27.60302 33.81902 40.81902 44.71102 50.92702 57.14302 60.64302 64.53502 71.53502 75.03502 82.03502 88.25102 91.75102 97.967029 101.859027 108.859027 115.07503 122.07503 128.29103 135.29103 138.79103 145.00704 148.89904 152.39904 159.39904 163.29103 167.95304 172.61504 178.83104 183.49304 189.70905 196.70905 200.60105 204.10105 208.76305 213.42505 219.64105 226.64105 233.64105 239.85706 246.85706 253.07306 256.96507 263.18107 268.62709 272.12709 275.62709 284.18107 291.18107 295.07307 300.51908 304.01908 310.23509 314.12709 318.01908 325.01908 335.12709 340.5731 344.0731 348.73509 355.73509 360.39707 363.89707 367.78907 372.45106 378.66706 385.66706 391.88307 396.54505 403.54505 408.20704 412.86903 418.31504 421.81504 428.81504 435.03105 438.92304 449.03105 455.24705 461.46305">the device to be clocked at different frequencies. This allows for trade-offs between</tspan><tspan y="323.45" x="-.00498 6.99502 13.21102 17.87302 22.53502 29.53502 34.19702 45.089025 51.305025 58.305025 64.52103 70.73703 74.23703 80.45303 87.45303 94.45303 97.95303 104.95303 111.95303 122.061038 128.27704 132.93904 136.43904 143.43904 147.33104 152.77704 158.22304 162.11504 169.11504 175.33104 179.22304 183.11504 190.11504 197.11504">performance and power dissipation.</tspan><tspan y="347.85" x="-.00498 10.103021 16.319022 20.981022 24.873023 31.873023 38.873025 44.319025 47.819025 58.711027 65.71103 72.71103 79.71103 83.60303 89.81903 95.26503 98.76503 102.26503 107.71103 114.71103 120.92703 127.92703 131.42704 137.64304 143.08904 146.58904 150.48104 157.48104 163.69704 167.19704 177.30504 185.08904 194.42704 197.92704 208.03504 216.58904 226.69704 230.19704 239.53504 246.53504 253.53504 257.42704 262.08903 269.08903 272.98103 276.87303 283.08903 287.751 291.251 294.751 301.751 307.967 314.967 321.183 324.683 335.575 342.575 349.575 356.575 360.467 366.683 371.345 376.79103 383.79103 390.00703 396.22303 400.11503 404.777 408.669 414.885 418.385 424.601 428.493 435.493 441.709 448.709 454.15504 457.65504 461.54704 468.54704 474.76304 478.65504 482.15504 488.37104 494.58705">Various modules, such as the USB OTG Controller, have module-specific clocks that can</tspan><tspan y="363.85" x="-.00498 6.99502 13.21102 16.711022 23.711022 29.927021 36.92702 43.14302 47.80502 54.02102 57.91302 64.12902 71.12902 74.62902 79.29102 83.953029 90.953029 101.845027 105.345027 109.23702 116.23702 122.453029 125.953029 138.39904 147.73703 157.84503 165.62903 174.18303 182.73703 192.07503 200.62903 210.73703 214.23703 221.23703 225.89904 229.39904 241.84503 251.18303 261.29103 269.075 277.629 286.18299 295.521 304.07499 314.18299 317.68299 323.899 327.791 334.791 341.007 348.007 351.507 355.007 359.66899 366.66899 370.16899 376.38499 383.38499 390.38499 394.27699 398.16899 402.06098 409.06098 416.06098 419.56098 423.06098 426.95298 433.95298 440.16899 444.83097 451.04698 454.54698 460.76298 465.42497">be generated from the MCGPLLCLK or MCGFLLCLK clock. In addition, there are</tspan><tspan y="379.85" x="-.00498 6.99502 13.21102 17.87302 21.76502 28.76502 35.765024 41.21102 44.71102 51.71102 55.603025 62.603025 68.81902 73.481029 76.981029 87.873027 94.873027 101.873027 108.873027 112.76502 118.981029 123.64303 129.08904 136.08904 142.30504 148.52104 152.41304 157.07505 160.96704 167.18305 170.68305 176.89905 180.79105 187.79105 194.00705 201.00705 206.45305 209.95305 213.84505 220.84505 227.06105 230.95305 234.45305 241.45305 247.66905 254.66905 260.88505 264.38505 271.38505 275.27705 282.27705 288.49305 293.15504 296.65504 302.87104 306.76304 310.65504 316.87104 321.53303 328.53303 334.74903 338.64103 344.85704 348.35704 353.80305 360.80305 367.80305 372.46504 378.68104 384.89704 390.34306 393.84306 397.34306 406.68107 410.57307 417.57307 423.78907 430.78907 434.28907 439.73509 445.95109 449.84309 456.05909 462.2751 466.16709 470.05909 477.05909 484.05909 487.55909 492.22108 499.22108">various other module-specific clocks that have other alternate sources. Clock selection for</tspan><tspan y="395.85" x="-.00498 10.887021 17.88702 23.333022 27.225022 30.725022 41.617025 48.617025 55.617025 62.617025 66.509029 72.72503 78.17103 81.67103 85.56303 91.009029 94.509029 100.72503 107.72503 114.72503 118.61703 123.27903 130.27902 134.17102 138.06302 144.27902 151.27902 154.77902 161.77902 168.77902 172.27902 176.17102 183.17102 189.38703 192.88703 200.67102 210.77902 218.56302 227.11702 230.61702 235.27902 241.49503 248.49503 252.38703 257.83305 261.72505 267.94105 272.60304 278.04905 281.54905 285.44105 292.44105 295.94105 299.83305 306.83305 313.04905 316.54905 324.33305 328.99504 341.44105 344.94105 355.83305 362.83305 369.83305 376.83305 380.72505 386.94105">most modules is controlled by the SOPT registers in the SIM module.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 514.19998)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x=".00206 9.454061 14.180061">5.2</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 91.80322 514.19998)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x=".00206 11.341061 17.954062 28.34106 38.72806 45.34106 54.79306 69.90606 85.01906 89.745059 100.13206 110.51906 115.245059 130.35807 140.74506 151.13205 160.58405">Programming model</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 71.99997)" font-size="14" font-family="TimesLTStd"><tspan y="479.44999" x="-.00194 8.55206 15.55206 21.76806 25.26806 30.714062 36.93006 40.822065 47.038064 53.254064 57.146066 61.038068 68.03807 75.03807 78.53807 84.754077 91.754077 98.754077 102.254077 113.14607 120.14607 124.03807 127.93007 131.82207 138.82207 142.71407 148.93007 155.93007 159.82207 166.82207 173.82207 177.32207 184.32207 188.98407 192.48407 197.93007 204.93007 210.37607 214.26807 220.48407 231.37607 234.87607 241.09207 244.98407 251.98407 258.20008 265.20008 268.70008 274.1461 281.1461 288.1461 292.80809 299.02409 305.24009 310.6861 314.1861 318.0781 323.5241 327.0241 333.2401 340.2401 347.2401 351.1321 355.7941 362.7941 366.6861 370.5781 376.7941 383.7941 387.2941 393.5101 400.5101 407.5101 411.0101 418.0101 422.6721 429.6721 436.6721 441.33409 447.55009 458.44209 469.33409 475.55009 482.55009 486.05009 493.05009 496.94209">The selection and multiplexing of system clock sources is controlled and programmed via</tspan><tspan y="495.44999" x="-.00191 3.8900905 10.890091 17.10609 20.60609 33.052095 42.390096 52.498098 55.998098 66.8901 73.8901 80.8901 87.8901 91.7821 97.9981 101.4981 104.9981 113.5521 120.5521 126.768108 130.2681 135.7141 141.9301 145.8221 149.7141 153.6061 160.6061 167.6061 171.1061 178.1061 182.7681 186.2681 192.4841 196.3761 203.3761 209.5921 216.5921 220.0921 227.0921 230.9841 237.9841 241.8761 248.8761 255.0921 259.7541 265.2001 268.7001 274.9161 281.9161 288.9161 292.4161 303.3081 310.3081 317.3081 324.3081 328.2001 334.4161 337.9161 344.1321 348.0241 355.0241 361.2401 368.2401 371.7401 378.7401 384.95613 388.8481 392.7401 399.7401 406.7401 410.2401 414.9021 421.9021 426.5641 430.0641 433.9561 440.9561 447.1721 450.6721 456.1181 463.1181 468.56413 472.45613 478.67213">the MCG module. The setting of clock dividers and module clock gating for the system</tspan><tspan y="511.44999" x="-.00191 6.2140905 10.876091 17.09209 20.59209 27.59209 32.25409 39.25409 46.25409 50.91609 57.132089 68.024089 78.916088 85.13209 92.13209 95.63209 102.63209 106.524089 112.74009 116.24009 120.13209 127.13209 133.34809 136.84809 144.63208 149.29409 161.74008 165.24008 176.13208 183.13208 190.13208 197.13208 201.02408 207.24008 210.74008 214.24008 223.57808 229.79409 234.45609 240.67209 245.33409 251.5501 258.5501 264.7661 270.98213 274.48213 278.3741 285.3741 292.3741 297.82014 304.03614 307.53614 312.98216 319.19816 325.41416 329.30616 333.19816 340.19816 347.19816 352.64418 356.14418 360.80616 367.80616 372.46815 375.96815 382.96815 389.18415 393.07615 399.29216 403.18415 407.07615 413.29216 420.29216 423.79216 428.45414 434.67015 441.67015 445.56214 451.00816 454.90016 461.11616 465.77815 469.27815 475.49415 482.49415">are programmed via the SIM module. Reference those sections for detailed register and</tspan><tspan y="527.44998" x="-.00191 6.99809 10.89009 14.78209 18.28209 25.28209 31.498089 36.944089 43.160089 47.822088 51.71409 58.71409 62.60609 66.49809 73.49809 80.49809 85.94409">bit descriptions.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 645.7999)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x=".00709 9.45909 14.185091">5.3</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 91.80322 645.7999)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x=".00709 12.281091 17.007092 27.394093 37.781095 43.442094 53.829095 63.281095 72.73309 82.1851 86.911098 91.63709 102.02409 111.4761 120.9281 125.6541 135.1061 144.55809 149.28409 158.73609 163.46208 173.84908 183.30107 192.75307 197.47907 207.86606 218.25305 222.97905 233.36605 238.09204 247.54404 257.93104 264.54405 273.99604">High-Level device clocking diagram</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 71.99994)" font-size="14" font-family="TimesLTStd"><tspan y="611.05" x="-.00492 8.54908 15.54908 21.76508 25.26508 29.92708 36.92708 40.81908 44.711084 51.711084 61.819086 65.71108 72.71108 79.71108">The following </tspan></text>
<text fill="#0000ff" xml:space="preserve" transform="matrix(1 0 0 1 54.000005 71.99994)" font-size="14" font-family="TimesLTStd"><tspan y="611.05" x="83.215999 88.661998 95.661998 101.107997 104.99999 111.215999 122.107997 125.607997 132.608 138.054 144.27 148.162 152.054 155.946 162.162 166.054 173.054">system oscillator</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 71.99994)" font-size="14" font-family="TimesLTStd"><tspan y="611.05" x="177.716 181.216">, </tspan></text>
<text fill="#0000ff" xml:space="preserve" transform="matrix(1 0 0 1 54.000005 71.99994)" font-size="14" font-family="TimesLTStd"><tspan y="611.05" x="184.716 197.162 206.5">MCG</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 71.99994)" font-size="14" font-family="TimesLTStd"><tspan y="611.05" x="216.608 220.108 223.608 229.824 236.824 243.824">, and </tspan></text>
<text fill="#0000ff" xml:space="preserve" transform="matrix(1 0 0 1 54.000005 71.99994)" font-size="14" font-family="TimesLTStd"><tspan y="611.05" x="247.324 255.108 259.77">SIM</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 71.99994)" font-size="14" font-family="TimesLTStd"><tspan y="611.05" x="272.216 275.716 286.608 293.608 300.608 307.608 311.5 317.716 321.216 325.878 332.094 339.094 342.986 348.432 352.324 358.54 363.202 368.648 372.148 378.364 385.364 392.364 396.256 400.918 407.918 411.81 415.31 419.202 426.202"> module registers control the</tspan><tspan y="627.05" x="0 10.892001 17.892003 21.784003 25.676003 29.568003 36.568 40.460004 46.676004 53.676004 59.892004 64.554 70 73.5 77 84 87.892 94.892 98.784 105.784 112 116.662 122.108 125.608 129.108 135.324 142.324 149.324 152.824 159.04001 162.932 169.932 176.14801 183.14801 186.64801 193.64801 199.86402 203.75601 209.97202 215.41802 218.91802 224.36402 231.36402 238.36402 248.47202 255.47202 258.97203 262.864 269.864 273.364 277.256 284.256 290.47203 293.97203 300.97203 307.18803 311.08003 318.08003 328.18803 331.68803 336.35 340.242 347.242 354.242 358.904 365.12">multiplexers, dividers, and clock gates shown in the below figure:</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 729.2693)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="130.01001 137.23001 142.79001 148.35 151.13 157.8 163.91 170.02 173.35 179.46 185.02 193.91 196.69 199.47 205.03 207.81 215.03 220.59 223.92 229.48 233.37 238.93 245.04 250.59999 256.16 258.94 267.27 272.83 278.93998 285.04997 290.60997 293.38996 296.16996 298.94996 306.16996 311.72996 317.28996 320.06996 322.84996 328.40995 331.18995 336.74995 342.85993 348.9699 351.7499 357.3099 362.8699 368.4299">K60 Sub-Family Reference Manual, Rev. 2 Jun 2012</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 746.0866)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x=".00401 5.5030105 8.5000109 13.504011 18.50801 23.00801 27.50801 32.512014 34.510015 39.514017 42.016016 48.019014 53.023015 60.520017 62.518018 67.01802 72.02202 77.02602 82.030017 87.03401 91.53401 94.03601 99.04001 102.03701 104.53901 107.04101 109.54301 114.547008 119.047008">Freescale Semiconductor, Inc.</tspan></text>
<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 220.32 746.0866)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="58.45 65.12 69.01 74.57 77.35 80.13 89.02 91.799999 97.909999 103.46999 107.35999">Preliminary</tspan></text>
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