Ryan Malloy 5252d1d73c Add hardware reference docs (A3981, K60, RYS352A)

Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint,
3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep.

NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference
manual. Cortex-M4 96MHz MCU running the G2 firmware.

Reyax RYS352A GPS module: datasheet and PAIR command guide.
GPS receiver on the G2 board (used for auto-location/satellite lookup).

All extracted as markdown + page images + vector SVGs for LLM context.
Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.

2026-02-14 18:36:42 -07:00

1.4 MiB

Raw Permalink Blame History

Document Metadata

Format: PDF 1.4 Title: Kinetis K60: 100MHz Cortex-M4 256/512KB Flash (144 pin) Author: Freescale Semiconductor Inc. Subject: Kinetis K60 Reference Manual: 100MHz high-performance ARM Cortex-M4 microcontroller(MCU), Ethernet, mixed-signal, up to 512KB Flash/128KB SRAM (144pin) Keywords: K60P144M100SF2V2RM, MK60DN512VMD10,MK60DN256VMD10,MK60DX256VMD10,MK60DN256VLQ10,MK60DX256VLQ10,MK60DN512VLQ10, reference manual, Kinetis, microcontroller, MCU, Cortex-M, ARM, specification, architecture, features, registers, high-performance, Cortex-M4, Kinetis K, K-series, K7x, Ethernet, K60, mixed-signal integration Creator: AH Formatter V5.2 MR1 (5,2,2010,1221) for Linux64 Producer: Antenna House PDF Output Library 2.6.0 (Linux64); modified using iText® 5.5.4 ©2000-2014 iText Group NV (AGPL-version) Creation Date: D:20120602111254-05'00' Mod Date: D:20150220201302-06'00' Trapped: False

Page 1

K60 Sub-Family Reference Manual Supports: MK60DN256VLQ10, MK60DX256VLQ10, MK60DN512VLQ10, MK60DN256VMD10, MK60DX256VMD10, MK60DN512VMD10 Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 Preliminary General Business Information

Page 2

K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 2 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 3

Contents Section number Title Page Chapter 1 About This Document 1.1 Overview.......................................................................................................................................................................59 1.1.1 Purpose.........................................................................................................................................................59 1.1.2 Audience......................................................................................................................................................59 1.2 Conventions..................................................................................................................................................................59 1.2.1 Numbering systems......................................................................................................................................59 1.2.2 Typographic notation...................................................................................................................................60 1.2.3 Special terms................................................................................................................................................60 Chapter 2 Introduction 2.1 Overview.......................................................................................................................................................................61 2.2 Module Functional Categories......................................................................................................................................61 2.2.1 ARM Cortex-M4 Core Modules..................................................................................................................62 2.2.2 System Modules...........................................................................................................................................63 2.2.3 Memories and Memory Interfaces...............................................................................................................64 2.2.4 Clocks...........................................................................................................................................................65 2.2.5 Security and Integrity modules....................................................................................................................65 2.2.6 Analog modules...........................................................................................................................................66 2.2.7 Timer modules.............................................................................................................................................66 2.2.8 Communication interfaces...........................................................................................................................67 2.2.9 Human-machine interfaces..........................................................................................................................68 2.3 Orderable part numbers.................................................................................................................................................68 Chapter 3 Chip Configuration 3.1 Introduction...................................................................................................................................................................71 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 3 General Business Information

Page 4

Section number Title Page 3.2 Core modules................................................................................................................................................................71 3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................71 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................73 3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................79 3.2.4 JTAG Controller Configuration...................................................................................................................81 3.3 System modules............................................................................................................................................................81 3.3.1 SIM Configuration.......................................................................................................................................81 3.3.2 System Mode Controller (SMC) Configuration...........................................................................................82 3.3.3 PMC Configuration......................................................................................................................................83 3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................84 3.3.5 MCM Configuration....................................................................................................................................86 3.3.6 Crossbar Switch Configuration....................................................................................................................87 3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................89 3.3.8 Peripheral Bridge Configuration..................................................................................................................92 3.3.9 DMA request multiplexer configuration......................................................................................................93 3.3.10 DMA Controller Configuration...................................................................................................................96 3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................97 3.3.12 Watchdog Configuration..............................................................................................................................99 3.4 Clock modules..............................................................................................................................................................100 3.4.1 MCG Configuration.....................................................................................................................................100 3.4.2 OSC Configuration......................................................................................................................................101 3.4.3 RTC OSC configuration...............................................................................................................................102 3.5 Memories and memory interfaces.................................................................................................................................102 3.5.1 Flash Memory Configuration.......................................................................................................................102 3.5.2 Flash Memory Controller Configuration.....................................................................................................106 3.5.3 SRAM Configuration...................................................................................................................................107 3.5.4 SRAM Controller Configuration.................................................................................................................111 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 4 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 5

Section number Title Page 3.5.5 System Register File Configuration.............................................................................................................111 3.5.6 VBAT Register File Configuration..............................................................................................................112 3.5.7 EzPort Configuration...................................................................................................................................113 3.5.8 FlexBus Configuration.................................................................................................................................114 3.6 Security.........................................................................................................................................................................117 3.6.1 CRC Configuration......................................................................................................................................117 3.6.2 MMCAU Configuration...............................................................................................................................118 3.6.3 RNG Configuration......................................................................................................................................119 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 5 General Business Information

Page 6

Section number Title Page 3.7 Analog...........................................................................................................................................................................119 3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................119 3.7.2 CMP Configuration......................................................................................................................................127 3.7.3 12-bit DAC Configuration...........................................................................................................................129 3.7.4 VREF Configuration....................................................................................................................................130 3.8 Timers...........................................................................................................................................................................131 3.8.1 PDB Configuration......................................................................................................................................131 3.8.2 FlexTimer Configuration.............................................................................................................................134 3.8.3 PIT Configuration........................................................................................................................................138 3.8.4 Low-power timer configuration...................................................................................................................139 3.8.5 CMT Configuration......................................................................................................................................141 3.8.6 RTC configuration.......................................................................................................................................142 3.9 Communication interfaces............................................................................................................................................143 3.9.1 Ethernet Configuration.................................................................................................................................143 3.9.2 Universal Serial Bus (USB) FS Subsystem.................................................................................................146 3.9.3 CAN Configuration......................................................................................................................................151 3.9.4 SPI configuration.........................................................................................................................................153 3.9.5 I2C Configuration........................................................................................................................................156 3.9.6 UART Configuration...................................................................................................................................157 3.9.7 SDHC Configuration....................................................................................................................................160 3.9.8 I2S configuration..........................................................................................................................................162 3.10 Human-machine interfaces...........................................................................................................................................164 3.10.1 GPIO configuration......................................................................................................................................164 3.10.2 TSI Configuration........................................................................................................................................165 Chapter 4 Memory Map 4.1 Introduction...................................................................................................................................................................169 4.2 System memory map.....................................................................................................................................................169 4.2.1 Aliased bit-band regions..............................................................................................................................170 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 6 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 7

Section number Title Page 4.3 Flash Memory Map.......................................................................................................................................................171 4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................172 4.4 SRAM memory map.....................................................................................................................................................173 4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................173 4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................173 4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................177 4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................181 Chapter 5 Clock Distribution 5.1 Introduction...................................................................................................................................................................183 5.2 Programming model......................................................................................................................................................183 5.3 High-Level device clocking diagram............................................................................................................................183 5.4 Clock definitions...........................................................................................................................................................184 5.4.1 Device clock summary.................................................................................................................................185 5.5 Internal clocking requirements.....................................................................................................................................187 5.5.1 Clock divider values after reset....................................................................................................................188 5.5.2 VLPR mode clocking...................................................................................................................................188 5.6 Clock Gating.................................................................................................................................................................189 5.7 Module clocks...............................................................................................................................................................189 5.7.1 PMC 1-kHz LPO clock................................................................................................................................191 5.7.2 WDOG clocking..........................................................................................................................................191 5.7.3 Debug trace clock.........................................................................................................................................191 5.7.4 PORT digital filter clocking.........................................................................................................................192 5.7.5 LPTMR clocking..........................................................................................................................................192 5.7.6 Ethernet Clocking........................................................................................................................................193 5.7.7 USB FS OTG Controller clocking...............................................................................................................194 5.7.8 FlexCAN clocking.......................................................................................................................................195 5.7.9 UART clocking............................................................................................................................................195 5.7.10 SDHC clocking............................................................................................................................................195 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 7 General Business Information

Page 8

Section number Title Page 5.7.11 I2S/SAI clocking..........................................................................................................................................196 5.7.12 TSI clocking.................................................................................................................................................196 Chapter 6 Reset and Boot 6.1 Introduction...................................................................................................................................................................199 6.2 Reset..............................................................................................................................................................................200 6.2.1 Power-on reset (POR)..................................................................................................................................200 6.2.2 System reset sources....................................................................................................................................200 6.2.3 MCU Resets.................................................................................................................................................204 6.2.4 Reset Pin .....................................................................................................................................................206 6.2.5 Debug resets.................................................................................................................................................206 6.3 Boot...............................................................................................................................................................................207 6.3.1 Boot sources.................................................................................................................................................207 6.3.2 Boot options.................................................................................................................................................208 6.3.3 FOPT boot options.......................................................................................................................................208 6.3.4 Boot sequence..............................................................................................................................................209 Chapter 7 Power Management 7.1 Introduction...................................................................................................................................................................211 7.2 Power modes.................................................................................................................................................................211 7.3 Entering and exiting power modes...............................................................................................................................213 7.4 Power mode transitions.................................................................................................................................................214 7.5 Power modes shutdown sequencing.............................................................................................................................215 7.6 Module Operation in Low Power Modes......................................................................................................................215 7.7 Clock Gating.................................................................................................................................................................218 Chapter 8 Security 8.1 Introduction...................................................................................................................................................................219 8.2 Flash Security...............................................................................................................................................................219 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 8 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 9

Section number Title Page 8.3 Security Interactions with other Modules.....................................................................................................................220 8.3.1 Security interactions with FlexBus..............................................................................................................220 8.3.2 Security Interactions with EzPort................................................................................................................220 8.3.3 Security Interactions with Debug.................................................................................................................220 Chapter 9 Debug 9.1 Introduction...................................................................................................................................................................223 9.1.1 References....................................................................................................................................................225 9.2 The Debug Port.............................................................................................................................................................225 9.2.1 JTAG-to-SWD change sequence.................................................................................................................226 9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................226 9.3 Debug Port Pin Descriptions.........................................................................................................................................227 9.4 System TAP connection................................................................................................................................................227 9.4.1 IR Codes.......................................................................................................................................................227 9.5 JTAG status and control registers.................................................................................................................................228 9.5.1 MDM-AP Control Register..........................................................................................................................229 9.5.2 MDM-AP Status Register............................................................................................................................231 9.6 Debug Resets................................................................................................................................................................232 9.7 AHB-AP........................................................................................................................................................................233 9.8 ITM...............................................................................................................................................................................234 9.9 Core Trace Connectivity...............................................................................................................................................234 9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................235 9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................236 9.11.1 Performance Profiling with the ETB...........................................................................................................236 9.11.2 ETB Counter Control...................................................................................................................................237 9.12 TPIU..............................................................................................................................................................................237 9.13 DWT.............................................................................................................................................................................237 9.14 Debug in Low Power Modes........................................................................................................................................238 9.14.1 Debug Module State in Low Power Modes.................................................................................................239 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 9 General Business Information

Page 10

Section number Title Page 9.15 Debug & Security.........................................................................................................................................................239 Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction...................................................................................................................................................................241 10.2 Signal Multiplexing Integration....................................................................................................................................241 10.2.1 Port control and interrupt module features..................................................................................................242 10.2.2 PCRn reset values for port A.......................................................................................................................242 10.2.3 Clock gating.................................................................................................................................................242 10.2.4 Signal multiplexing constraints....................................................................................................................242 10.3 Pinout............................................................................................................................................................................243 10.3.1 K60 Signal Multiplexing and Pin Assignments...........................................................................................243 10.3.2 K60 Pinouts..................................................................................................................................................249 10.4 Module Signal Description Tables................................................................................................................................251 10.4.1 Core Modules...............................................................................................................................................251 10.4.2 System Modules...........................................................................................................................................252 10.4.3 Clock Modules.............................................................................................................................................253 10.4.4 Memories and Memory Interfaces...............................................................................................................253 10.4.5 Analog..........................................................................................................................................................256 10.4.6 Timer Modules.............................................................................................................................................258 10.4.7 Communication Interfaces...........................................................................................................................261 10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................267 Chapter 11 Port control and interrupts (PORT) 11.1 Introduction...................................................................................................................................................................269 11.2 Overview.......................................................................................................................................................................269 11.2.1 Features........................................................................................................................................................269 11.2.2 Modes of operation......................................................................................................................................270 11.3 External signal description............................................................................................................................................271 11.4 Detailed signal description............................................................................................................................................271 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 10 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 11

Section number Title Page 11.5 Memory map and register definition.............................................................................................................................271 11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................277 11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................280 11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................280 11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................281 11.6 Functional description...................................................................................................................................................281 11.6.1 Pin control....................................................................................................................................................281 11.6.2 Global pin control........................................................................................................................................282 11.6.3 External interrupts........................................................................................................................................282 Chapter 12 System Integration Module (SIM) 12.1 Introduction...................................................................................................................................................................285 12.1.1 Features........................................................................................................................................................285 12.2 Memory map and register definition.............................................................................................................................286 12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................287 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................289 12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................290 12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................293 12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................295 12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................297 12.2.7 System Device Identification Register (SIM_SDID)...................................................................................299 12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................300 12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................301 12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................302 12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................304 12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................306 12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................308 12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................310 12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................311 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 11 General Business Information

Page 12

Section number Title Page 12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................314 12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................314 12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................317 12.2.19 Unique Identification Register High (SIM_UIDH).....................................................................................318 12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................319 12.2.21 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................319 12.2.22 Unique Identification Register Low (SIM_UIDL)......................................................................................320 12.3 Functional description...................................................................................................................................................320 Chapter 13 Reset Control Module (RCM) 13.1 Introduction...................................................................................................................................................................321 13.2 Reset memory map and register descriptions...............................................................................................................321 13.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................321 13.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................323 13.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................324 13.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................325 13.2.5 Mode Register (RCM_MR).........................................................................................................................327 Chapter 14 System Mode Controller 14.1 Introduction...................................................................................................................................................................329 14.2 Modes of operation.......................................................................................................................................................329 14.3 Memory map and register descriptions.........................................................................................................................331 14.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................332 14.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................333 14.3.3 VLLS Control register (SMC_VLLSCTRL)...............................................................................................334 14.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................335 14.4 Functional description...................................................................................................................................................336 14.4.1 Power mode transitions................................................................................................................................336 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 12 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 13

Section number Title Page 14.4.2 Power mode entry/exit sequencing..............................................................................................................339 14.4.3 Run modes....................................................................................................................................................341 14.4.4 Wait modes..................................................................................................................................................343 14.4.5 Stop modes...................................................................................................................................................344 14.4.6 Debug in low power modes.........................................................................................................................347 Chapter 15 Power Management Controller 15.1 Introduction...................................................................................................................................................................349 15.2 Features.........................................................................................................................................................................349 15.3 Low-voltage detect (LVD) system................................................................................................................................349 15.3.1 LVD reset operation.....................................................................................................................................350 15.3.2 LVD interrupt operation...............................................................................................................................350 15.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................350 15.4 I/O retention..................................................................................................................................................................351 15.5 Memory map and register descriptions.........................................................................................................................351 15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................352 15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................353 15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................354 Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.1 Introduction...................................................................................................................................................................357 16.1.1 Features........................................................................................................................................................357 16.1.2 Modes of operation......................................................................................................................................358 16.1.3 Block diagram..............................................................................................................................................359 16.2 LLWU signal descriptions............................................................................................................................................360 16.3 Memory map/register definition...................................................................................................................................361 16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................362 16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................363 16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................364 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 13 General Business Information

Page 14

Section number Title Page 16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................365 16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................366 16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................368 16.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................369 16.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................371 16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................373 16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................374 16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................375 16.4 Functional description...................................................................................................................................................376 16.4.1 LLS mode.....................................................................................................................................................376 16.4.2 VLLS modes................................................................................................................................................376 16.4.3 Initialization.................................................................................................................................................377 Chapter 17 Miscellaneous Control Module (MCM) 17.1 Introduction...................................................................................................................................................................379 17.1.1 Features........................................................................................................................................................379 17.2 Memory map/register descriptions...............................................................................................................................379 17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................380 17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................381 17.2.3 Control Register (MCM_CR)......................................................................................................................381 17.2.4 Interrupt Status Register (MCM_ISR).........................................................................................................383 17.2.5 ETB Counter Control register (MCM_ETBCC)..........................................................................................384 17.2.6 ETB Reload register (MCM_ETBRL).........................................................................................................385 17.2.7 ETB Counter Value register (MCM_ETBCNT)..........................................................................................385 17.2.8 Process ID register (MCM_PID).................................................................................................................386 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 14 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 15

Section number Title Page 17.3 Functional description...................................................................................................................................................386 17.3.1 Interrupts......................................................................................................................................................386 Chapter 18 Crossbar Switch (AXBS) 18.1 Introduction...................................................................................................................................................................389 18.1.1 Features........................................................................................................................................................389 18.2 Memory Map / Register Definition...............................................................................................................................390 18.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................391 18.2.2 Control Register (AXBS_CRSn).................................................................................................................394 18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................396 18.3 Functional Description..................................................................................................................................................396 18.3.1 General operation.........................................................................................................................................396 18.3.2 Register coherency.......................................................................................................................................398 18.3.3 Arbitration....................................................................................................................................................398 18.4 Initialization/application information...........................................................................................................................401 Chapter 19 Memory Protection Unit (MPU) 19.1 Introduction...................................................................................................................................................................403 19.2 Overview.......................................................................................................................................................................403 19.2.1 Block diagram..............................................................................................................................................403 19.2.2 Features........................................................................................................................................................404 19.3 Memory map/register definition...................................................................................................................................405 19.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................409 19.3.2 Error Address Register, slave port n (MPU_EARn)....................................................................................410 19.3.3 Error Detail Register, slave port n (MPU_EDRn).......................................................................................411 19.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................412 19.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................412 19.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................413 19.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................416 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 15 General Business Information

Page 16

Section number Title Page 19.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................417 19.4 Functional description...................................................................................................................................................419 19.4.1 Access evaluation macro..............................................................................................................................419 19.4.2 Putting it all together and error terminations...............................................................................................420 19.4.3 Power management......................................................................................................................................421 19.5 Initialization information..............................................................................................................................................421 19.6 Application information................................................................................................................................................421 Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction...................................................................................................................................................................425 20.1.1 Features........................................................................................................................................................425 20.1.2 General operation.........................................................................................................................................426 20.2 Memory map/register definition...................................................................................................................................426 20.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................428 20.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................431 20.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................436 20.3 Functional description...................................................................................................................................................441 20.3.1 Access support.............................................................................................................................................441 Chapter 21 Direct Memory Access Multiplexer (DMAMUX) 21.1 Introduction...................................................................................................................................................................443 21.1.1 Overview......................................................................................................................................................443 21.1.2 Features........................................................................................................................................................444 21.1.3 Modes of operation......................................................................................................................................444 21.2 External signal description............................................................................................................................................445 21.3 Memory map/register definition...................................................................................................................................445 21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................446 21.4 Functional description...................................................................................................................................................447 21.4.1 DMA channels with periodic triggering capability......................................................................................447 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 16 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 17

Section number Title Page 21.4.2 DMA channels with no triggering capability...............................................................................................449 21.4.3 "Always enabled" DMA sources.................................................................................................................449 21.5 Initialization/application information...........................................................................................................................450 21.5.1 Reset.............................................................................................................................................................451 21.5.2 Enabling and configuring sources................................................................................................................451 Chapter 22 Direct Memory Access Controller (eDMA) 22.1 Introduction...................................................................................................................................................................455 22.1.1 Block diagram..............................................................................................................................................455 22.1.2 Block parts...................................................................................................................................................456 22.1.3 Features........................................................................................................................................................457 22.2 Modes of operation.......................................................................................................................................................459 22.3 Memory map/register definition...................................................................................................................................459 22.3.1 Control Register (DMA_CR).......................................................................................................................470 22.3.2 Error Status Register (DMA_ES)................................................................................................................472 22.3.3 Enable Request Register (DMA_ ERQ ).....................................................................................................474 22.3.4 Enable Error Interrupt Register (DMA_ EEI ).............................................................................................476 22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................479 22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................480 22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................481 22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................482 22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................483 22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................484 22.3.11 Clear Error Register (DMA_CERR)............................................................................................................485 22.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................486 22.3.13 Interrupt Request Register (DMA_ INT )....................................................................................................487 22.3.14 Error Register (DMA_ ERR )......................................................................................................................489 22.3.15 Hardware Request Status Register (DMA_ HRS )......................................................................................492 22.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................494 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 17 General Business Information

Page 18

Section number Title Page 22.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................495 22.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................495 22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................496 22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................497 22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................497 22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................498 22.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................500 22.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................500 22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................501 22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_CITER_ELINKYES)...........................................................................................................501 22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_CITER_ELINKNO)............................................................................................................502 22.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........503 22.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................504 22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_BITER_ELINKYES)...........................................................................................................506 22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO)............................................................................................................507 22.4 Functional description...................................................................................................................................................508 22.4.1 eDMA basic data flow.................................................................................................................................508 22.4.2 Error reporting and handling........................................................................................................................511 22.4.3 Channel preemption.....................................................................................................................................513 22.4.4 Performance.................................................................................................................................................513 22.5 Initialization/application information...........................................................................................................................518 22.5.1 eDMA initialization.....................................................................................................................................518 22.5.2 Programming errors.....................................................................................................................................520 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 18 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 19

Section number Title Page 22.5.3 Arbitration mode considerations..................................................................................................................520 22.5.4 Performing DMA transfers (examples)........................................................................................................521 22.5.5 Monitoring transfer descriptor status...........................................................................................................525 22.5.6 Channel Linking...........................................................................................................................................526 22.5.7 Dynamic programming................................................................................................................................528 Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction...................................................................................................................................................................533 23.1.1 Features........................................................................................................................................................533 23.1.2 Modes of Operation.....................................................................................................................................534 23.1.3 Block Diagram.............................................................................................................................................535 23.2 EWM Signal Descriptions............................................................................................................................................536 23.3 Memory Map/Register Definition.................................................................................................................................536 23.3.1 Control Register (EWM_CTRL).................................................................................................................536 23.3.2 Service Register (EWM_SERV)..................................................................................................................537 23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................537 23.3.4 Compare High Register (EWM_CMPH).....................................................................................................538 23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................539 23.4 Functional Description..................................................................................................................................................539 23.4.1 The EWM_out Signal..................................................................................................................................539 23.4.2 The EWM_in Signal....................................................................................................................................540 23.4.3 EWM Counter..............................................................................................................................................541 23.4.4 EWM Compare Registers............................................................................................................................541 23.4.5 EWM Refresh Mechanism...........................................................................................................................541 23.4.6 EWM Interrupt.............................................................................................................................................542 23.4.7 Counter clock prescaler................................................................................................................................542 Chapter 24 Watchdog Timer (WDOG) 24.1 Introduction...................................................................................................................................................................543 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 19 General Business Information

Page 20

Section number Title Page 24.2 Features.........................................................................................................................................................................543 24.3 Functional overview......................................................................................................................................................545 24.3.1 Unlocking and updating the watchdog.........................................................................................................546 24.3.2 Watchdog configuration time (WCT)..........................................................................................................547 24.3.3 Refreshing the watchdog..............................................................................................................................548 24.3.4 Windowed mode of operation......................................................................................................................548 24.3.5 Watchdog disabled mode of operation.........................................................................................................548 24.3.6 Low-power modes of operation...................................................................................................................549 24.3.7 Debug modes of operation...........................................................................................................................549 24.4 Testing the watchdog....................................................................................................................................................550 24.4.1 Quick test.....................................................................................................................................................550 24.4.2 Byte test........................................................................................................................................................551 24.5 Backup reset generator..................................................................................................................................................552 24.6 Generated resets and interrupts.....................................................................................................................................552 24.7 Memory map and register definition.............................................................................................................................553 24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................554 24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................555 24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................556 24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................556 24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................557 24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................557 24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................558 24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................558 24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................558 24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................559 24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................559 24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................560 24.8 Watchdog operation with 8-bit access..........................................................................................................................560 24.8.1 General guideline.........................................................................................................................................560 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 20 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 21

Section number Title Page 24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................560 24.9 Restrictions on watchdog operation..............................................................................................................................561 Chapter 25 Multipurpose Clock Generator (MCG) 25.1 Introduction...................................................................................................................................................................565 25.1.1 Features........................................................................................................................................................565 25.1.2 Modes of Operation.....................................................................................................................................568 25.2 External Signal Description..........................................................................................................................................569 25.3 Memory Map/Register Definition.................................................................................................................................569 25.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................570 25.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................571 25.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................572 25.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................573 25.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................574 25.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................575 25.3.7 MCG Status Register (MCG_S)..................................................................................................................577 25.3.8 MCG Status and Control Register (MCG_SC)............................................................................................578 25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................580 25.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................580 25.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................580 25.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................581 25.3.13 MCG Control 9 Register (MCG_C9)...........................................................................................................582 25.3.14 MCG Control 10 Register (MCG_C10).......................................................................................................582 25.4 Functional Description..................................................................................................................................................583 25.4.1 MCG mode state diagram............................................................................................................................583 25.4.2 Low Power Bit Usage..................................................................................................................................587 25.4.3 MCG Internal Reference Clocks..................................................................................................................587 25.4.4 External Reference Clock............................................................................................................................588 25.4.5 MCG Fixed frequency clock .......................................................................................................................588 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 21 General Business Information

Page 22

Section number Title Page 25.4.6 MCG PLL clock ..........................................................................................................................................589 25.4.7 MCG Auto TRIM (ATM)............................................................................................................................589 25.5 Initialization / Application information........................................................................................................................590 25.5.1 MCG module initialization sequence...........................................................................................................590 25.5.2 Using a 32.768 kHz reference......................................................................................................................593 25.5.3 MCG mode switching..................................................................................................................................593 Chapter 26 Oscillator (OSC) 26.1 Introduction...................................................................................................................................................................603 26.2 Features and Modes......................................................................................................................................................603 26.3 Block Diagram..............................................................................................................................................................604 26.4 OSC Signal Descriptions..............................................................................................................................................604 26.5 External Crystal / Resonator Connections....................................................................................................................605 26.6 External Clock Connections.........................................................................................................................................606 26.7 Memory Map/Register Definitions...............................................................................................................................607 26.7.1 OSC Memory Map/Register Definition.......................................................................................................607 26.8 Functional Description..................................................................................................................................................608 26.8.1 OSC Module States......................................................................................................................................608 26.8.2 OSC Module Modes.....................................................................................................................................610 26.8.3 Counter.........................................................................................................................................................612 26.8.4 Reference Clock Pin Requirements.............................................................................................................612 26.9 Reset..............................................................................................................................................................................612 26.10 Low Power Modes Operation.......................................................................................................................................613 26.11 Interrupts.......................................................................................................................................................................613 Chapter 27 RTC Oscillator 27.1 Introduction...................................................................................................................................................................615 27.1.1 Features and Modes.....................................................................................................................................615 27.1.2 Block Diagram.............................................................................................................................................615 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 22 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 23

Section number Title Page 27.2 RTC Signal Descriptions..............................................................................................................................................616 27.2.1 EXTAL32 — Oscillator Input.....................................................................................................................616 27.2.2 XTAL32 — Oscillator Output.....................................................................................................................616 27.3 External Crystal Connections.......................................................................................................................................617 27.4 Memory Map/Register Descriptions.............................................................................................................................617 27.5 Functional Description..................................................................................................................................................617 27.6 Reset Overview.............................................................................................................................................................618 27.7 Interrupts.......................................................................................................................................................................618 Chapter 28 Flash Memory Controller (FMC) 28.1 Introduction...................................................................................................................................................................619 28.1.1 Overview......................................................................................................................................................619 28.1.2 Features........................................................................................................................................................620 28.2 Modes of operation.......................................................................................................................................................620 28.3 External signal description............................................................................................................................................621 28.4 Memory map and register descriptions.........................................................................................................................621 28.4.1 Flash Access Protection Register (FMC_PFAPR).......................................................................................627 28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)........................................................................................630 28.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)........................................................................................633 28.4.4 Cache Tag Storage (FMC_TAGVDW0Sn).................................................................................................635 28.4.5 Cache Tag Storage (FMC_TAGVDW1Sn).................................................................................................636 28.4.6 Cache Tag Storage (FMC_TAGVDW2Sn).................................................................................................637 28.4.7 Cache Tag Storage (FMC_TAGVDW3Sn).................................................................................................638 28.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)..........................................................................638 28.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)..........................................................................639 28.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)..........................................................................639 28.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)..........................................................................640 28.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)..........................................................................640 28.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL)..........................................................................641 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 23 General Business Information

Page 24

Section number Title Page 28.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)..........................................................................641 28.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL)..........................................................................642 28.5 Functional description...................................................................................................................................................642 28.5.1 Default configuration...................................................................................................................................642 28.5.2 Configuration options..................................................................................................................................643 28.5.3 Wait states....................................................................................................................................................643 28.5.4 Speculative reads..........................................................................................................................................644 28.6 Initialization and application information.....................................................................................................................645 Chapter 29 Flash Memory Module (FTFL) 29.1 Introduction...................................................................................................................................................................647 29.1.1 Features........................................................................................................................................................648 29.1.2 Block Diagram.............................................................................................................................................650 29.1.3 Glossary.......................................................................................................................................................651 29.2 External Signal Description..........................................................................................................................................653 29.3 Memory Map and Registers..........................................................................................................................................653 29.3.1 Flash Configuration Field Description.........................................................................................................654 29.3.2 Program Flash IFR Map...............................................................................................................................654 29.3.3 Data Flash IFR Map.....................................................................................................................................655 29.3.4 Register Descriptions...................................................................................................................................657 29.4 Functional Description..................................................................................................................................................670 29.4.1 Program Flash Memory Swap......................................................................................................................670 29.4.2 Flash Protection............................................................................................................................................670 29.4.3 FlexNVM Description..................................................................................................................................672 29.4.4 Interrupts......................................................................................................................................................677 29.4.5 Flash Operation in Low-Power Modes........................................................................................................678 29.4.6 Functional Modes of Operation...................................................................................................................678 29.4.7 Flash Reads and Ignored Writes..................................................................................................................678 29.4.8 Read While Write (RWW)...........................................................................................................................679 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 24 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 25

Section number Title Page 29.4.9 Flash Program and Erase..............................................................................................................................679 29.4.10 Flash Command Operations.........................................................................................................................679 29.4.11 Margin Read Commands.............................................................................................................................688 29.4.12 Flash Command Description........................................................................................................................689 29.4.13 Security........................................................................................................................................................717 29.4.14 Reset Sequence............................................................................................................................................719 Chapter 30 External Bus Interface (FlexBus) 30.1 Introduction...................................................................................................................................................................721 30.1.1 Definition.....................................................................................................................................................721 30.1.2 Features........................................................................................................................................................722 30.2 Signal descriptions........................................................................................................................................................722 30.3 Memory Map/Register Definition.................................................................................................................................725 30.3.1 Chip Select Address Register (FB_CSARn)................................................................................................727 30.3.2 Chip Select Mask Register (FB_CSMRn)...................................................................................................727 30.3.3 Chip Select Control Register (FB_CSCRn).................................................................................................728 30.3.4 Chip Select port Multiplexing Control Register (FB_CSPMCR)................................................................731 30.4 Functional description...................................................................................................................................................732 30.4.1 Modes of operation......................................................................................................................................733 30.4.2 Address comparison.....................................................................................................................................733 30.4.3 Address driven on address bus.....................................................................................................................733 30.4.4 Connecting address/data lines......................................................................................................................733 30.4.5 Bit ordering..................................................................................................................................................734 30.4.6 Data transfer signals.....................................................................................................................................734 30.4.7 Signal transitions..........................................................................................................................................734 30.4.8 Data-byte alignment and physical connections............................................................................................734 30.4.9 Address/data bus multiplexing.....................................................................................................................735 30.4.10 Data transfer states.......................................................................................................................................736 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 25 General Business Information

Page 26

Section number Title Page 30.4.11 FlexBus Timing Examples...........................................................................................................................737 30.4.12 Burst cycles..................................................................................................................................................756 30.4.13 Extended Transfer Start/Address Latch Enable...........................................................................................764 30.4.14 Bus errors.....................................................................................................................................................765 30.5 Initialization/Application Information..........................................................................................................................766 30.5.1 Initializing a chip-select...............................................................................................................................766 30.5.2 Reconfiguring a chip-select.........................................................................................................................766 Chapter 31 EzPort 31.1 Overview.......................................................................................................................................................................767 31.1.1 Introduction..................................................................................................................................................767 31.1.2 Features........................................................................................................................................................768 31.1.3 Modes of operation......................................................................................................................................768 31.2 External signal description............................................................................................................................................769 31.2.1 EzPort Clock (EZP_CK)..............................................................................................................................769 31.2.2 EzPort Chip Select (EZP_CS)......................................................................................................................769 31.2.3 EzPort Serial Data In (EZP_D)....................................................................................................................770 31.2.4 EzPort Serial Data Out (EZP_Q).................................................................................................................770 31.3 Command definition.....................................................................................................................................................770 31.3.1 Command descriptions.................................................................................................................................771 31.4 Flash memory map for EzPort access...........................................................................................................................777 Chapter 32 Cyclic Redundancy Check (CRC) 32.1 Introduction...................................................................................................................................................................779 32.1.1 Features........................................................................................................................................................779 32.1.2 Block diagram..............................................................................................................................................780 32.1.3 Modes of operation......................................................................................................................................780 32.2 Memory map and register descriptions.........................................................................................................................780 32.2.1 CRC Data register (CRC_CRC)..................................................................................................................781 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 26 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 27

Section number Title Page 32.2.2 CRC Polynomial register (CRC_GPOLY)..................................................................................................782 32.2.3 CRC Control register (CRC_CTRL)............................................................................................................783 32.3 Functional description...................................................................................................................................................784 32.3.1 CRC initialization/reinitialization................................................................................................................784 32.3.2 CRC calculations..........................................................................................................................................784 32.3.3 Transpose feature.........................................................................................................................................785 32.3.4 CRC result complement...............................................................................................................................787 Chapter 33 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) 33.1 Introduction...................................................................................................................................................................789 33.2 MMCAU Block Diagram.............................................................................................................................................789 33.3 Overview.......................................................................................................................................................................791 33.4 Features.........................................................................................................................................................................792 33.5 Memory map/register definition...................................................................................................................................792 33.5.1 Status Register (CAU_CASR).....................................................................................................................794 33.5.2 Accumulator (CAU_CAA)..........................................................................................................................795 33.5.3 General Purpose Register (CAU_CAn).......................................................................................................795 33.6 Functional description...................................................................................................................................................796 33.6.1 MMCAU programming model....................................................................................................................796 33.6.2 MMCAU integrity checks............................................................................................................................798 33.6.3 CAU commands...........................................................................................................................................800 33.7 Application/initialization information..........................................................................................................................807 33.7.1 Code example...............................................................................................................................................807 33.7.2 Assembler equate values..............................................................................................................................807 Chapter 34 Random Number Generator Accelerator (RNGA) 34.1 Introduction...................................................................................................................................................................809 34.1.1 Overview......................................................................................................................................................809 34.2 Modes of operation.......................................................................................................................................................810 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 27 General Business Information

Page 28

Section number Title Page 34.3 Memory map and register definition.............................................................................................................................810 34.3.1 RNGA Control Register (RNG_CR)...........................................................................................................811 34.3.2 RNGA Status Register (RNG_SR)..............................................................................................................813 34.3.3 RNGA Entropy Register (RNG_ER)...........................................................................................................815 34.3.4 RNGA Output Register (RNG_OR)............................................................................................................816 34.4 Functional description...................................................................................................................................................816 34.4.1 RNGA Output Register................................................................................................................................817 34.4.2 RNGA Core/Control Logic Block...............................................................................................................817 34.5 Initialization/application information...........................................................................................................................818 Chapter 35 Analog-to-Digital Converter (ADC) 35.1 Introduction...................................................................................................................................................................819 35.1.1 Features........................................................................................................................................................819 35.1.2 Block diagram..............................................................................................................................................820 35.2 ADC Signal Descriptions..............................................................................................................................................821 35.2.1 Analog Power (VDDA)...............................................................................................................................822 35.2.2 Analog Ground (VSSA)...............................................................................................................................822 35.2.3 Voltage Reference Select.............................................................................................................................822 35.2.4 Analog Channel Inputs (ADx).....................................................................................................................823 35.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................823 35.3 Register definition.........................................................................................................................................................823 35.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................826 35.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................829 35.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................831 35.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................832 35.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................833 35.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................834 35.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................836 35.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................838 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 28 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 29

Section number Title Page 35.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................838 35.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................839 35.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................839 35.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................840 35.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................840 35.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................841 35.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................841 35.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................842 35.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................842 35.3.18 ADC PGA Register (ADCx_PGA)..............................................................................................................843 35.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................844 35.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLMS).....................................................845 35.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM4).....................................................845 35.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM3).....................................................846 35.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM2).....................................................846 35.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM1).....................................................847 35.3.25 ADC Minus-Side General Calibration Value Register (ADCx_CLM0).....................................................847 35.4 Functional description...................................................................................................................................................847 35.4.1 PGA functional description..........................................................................................................................848 35.4.2 Clock select and divide control....................................................................................................................849 35.4.3 Voltage reference selection..........................................................................................................................849 35.4.4 Hardware trigger and channel selects..........................................................................................................850 35.4.5 Conversion control.......................................................................................................................................851 35.4.6 Automatic compare function........................................................................................................................858 35.4.7 Calibration function.....................................................................................................................................859 35.4.8 User-defined offset function........................................................................................................................861 35.4.9 Temperature sensor......................................................................................................................................862 35.4.10 MCU wait mode operation...........................................................................................................................863 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 29 General Business Information

Page 30

Section number Title Page 35.4.11 MCU Normal Stop mode operation.............................................................................................................863 35.4.12 MCU Low-Power Stop mode operation......................................................................................................864 35.5 Initialization information..............................................................................................................................................865 35.5.1 ADC module initialization example............................................................................................................865 35.6 Application information................................................................................................................................................867 35.6.1 External pins and routing.............................................................................................................................867 35.6.2 Sources of error............................................................................................................................................869 Chapter 36 Comparator (CMP) 36.1 Introduction...................................................................................................................................................................875 36.2 CMP features................................................................................................................................................................875 36.3 6-bit DAC key features.................................................................................................................................................876 36.4 ANMUX key features...................................................................................................................................................877 36.5 CMP, DAC and ANMUX diagram...............................................................................................................................877 36.6 CMP block diagram......................................................................................................................................................878 36.7 Memory map/register definitions..................................................................................................................................880 36.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................880 36.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................881 36.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................883 36.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................883 36.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................884 36.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................885 36.8 CMP functional description..........................................................................................................................................886 36.8.1 CMP functional modes.................................................................................................................................886 36.8.2 Power modes................................................................................................................................................895 36.8.3 Startup and operation...................................................................................................................................896 36.8.4 Low-pass filter.............................................................................................................................................897 36.9 CMP interrupts..............................................................................................................................................................899 36.10 CMP DMA support.......................................................................................................................................................899 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 30 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 31

Section number Title Page 36.11 Digital-to-analog converter block diagram...................................................................................................................900 36.12 DAC functional description..........................................................................................................................................900 36.12.1 Voltage reference source select....................................................................................................................900 36.13 DAC resets....................................................................................................................................................................901 36.14 DAC clocks...................................................................................................................................................................901 36.15 DAC interrupts..............................................................................................................................................................901 Chapter 37 12-bit Digital-to-Analog Converter (DAC) 37.1 Introduction...................................................................................................................................................................903 37.2 Features.........................................................................................................................................................................903 37.3 Block diagram...............................................................................................................................................................904 37.4 Memory map/register definition...................................................................................................................................905 37.4.1 DAC Data Low Register (DACx_DATnL).................................................................................................906 37.4.2 DAC Data High Register (DACx_DATnH)................................................................................................906 37.4.3 DAC Status Register (DACx_SR)...............................................................................................................907 37.4.4 DAC Control Register (DACx_C0).............................................................................................................908 37.4.5 DAC Control Register 1 (DACx_C1)..........................................................................................................909 37.4.6 DAC Control Register 2 (DACx_C2)..........................................................................................................910 37.5 Functional description...................................................................................................................................................910 37.5.1 DAC data buffer operation...........................................................................................................................910 37.5.2 DMA operation............................................................................................................................................911 37.5.3 Resets...........................................................................................................................................................911 37.5.4 Low-Power mode operation.........................................................................................................................912 Chapter 38 Voltage Reference (VREFV1) 38.1 Introduction...................................................................................................................................................................913 38.1.1 Overview......................................................................................................................................................914 38.1.2 Features........................................................................................................................................................914 38.1.3 Modes of Operation.....................................................................................................................................915 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 31 General Business Information

Page 32

Section number Title Page 38.1.4 VREF Signal Descriptions...........................................................................................................................915 38.2 Memory Map and Register Definition..........................................................................................................................916 38.2.1 VREF Trim Register (VREF_TRM)............................................................................................................916 38.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................917 38.3 Functional Description..................................................................................................................................................918 38.3.1 Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................918 38.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................919 38.4 Initialization/Application Information..........................................................................................................................920 Chapter 39 Programmable Delay Block (PDB) 39.1 Introduction...................................................................................................................................................................921 39.1.1 Features........................................................................................................................................................921 39.1.2 Implementation............................................................................................................................................922 39.1.3 Back-to-back acknowledgment connections................................................................................................923 39.1.4 DAC External Trigger Input Connections...................................................................................................923 39.1.5 Block diagram..............................................................................................................................................923 39.1.6 Modes of operation......................................................................................................................................925 39.2 PDB signal descriptions................................................................................................................................................925 39.3 Memory map and register definition.............................................................................................................................925 39.3.1 Status and Control Register (PDBx_SC).....................................................................................................927 39.3.2 Modulus Register (PDBx_MOD).................................................................................................................929 39.3.3 Counter Register (PDBx_CNT)...................................................................................................................930 39.3.4 Interrupt Delay Register (PDBx_IDLY)......................................................................................................930 39.3.5 Channel n Control Register 1 (PDBx_CHnC1)...........................................................................................931 39.3.6 Channel n Status Register (PDBx_CHnS)...................................................................................................932 39.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)........................................................................................932 39.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)........................................................................................933 39.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn).................................................................933 39.3.10 DAC Interval n Register (PDBx_DACINTn)..............................................................................................934 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 32 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 33

Section number Title Page 39.3.11 Pulse-Out n Enable Register (PDBx_POEN)...............................................................................................934 39.3.12 Pulse-Out n Delay Register (PDBx_POnDLY)...........................................................................................935 39.4 Functional description...................................................................................................................................................935 39.4.1 PDB pre-trigger and trigger outputs.............................................................................................................935 39.4.2 PDB trigger input source selection..............................................................................................................937 39.4.3 DAC interval trigger outputs........................................................................................................................937 39.4.4 Pulse-Out's...................................................................................................................................................938 39.4.5 Updating the delay registers.........................................................................................................................938 39.4.6 Interrupts......................................................................................................................................................940 39.4.7 DMA............................................................................................................................................................940 39.5 Application information................................................................................................................................................940 39.5.1 Impact of using the prescaler and multiplication factor on timing resolution.............................................940 Chapter 40 FlexTimer Module (FTM) 40.1 Introduction...................................................................................................................................................................943 40.1.1 FlexTimer philosophy..................................................................................................................................943 40.1.2 Features........................................................................................................................................................944 40.1.3 Modes of operation......................................................................................................................................945 40.1.4 Block diagram..............................................................................................................................................946 40.2 FTM signal descriptions...............................................................................................................................................948 40.3 Memory map and register definition.............................................................................................................................948 40.3.1 Memory map................................................................................................................................................948 40.3.2 Register descriptions....................................................................................................................................949 40.3.3 Status And Control (FTMx_SC)..................................................................................................................955 40.3.4 Counter (FTMx_CNT).................................................................................................................................956 40.3.5 Modulo (FTMx_MOD)................................................................................................................................957 40.3.6 Channel (n) Status And Control (FTMx_CnSC)..........................................................................................958 40.3.7 Channel (n) Value (FTMx_CnV).................................................................................................................960 40.3.8 Counter Initial Value (FTMx_CNTIN)........................................................................................................961 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 33 General Business Information

Page 34

Section number Title Page 40.3.9 Capture And Compare Status (FTMx_STATUS)........................................................................................961 40.3.10 Features Mode Selection (FTMx_MODE)..................................................................................................963 40.3.11 Synchronization (FTMx_SYNC).................................................................................................................965 40.3.12 Initial State For Channels Output (FTMx_OUTINIT).................................................................................968 40.3.13 Output Mask (FTMx_OUTMASK).............................................................................................................969 40.3.14 Function For Linked Channels (FTMx_COMBINE)...................................................................................971 40.3.15 Deadtime Insertion Control (FTMx_DEADTIME).....................................................................................976 40.3.16 FTM External Trigger (FTMx_EXTTRIG).................................................................................................977 40.3.17 Channels Polarity (FTMx_POL)..................................................................................................................978 40.3.18 Fault Mode Status (FTMx_FMS).................................................................................................................981 40.3.19 Input Capture Filter Control (FTMx_FILTER)...........................................................................................983 40.3.20 Fault Control (FTMx_FLTCTRL)...............................................................................................................984 40.3.21 Quadrature Decoder Control And Status (FTMx_QDCTRL)......................................................................986 40.3.22 Configuration (FTMx_CONF).....................................................................................................................988 40.3.23 FTM Fault Input Polarity (FTMx_FLTPOL)...............................................................................................989 40.3.24 Synchronization Configuration (FTMx_SYNCONF)..................................................................................991 40.3.25 FTM Inverting Control (FTMx_INVCTRL)................................................................................................993 40.3.26 FTM Software Output Control (FTMx_SWOCTRL)..................................................................................994 40.3.27 FTM PWM Load (FTMx_PWMLOAD).....................................................................................................996 40.4 Functional description...................................................................................................................................................997 40.4.1 Clock source.................................................................................................................................................998 40.4.2 Prescaler.......................................................................................................................................................999 40.4.3 Counter.........................................................................................................................................................999 40.4.4 Input Capture mode......................................................................................................................................1004 40.4.5 Output Compare mode.................................................................................................................................1007 40.4.6 Edge-Aligned PWM (EPWM) mode...........................................................................................................1008 40.4.7 Center-Aligned PWM (CPWM) mode........................................................................................................1010 40.4.8 Combine mode.............................................................................................................................................1012 40.4.9 Complementary mode..................................................................................................................................1020 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 34 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 35

Section number Title Page 40.4.10 Registers updated from write buffers...........................................................................................................1021 40.4.11 PWM synchronization..................................................................................................................................1023 40.4.12 Inverting.......................................................................................................................................................1039 40.4.13 Software output control................................................................................................................................1040 40.4.14 Deadtime insertion.......................................................................................................................................1042 40.4.15 Output mask.................................................................................................................................................1045 40.4.16 Fault control.................................................................................................................................................1046 40.4.17 Polarity control.............................................................................................................................................1049 40.4.18 Initialization.................................................................................................................................................1050 40.4.19 Features priority...........................................................................................................................................1050 40.4.20 Channel trigger output.................................................................................................................................1051 40.4.21 Initialization trigger......................................................................................................................................1052 40.4.22 Capture Test mode.......................................................................................................................................1054 40.4.23 DMA............................................................................................................................................................1055 40.4.24 Dual Edge Capture mode.............................................................................................................................1056 40.4.25 Quadrature Decoder mode...........................................................................................................................1063 40.4.26 BDM mode...................................................................................................................................................1068 40.4.27 Intermediate load..........................................................................................................................................1069 40.4.28 Global time base (GTB)...............................................................................................................................1071 40.5 Reset overview..............................................................................................................................................................1072 40.6 FTM Interrupts..............................................................................................................................................................1074 40.6.1 Timer Overflow Interrupt.............................................................................................................................1074 40.6.2 Channel (n) Interrupt....................................................................................................................................1074 40.6.3 Fault Interrupt..............................................................................................................................................1074 Chapter 41 Periodic Interrupt Timer (PIT) 41.1 Introduction...................................................................................................................................................................1075 41.1.1 Block diagram..............................................................................................................................................1075 41.1.2 Features........................................................................................................................................................1076 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 35 General Business Information

Page 36

Section number Title Page 41.2 Signal description..........................................................................................................................................................1076 41.3 Memory map/register description.................................................................................................................................1077 41.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................1078 41.3.2 Timer Load Value Register (PIT_LDVALn)...............................................................................................1078 41.3.3 Current Timer Value Register (PIT_CVALn).............................................................................................1079 41.3.4 Timer Control Register (PIT_TCTRLn)......................................................................................................1079 41.3.5 Timer Flag Register (PIT_TFLGn)..............................................................................................................1080 41.4 Functional description...................................................................................................................................................1081 41.4.1 General operation.........................................................................................................................................1081 41.4.2 Interrupts......................................................................................................................................................1082 41.4.3 Chained timers.............................................................................................................................................1083 41.5 Initialization and application information.....................................................................................................................1083 41.6 Example configuration for chained timers....................................................................................................................1084 Chapter 42 Low-Power Timer (LPTMR) 42.1 Introduction...................................................................................................................................................................1087 42.1.1 Features........................................................................................................................................................1087 42.1.2 Modes of operation......................................................................................................................................1087 42.2 LPTMR signal descriptions..........................................................................................................................................1088 42.2.1 Detailed signal descriptions.........................................................................................................................1088 42.3 Memory map and register definition.............................................................................................................................1089 42.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................1089 42.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................1091 42.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................1092 42.3.4 Low Power Timer Counter Register (LPTMRx_CNR)...............................................................................1093 42.4 Functional description...................................................................................................................................................1093 42.4.1 LPTMR power and reset..............................................................................................................................1093 42.4.2 LPTMR clocking..........................................................................................................................................1093 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 36 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 37

Section number Title Page 42.4.3 LPTMR prescaler/glitch filter......................................................................................................................1094 42.4.4 LPTMR compare..........................................................................................................................................1095 42.4.5 LPTMR counter...........................................................................................................................................1095 42.4.6 LPTMR hardware trigger.............................................................................................................................1096 42.4.7 LPTMR interrupt..........................................................................................................................................1096 Chapter 43 Carrier Modulator Transmitter (CMT) 43.1 Introduction...................................................................................................................................................................1099 43.2 Features.........................................................................................................................................................................1099 43.3 Block diagram...............................................................................................................................................................1100 43.4 Modes of operation.......................................................................................................................................................1101 43.4.1 Wait mode operation....................................................................................................................................1102 43.4.2 Stop mode operation....................................................................................................................................1103 43.5 CMT external signal descriptions.................................................................................................................................1103 43.5.1 CMT_IRO — Infrared Output.....................................................................................................................1103 43.6 Memory map/register definition...................................................................................................................................1104 43.6.1 CMT Carrier Generator High Data Register 1 (CMT_CGH1)....................................................................1105 43.6.2 CMT Carrier Generator Low Data Register 1 (CMT_CGL1).....................................................................1106 43.6.3 CMT Carrier Generator High Data Register 2 (CMT_CGH2)....................................................................1106 43.6.4 CMT Carrier Generator Low Data Register 2 (CMT_CGL2).....................................................................1107 43.6.5 CMT Output Control Register (CMT_OC).................................................................................................1107 43.6.6 CMT Modulator Status and Control Register (CMT_MSC).......................................................................1108 43.6.7 CMT Modulator Data Register Mark High (CMT_CMD1)........................................................................1110 43.6.8 CMT Modulator Data Register Mark Low (CMT_CMD2).........................................................................1111 43.6.9 CMT Modulator Data Register Space High (CMT_CMD3).......................................................................1111 43.6.10 CMT Modulator Data Register Space Low (CMT_CMD4)........................................................................1112 43.6.11 CMT Primary Prescaler Register (CMT_PPS)............................................................................................1112 43.6.12 CMT Direct Memory Access Register (CMT_DMA).................................................................................1113 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 37 General Business Information

Page 38

Section number Title Page 43.7 Functional description...................................................................................................................................................1114 43.7.1 Clock divider................................................................................................................................................1114 43.7.2 Carrier generator..........................................................................................................................................1114 43.7.3 Modulator.....................................................................................................................................................1117 43.7.4 Extended space operation.............................................................................................................................1121 43.8 CMT interrupts and DMA............................................................................................................................................1123 Chapter 44 Real Time Clock (RTC) 44.1 Introduction...................................................................................................................................................................1125 44.1.1 Features........................................................................................................................................................1125 44.1.2 Modes of operation......................................................................................................................................1125 44.1.3 RTC Signal Descriptions.............................................................................................................................1126 44.2 Register definition.........................................................................................................................................................1127 44.2.1 RTC Time Seconds Register (RTC_TSR)...................................................................................................1128 44.2.2 RTC Time Prescaler Register (RTC_TPR)..................................................................................................1128 44.2.3 RTC Time Alarm Register (RTC_TAR).....................................................................................................1129 44.2.4 RTC Time Compensation Register (RTC_TCR).........................................................................................1129 44.2.5 RTC Control Register (RTC_CR)................................................................................................................1130 44.2.6 RTC Status Register (RTC_SR)..................................................................................................................1132 44.2.7 RTC Lock Register (RTC_LR)....................................................................................................................1133 44.2.8 RTC Interrupt Enable Register (RTC_IER).................................................................................................1134 44.2.9 RTC Write Access Register (RTC_WAR)..................................................................................................1135 44.2.10 RTC Read Access Register (RTC_RAR)....................................................................................................1137 44.3 Functional description...................................................................................................................................................1138 44.3.1 Power, clocking, and reset...........................................................................................................................1138 44.3.2 Time counter................................................................................................................................................1139 44.3.3 Compensation...............................................................................................................................................1140 44.3.4 Time alarm...................................................................................................................................................1140 44.3.5 Update mode................................................................................................................................................1141 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 38 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 39

Section number Title Page 44.3.6 Register lock................................................................................................................................................1141 44.3.7 Access control..............................................................................................................................................1141 44.3.8 Interrupt........................................................................................................................................................1141 Chapter 45 10/100-Mbps Ethernet MAC (ENET) 45.1 Introduction...................................................................................................................................................................1143 45.1.1 Overview......................................................................................................................................................1143 45.1.2 Features........................................................................................................................................................1144 45.1.3 Block diagram..............................................................................................................................................1146 45.2 External signal description............................................................................................................................................1147 45.3 Memory map/register definition...................................................................................................................................1149 45.3.1 Interrupt Event Register (ENET_EIR).........................................................................................................1152 45.3.2 Interrupt Mask Register (ENET_EIMR)......................................................................................................1154 45.3.3 Receive Descriptor Active Register (ENET_RDAR)..................................................................................1157 45.3.4 Transmit Descriptor Active Register (ENET_TDAR).................................................................................1158 45.3.5 Ethernet Control Register (ENET_ECR).....................................................................................................1159 45.3.6 MII Management Frame Register (ENET_MMFR)....................................................................................1161 45.3.7 MII Speed Control Register (ENET_MSCR)..............................................................................................1162 45.3.8 MIB Control Register (ENET_MIBC)........................................................................................................1164 45.3.9 Receive Control Register (ENET_RCR).....................................................................................................1165 45.3.10 Transmit Control Register (ENET_TCR)....................................................................................................1168 45.3.11 Physical Address Lower Register (ENET_PALR)......................................................................................1170 45.3.12 Physical Address Upper Register (ENET_PAUR)......................................................................................1170 45.3.13 Opcode/Pause Duration Register (ENET_OPD).........................................................................................1171 45.3.14 Descriptor Individual Upper Address Register (ENET_IAUR)..................................................................1171 45.3.15 Descriptor Individual Lower Address Register (ENET_IALR)..................................................................1172 45.3.16 Descriptor Group Upper Address Register (ENET_GAUR).......................................................................1172 45.3.17 Descriptor Group Lower Address Register (ENET_GALR).......................................................................1173 45.3.18 Transmit FIFO Watermark Register (ENET_TFWR).................................................................................1173 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 39 General Business Information

Page 40

Section number Title Page 45.3.19 Receive Descriptor Ring Start Register (ENET_RDSR).............................................................................1174 45.3.20 Transmit Buffer Descriptor Ring Start Register (ENET_TDSR)................................................................1175 45.3.21 Maximum Receive Buffer Size Register (ENET_MRBR)..........................................................................1175 45.3.22 Receive FIFO Section Full Threshold (ENET_RSFL)................................................................................1176 45.3.23 Receive FIFO Section Empty Threshold (ENET_RSEM)..........................................................................1176 45.3.24 Receive FIFO Almost Empty Threshold (ENET_RAEM)..........................................................................1177 45.3.25 Receive FIFO Almost Full Threshold (ENET_RAFL)................................................................................1177 45.3.26 Transmit FIFO Section Empty Threshold (ENET_TSEM).........................................................................1178 45.3.27 Transmit FIFO Almost Empty Threshold (ENET_TAEM).........................................................................1178 45.3.28 Transmit FIFO Almost Full Threshold (ENET_TAFL)..............................................................................1178 45.3.29 Transmit Inter-Packet Gap (ENET_TIPG)..................................................................................................1179 45.3.30 Frame Truncation Length (ENET_FTRL)...................................................................................................1179 45.3.31 Transmit Accelerator Function Configuration (ENET_TACC)..................................................................1180 45.3.32 Receive Accelerator Function Configuration (ENET_RACC)....................................................................1181 45.3.33 Timer Control Register (ENET_ATCR)......................................................................................................1182 45.3.34 Timer Value Register (ENET_ATVR)........................................................................................................1184 45.3.35 Timer Offset Register (ENET_ATOFF)......................................................................................................1184 45.3.36 Timer Period Register (ENET_ATPER)......................................................................................................1185 45.3.37 Timer Correction Register (ENET_ATCOR)..............................................................................................1185 45.3.38 Time-Stamping Clock Period Register (ENET_ATINC)............................................................................1186 45.3.39 Timestamp of Last Transmitted Frame (ENET_ATSTMP)........................................................................1186 45.3.40 Timer Global Status Register (ENET_TGSR).............................................................................................1187 45.3.41 Timer Control Status Register (ENET_TCSRn)..........................................................................................1188 45.3.42 Timer Compare Capture Register (ENET_TCCRn)....................................................................................1189 45.3.43 Statistic event counters.................................................................................................................................1189 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 40 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 41

Section number Title Page 45.4 Functional description...................................................................................................................................................1192 45.4.1 Ethernet MAC frame formats......................................................................................................................1192 45.4.2 IP and higher layers frame format................................................................................................................1195 45.4.3 IEEE 1588 message formats........................................................................................................................1199 45.4.4 MAC receive................................................................................................................................................1203 45.4.5 MAC transmit..............................................................................................................................................1208 45.4.6 Full-duplex flow control operation..............................................................................................................1212 45.4.7 Magic packet detection................................................................................................................................1214 45.4.8 IP accelerator functions................................................................................................................................1215 45.4.9 Resets and stop controls...............................................................................................................................1220 45.4.10 IEEE 1588 functions....................................................................................................................................1223 45.4.11 FIFO thresholds............................................................................................................................................1226 45.4.12 Loopback options.........................................................................................................................................1229 45.4.13 Legacy buffer descriptors.............................................................................................................................1230 45.4.14 Enhanced buffer descriptors.........................................................................................................................1231 45.4.15 Client FIFO application interface................................................................................................................1237 45.4.16 FIFO protection............................................................................................................................................1240 45.4.17 PHY management interface.........................................................................................................................1243 45.4.18 Ethernet interfaces........................................................................................................................................1244 Chapter 46 Universal Serial Bus OTG Controller (USBOTG) 46.1 Introduction...................................................................................................................................................................1249 46.1.1 USB..............................................................................................................................................................1249 46.1.2 USB On-The-Go..........................................................................................................................................1250 46.1.3 USB-FS Features..........................................................................................................................................1251 46.2 Functional description...................................................................................................................................................1252 46.2.1 Data Structures.............................................................................................................................................1252 46.3 Programmers interface..................................................................................................................................................1252 46.3.1 Buffer Descriptor Table...............................................................................................................................1252 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 41 General Business Information

Page 42

Section number Title Page 46.3.2 RX vs. TX as a USB target device or USB host..........................................................................................1253 46.3.3 Addressing BDT entries...............................................................................................................................1254 46.3.4 Buffer Descriptors (BDs).............................................................................................................................1254 46.3.5 USB transaction...........................................................................................................................................1257 46.4 Memory map/Register definitions................................................................................................................................1259 46.4.1 Peripheral ID register (USBx_PERID)........................................................................................................1261 46.4.2 Peripheral ID Complement register (USBx_IDCOMP)...............................................................................1262 46.4.3 Peripheral Revision register (USBx_REV)..................................................................................................1262 46.4.4 Peripheral Additional Info register (USBx_ADDINFO).............................................................................1263 46.4.5 OTG Interrupt Status register (USBx_OTGISTAT)....................................................................................1263 46.4.6 OTG Interrupt Control Register (USBx_OTGICR).....................................................................................1264 46.4.7 OTG Status register (USBx_OTGSTAT)....................................................................................................1265 46.4.8 OTG Control register (USBx_OTGCTL)....................................................................................................1266 46.4.9 Interrupt Status register (USBx_ISTAT).....................................................................................................1267 46.4.10 Interrupt Enable register (USBx_INTEN)...................................................................................................1268 46.4.11 Error Interrupt Status register (USBx_ERRSTAT).....................................................................................1269 46.4.12 Error Interrupt Enable register (USBx_ERREN).........................................................................................1270 46.4.13 Status register (USBx_STAT)......................................................................................................................1271 46.4.14 Control register (USBx_CTL)......................................................................................................................1272 46.4.15 Address register (USBx_ADDR).................................................................................................................1273 46.4.16 BDT Page Register 1 (USBx_BDTPAGE1)................................................................................................1274 46.4.17 Frame Number Register Low (USBx_FRMNUML)...................................................................................1274 46.4.18 Frame Number Register High (USBx_FRMNUMH)..................................................................................1275 46.4.19 Token register (USBx_TOKEN)..................................................................................................................1275 46.4.20 SOF Threshold Register (USBx_SOFTHLD)..............................................................................................1276 46.4.21 BDT Page Register 2 (USBx_BDTPAGE2)................................................................................................1277 46.4.22 BDT Page Register 3 (USBx_BDTPAGE3)................................................................................................1277 46.4.23 Endpoint Control register (USBx_ENDPTn)...............................................................................................1277 46.4.24 USB Control register (USBx_USBCTRL)..................................................................................................1278 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 42 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 43

Section number Title Page 46.4.25 USB OTG Observe register (USBx_OBSERVE)........................................................................................1279 46.4.26 USB OTG Control register (USBx_CONTROL)........................................................................................1280 46.4.27 USB Transceiver Control Register 0 (USBx_USBTRC0)...........................................................................1280 46.4.28 Frame Adjust Register (USBx_USBFRMADJUST)...................................................................................1281 46.5 OTG and Host mode operation.....................................................................................................................................1282 46.6 Host Mode Operation Examples...................................................................................................................................1282 46.7 On-The-Go operation....................................................................................................................................................1285 46.7.1 OTG dual role A device operation...............................................................................................................1286 46.7.2 OTG dual role B device operation...............................................................................................................1287 Chapter 47 USB Device Charger Detection Module (USBDCD) 47.1 Preface...........................................................................................................................................................................1289 47.1.1 References....................................................................................................................................................1289 47.1.2 Acronyms and abbreviations........................................................................................................................1289 47.1.3 Glossary.......................................................................................................................................................1290 47.2 Introduction...................................................................................................................................................................1290 47.2.1 Block diagram..............................................................................................................................................1290 47.2.2 Features........................................................................................................................................................1291 47.2.3 Modes of operation......................................................................................................................................1291 47.3 Module signal descriptions...........................................................................................................................................1292 47.4 Memory map/Register definition..................................................................................................................................1293 47.4.1 Control register (USBDCD_CONTROL)....................................................................................................1294 47.4.2 Clock register (USBDCD_CLOCK)............................................................................................................1295 47.4.3 Status register (USBDCD_STATUS)..........................................................................................................1297 47.4.4 TIMER0 register (USBDCD_TIMER0)......................................................................................................1298 47.4.5 TIMER1 register (USBDCD_TIMER1)......................................................................................................1299 47.4.6 TIMER2 register (USBDCD_TIMER2)......................................................................................................1300 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 43 General Business Information

Page 44

Section number Title Page 47.5 Functional description...................................................................................................................................................1301 47.5.1 The charger detection sequence...................................................................................................................1302 47.5.2 Interrupts and events....................................................................................................................................1311 47.5.3 Resets...........................................................................................................................................................1313 47.6 Initialization information..............................................................................................................................................1314 47.7 Application information................................................................................................................................................1314 47.7.1 External pullups...........................................................................................................................................1314 47.7.2 Dead or weak battery...................................................................................................................................1314 47.7.3 Handling unplug events...............................................................................................................................1315 Chapter 48 USB Voltage Regulator 48.1 Introduction...................................................................................................................................................................1317 48.1.1 Overview......................................................................................................................................................1318 48.1.2 Features........................................................................................................................................................1319 48.1.3 Modes of Operation.....................................................................................................................................1319 48.2 USB Voltage Regulator Module Signal Descriptions..................................................................................................1320 Chapter 49 CAN (FlexCAN) 49.1 Introduction...................................................................................................................................................................1321 49.1.1 Overview......................................................................................................................................................1322 49.1.2 FlexCAN module features...........................................................................................................................1323 49.1.3 Modes of operation......................................................................................................................................1324 49.2 FlexCAN signal descriptions........................................................................................................................................1326 49.2.1 CAN Rx .......................................................................................................................................................1326 49.2.2 CAN Tx .......................................................................................................................................................1326 49.3 Memory map/register definition...................................................................................................................................1326 49.3.1 FlexCAN memory mapping.........................................................................................................................1326 49.3.2 Module Configuration Register (CANx_MCR)...........................................................................................1331 49.3.3 Control 1 register (CANx_CTRL1).............................................................................................................1336 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 44 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 45

Section number Title Page 49.3.4 Free Running Timer (CANx_TIMER).........................................................................................................1339 49.3.5 Rx Mailboxes Global Mask Register (CANx_RXMGMASK)....................................................................1340 49.3.6 Rx 14 Mask register (CANx_RX14MASK)................................................................................................1341 49.3.7 Rx 15 Mask register (CANx_RX15MASK)................................................................................................1342 49.3.8 Error Counter (CANx_ECR)........................................................................................................................1342 49.3.9 Error and Status 1 register (CANx_ESR1)..................................................................................................1344 49.3.10 Interrupt Masks 1 register (CANx_IMASK1).............................................................................................1348 49.3.11 Interrupt Flags 1 register (CANx_IFLAG1)................................................................................................1349 49.3.12 Control 2 register (CANx_CTRL2).............................................................................................................1351 49.3.13 Error and Status 2 register (CANx_ESR2)..................................................................................................1354 49.3.14 CRC Register (CANx_CRCR).....................................................................................................................1355 49.3.15 Rx FIFO Global Mask register (CANx_RXFGMASK)..............................................................................1356 49.3.16 Rx FIFO Information Register (CANx_RXFIR).........................................................................................1357 49.3.17 Rx Individual Mask Registers (CANx_RXIMRn).......................................................................................1358 49.3.50 Message buffer structure..............................................................................................................................1359 49.3.51 Rx FIFO structure........................................................................................................................................1364 49.4 Functional description...................................................................................................................................................1366 49.4.1 Transmit process..........................................................................................................................................1367 49.4.2 Arbitration process.......................................................................................................................................1368 49.4.3 Receive process............................................................................................................................................1371 49.4.4 Matching process.........................................................................................................................................1373 49.4.5 Move process...............................................................................................................................................1378 49.4.6 Data coherence.............................................................................................................................................1380 49.4.7 Rx FIFO.......................................................................................................................................................1383 49.4.8 CAN protocol related features.....................................................................................................................1385 49.4.9 Clock domains and restrictions....................................................................................................................1391 49.4.10 Modes of operation details...........................................................................................................................1392 49.4.11 Interrupts......................................................................................................................................................1395 49.4.12 Bus interface................................................................................................................................................1396 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 45 General Business Information

Page 46

Section number Title Page 49.5 Initialization/application information...........................................................................................................................1397 49.5.1 FlexCAN initialization sequence.................................................................................................................1397 Chapter 50 Serial Peripheral Interface (SPI) 50.1 Introduction...................................................................................................................................................................1401 50.1.1 Block Diagram.............................................................................................................................................1401 50.1.2 Features........................................................................................................................................................1402 50.1.3 SPI Configuration........................................................................................................................................1403 50.1.4 Modes of Operation.....................................................................................................................................1404 50.2 Module signal descriptions...........................................................................................................................................1406 50.2.1 PCS0/SS — Peripheral Chip Select/Slave Select........................................................................................1406 50.2.2 PCS1 – PCS3 — Peripheral Chip Selects 1 – 3...........................................................................................1406 50.2.3 PCS4 — Peripheral Chip Select 4................................................................................................................1406 50.2.4 SIN — Serial Input......................................................................................................................................1407 50.2.5 SOUT — Serial Output................................................................................................................................1407 50.2.6 SCK — Serial Clock....................................................................................................................................1407 50.3 Memory Map/Register Definition.................................................................................................................................1407 50.3.1 Module Configuration Register (SPIx_MCR).............................................................................................1410 50.3.2 Transfer Count Register (SPIx_TCR)..........................................................................................................1413 50.3.3 DSPI Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)......................................1413 50.3.4 Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)...................................1418 50.3.5 DSPI Status Register (SPIx_SR)..................................................................................................................1420 50.3.6 DMA/Interrupt Request Select and Enable Register (SPIx_RSER)............................................................1423 50.3.7 PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)........................................................................1425 50.3.8 PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)............................................................1427 50.3.9 POP RX FIFO Register (SPIx_POPR).........................................................................................................1427 50.3.10 DSPI Transmit FIFO Registers (SPIx_TXFRn)...........................................................................................1428 50.3.11 DSPI Receive FIFO Registers (SPIx_RXFRn)............................................................................................1428 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 46 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 47

Section number Title Page 50.4 Functional description...................................................................................................................................................1429 50.4.1 Start and Stop of module transfers...............................................................................................................1430 50.4.2 Serial Peripheral Interface (SPI) configuration............................................................................................1430 50.4.3 Module baud rate and clock delay generation.............................................................................................1434 50.4.4 Transfer formats...........................................................................................................................................1436 50.4.5 Continuous Serial Communications Clock..................................................................................................1441 50.4.6 Slave Mode Operation Constraints..............................................................................................................1443 50.4.7 Interrupts/DMA requests..............................................................................................................................1443 50.4.8 Power saving features..................................................................................................................................1446 50.5 Initialization/application information...........................................................................................................................1447 50.5.1 How to manage queues................................................................................................................................1447 50.5.2 Switching Master and Slave mode...............................................................................................................1448 50.5.3 Initializing Module in Master/Slave Modes.................................................................................................1448 50.5.4 Baud rate settings.........................................................................................................................................1448 50.5.5 Delay settings...............................................................................................................................................1449 50.5.6 Calculation of FIFO pointer addresses.........................................................................................................1450 Chapter 51 Inter-Integrated Circuit (I2C) 51.1 Introduction...................................................................................................................................................................1453 51.1.1 Features........................................................................................................................................................1453 51.1.2 Modes of operation......................................................................................................................................1454 51.1.3 Block diagram..............................................................................................................................................1454 51.2 I2C signal descriptions..................................................................................................................................................1455 51.3 Memory map and register descriptions.........................................................................................................................1455 51.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................1456 51.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................1457 51.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................1458 51.3.4 I2C Status register (I2Cx_S)........................................................................................................................1460 51.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................1461 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 47 General Business Information

Page 48

Section number Title Page 51.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................1462 51.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................1463 51.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................1464 51.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................1464 51.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................1466 51.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................1466 51.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................1467 51.4 Functional description...................................................................................................................................................1467 51.4.1 I2C protocol.................................................................................................................................................1467 51.4.2 10-bit address...............................................................................................................................................1472 51.4.3 Address matching.........................................................................................................................................1474 51.4.4 System management bus specification........................................................................................................1474 51.4.5 Resets...........................................................................................................................................................1477 51.4.6 Interrupts......................................................................................................................................................1477 51.4.7 Programmable input glitch filter..................................................................................................................1479 51.4.8 Address matching wakeup...........................................................................................................................1480 51.4.9 DMA support...............................................................................................................................................1480 51.5 Initialization/application information...........................................................................................................................1481 Chapter 52 Universal Asynchronous Receiver/Transmitter (UART) 52.1 Introduction...................................................................................................................................................................1485 52.1.1 Features........................................................................................................................................................1485 52.1.2 Modes of operation......................................................................................................................................1487 52.2 UART signal descriptions.............................................................................................................................................1488 52.2.1 Detailed signal descriptions.........................................................................................................................1489 52.3 Memory map and registers............................................................................................................................................1490 52.3.1 UART Baud Rate Registers: High (UARTx_BDH)....................................................................................1504 52.3.2 UART Baud Rate Registers: Low (UARTx_BDL).....................................................................................1505 52.3.3 UART Control Register 1 (UARTx_C1).....................................................................................................1506 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 48 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 49

Section number Title Page 52.3.4 UART Control Register 2 (UARTx_C2).....................................................................................................1507 52.3.5 UART Status Register 1 (UARTx_S1)........................................................................................................1509 52.3.6 UART Status Register 2 (UARTx_S2)........................................................................................................1512 52.3.7 UART Control Register 3 (UARTx_C3).....................................................................................................1514 52.3.8 UART Data Register (UARTx_D)...............................................................................................................1515 52.3.9 UART Match Address Registers 1 (UARTx_MA1)....................................................................................1517 52.3.10 UART Match Address Registers 2 (UARTx_MA2)....................................................................................1517 52.3.11 UART Control Register 4 (UARTx_C4).....................................................................................................1517 52.3.12 UART Control Register 5 (UARTx_C5).....................................................................................................1518 52.3.13 UART Extended Data Register (UARTx_ED)............................................................................................1519 52.3.14 UART Modem Register (UARTx_MODEM).............................................................................................1520 52.3.15 UART Infrared Register (UARTx_IR)........................................................................................................1521 52.3.16 UART FIFO Parameters (UARTx_PFIFO).................................................................................................1522 52.3.17 UART FIFO Control Register (UARTx_CFIFO)........................................................................................1524 52.3.18 UART FIFO Status Register (UARTx_SFIFO)...........................................................................................1525 52.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO).............................................................................1526 52.3.20 UART FIFO Transmit Count (UARTx_TCFIFO).......................................................................................1527 52.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)...............................................................................1527 52.3.22 UART FIFO Receive Count (UARTx_RCFIFO)........................................................................................1528 52.3.23 UART 7816 Control Register (UARTx_C7816).........................................................................................1528 52.3.24 UART 7816 Interrupt Enable Register (UARTx_IE7816)..........................................................................1530 52.3.25 UART 7816 Interrupt Status Register (UARTx_IS7816)............................................................................1531 52.3.26 UART 7816 Wait Parameter Register (UARTx_WP7816T0).....................................................................1532 52.3.27 UART 7816 Wait Parameter Register (UARTx_WP7816T1).....................................................................1533 52.3.28 UART 7816 Wait N Register (UARTx_WN7816)......................................................................................1533 52.3.29 UART 7816 Wait FD Register (UARTx_WF7816)....................................................................................1534 52.3.30 UART 7816 Error Threshold Register (UARTx_ET7816)..........................................................................1534 52.3.31 UART 7816 Transmit Length Register (UARTx_TL7816)........................................................................1535 52.3.32 UART CEA709.1-B Control Register 6 (UARTx_C6)...............................................................................1536 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 49 General Business Information

Page 50

Section number Title Page 52.3.33 UART CEA709.1-B Packet Cycle Time Counter High (UARTx_PCTH)..................................................1536 52.3.34 UART CEA709.1-B Packet Cycle Time Counter Low (UARTx_PCTL)...................................................1537 52.3.35 UART CEA709.1-B Interrupt Enable Register 0 (UARTx_IE0)................................................................1537 52.3.36 UART CEA709.1-B Secondary Delay Timer High (UARTx_SDTH)........................................................1538 52.3.37 UART CEA709.1-B Secondary Delay Timer Low (UARTx_SDTL).........................................................1538 52.3.38 UART CEA709.1-B Preamble (UARTx_PRE)...........................................................................................1539 52.3.39 UART CEA709.1-B Transmit Packet Length (UARTx_TPL)....................................................................1539 52.3.40 UART CEA709.1-B Interrupt Enable Register (UARTx_IE).....................................................................1540 52.3.41 UART CEA709.1-B WBASE (UARTx_WB).............................................................................................1541 52.3.42 UART CEA709.1-B Status Register (UARTx_S3).....................................................................................1541 52.3.43 UART CEA709.1-B Status Register (UARTx_S4).....................................................................................1543 52.3.44 UART CEA709.1-B Received Packet Length (UARTx_RPL)...................................................................1544 52.3.45 UART CEA709.1-B Received Preamble Length (UARTx_RPREL)..........................................................1544 52.3.46 UART CEA709.1-B Collision Pulse Width (UARTx_CPW).....................................................................1544 52.3.47 UART CEA709.1-B Receive Indeterminate Time High (UARTx_RIDTH)...............................................1545 52.3.48 UART CEA709.1-B Receive Indeterminate Time Low (UARTx_RIDTL)................................................1545 52.3.49 UART CEA709.1-B Transmit Indeterminate Time High (UARTx_TIDTH).............................................1546 52.3.50 UART CEA709.1-B Transmit Indeterminate Time Low (UARTx_TIDTL)..............................................1546 52.3.51 UART CEA709.1-B Receive Beta1 Timer High (UARTx_RB1TH)..........................................................1546 52.3.52 UART CEA709.1-B Receive Beta1 Timer Low (UARTx_RB1TL)...........................................................1547 52.3.53 UART CEA709.1-B Transmit Beta1 Timer High (UARTx_TB1TH)........................................................1547 52.3.54 UART CEA709.1-B Transmit Beta1 Timer Low (UARTx_TB1TL)..........................................................1548 52.3.55 UART CEA709.1-B Programmable register (UARTx_PROG_REG)........................................................1548 52.3.56 UART CEA709.1-B State register (UARTx_STATE_REG)......................................................................1549 52.4 Functional description...................................................................................................................................................1549 52.4.1 CEA709.1-B.................................................................................................................................................1549 52.4.2 Transmitter...................................................................................................................................................1560 52.4.3 Receiver.......................................................................................................................................................1566 52.4.4 Baud rate generation....................................................................................................................................1575 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 50 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 51

Section number Title Page 52.4.5 Data format (non ISO-7816)........................................................................................................................1577 52.4.6 Single-wire operation...................................................................................................................................1580 52.4.7 Loop operation.............................................................................................................................................1581 52.4.8 ISO-7816/smartcard support........................................................................................................................1581 52.4.9 Infrared interface..........................................................................................................................................1586 52.5 Reset..............................................................................................................................................................................1587 52.6 System level interrupt sources......................................................................................................................................1587 52.6.1 RXEDGIF description..................................................................................................................................1588 52.7 DMA operation.............................................................................................................................................................1589 52.8 Application information................................................................................................................................................1589 52.8.1 Transmit/receive data buffer operation........................................................................................................1589 52.8.2 ISO-7816 initialization sequence.................................................................................................................1590 52.8.3 Initialization sequence (non ISO-7816).......................................................................................................1592 52.8.4 Overrun (OR) flag implications...................................................................................................................1593 52.8.5 Overrun NACK considerations....................................................................................................................1594 52.8.6 Match address registers................................................................................................................................1595 52.8.7 Modem feature.............................................................................................................................................1595 52.8.8 IrDA minimum pulse width.........................................................................................................................1596 52.8.9 Clearing 7816 wait timer (WT, BWT, CWT) interrupts..............................................................................1596 52.8.10 Legacy and reverse compatibility considerations........................................................................................1597 Chapter 53 Secured digital host controller (SDHC) 53.1 Introduction...................................................................................................................................................................1599 53.2 Overview.......................................................................................................................................................................1599 53.2.1 Supported types of cards..............................................................................................................................1599 53.2.2 SDHC block diagram...................................................................................................................................1600 53.2.3 Features........................................................................................................................................................1601 53.2.4 Modes and operations..................................................................................................................................1602 53.3 SDHC signal descriptions.............................................................................................................................................1603 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 51 General Business Information

Page 52

Section number Title Page 53.4 Memory map and register definition.............................................................................................................................1604 53.4.1 DMA System Address register (SDHC_DSADDR)....................................................................................1605 53.4.2 Block Attributes register (SDHC_BLKATTR)...........................................................................................1606 53.4.3 Command Argument register (SDHC_CMDARG).....................................................................................1607 53.4.4 Transfer Type register (SDHC_XFERTYP)................................................................................................1608 53.4.5 Command Response 0 (SDHC_CMDRSP0)...............................................................................................1612 53.4.6 Command Response 1 (SDHC_CMDRSP1)...............................................................................................1612 53.4.7 Command Response 2 (SDHC_CMDRSP2)...............................................................................................1613 53.4.8 Command Response 3 (SDHC_CMDRSP3)...............................................................................................1613 53.4.9 Buffer Data Port register (SDHC_DATPORT)...........................................................................................1614 53.4.10 Present State register (SDHC_PRSSTAT)..................................................................................................1615 53.4.11 Protocol Control register (SDHC_PROCTL)..............................................................................................1620 53.4.12 System Control register (SDHC_SYSCTL)................................................................................................1624 53.4.13 Interrupt Status register (SDHC_IRQSTAT)...............................................................................................1627 53.4.14 Interrupt Status Enable register (SDHC_IRQSTATEN).............................................................................1632 53.4.15 Interrupt Signal Enable register (SDHC_IRQSIGEN)................................................................................1635 53.4.16 Auto CMD12 Error Status Register (SDHC_AC12ERR)...........................................................................1637 53.4.17 Host Controller Capabilities (SDHC_HTCAPBLT)....................................................................................1641 53.4.18 Watermark Level Register (SDHC_WML).................................................................................................1643 53.4.19 Force Event register (SDHC_FEVT)...........................................................................................................1644 53.4.20 ADMA Error Status register (SDHC_ADMAES).......................................................................................1646 53.4.21 ADMA System Addressregister (SDHC_ADSADDR)...............................................................................1648 53.4.22 Vendor Specific register (SDHC_VENDOR)..............................................................................................1649 53.4.23 MMC Boot register (SDHC_MMCBOOT).................................................................................................1650 53.4.24 Host Controller Version (SDHC_HOSTVER)............................................................................................1651 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 52 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 53

Section number Title Page 53.5 Functional description...................................................................................................................................................1652 53.5.1 Data buffer...................................................................................................................................................1652 53.5.2 DMA crossbar switch interface....................................................................................................................1658 53.5.3 SD protocol unit...........................................................................................................................................1664 53.5.4 Clock and reset manager..............................................................................................................................1666 53.5.5 Clock generator............................................................................................................................................1667 53.5.6 SDIO card interrupt......................................................................................................................................1667 53.5.7 Card insertion and removal detection..........................................................................................................1669 53.5.8 Power management and wakeup events.......................................................................................................1670 53.5.9 MMC fast boot.............................................................................................................................................1671 53.6 Initialization/application of SDHC...............................................................................................................................1673 53.6.1 Command send and response receive basic operation.................................................................................1673 53.6.2 Card Identification mode.............................................................................................................................1674 53.6.3 Card access...................................................................................................................................................1679 53.6.4 Switch function............................................................................................................................................1690 53.6.5 ADMA operation.........................................................................................................................................1692 53.6.6 Fast boot operation.......................................................................................................................................1693 53.6.7 Commands for MMC/SD/SDIO/CE-ATA...................................................................................................1697 53.7 Software restrictions.....................................................................................................................................................1703 53.7.1 Initialization active.......................................................................................................................................1703 53.7.2 Software polling procedure..........................................................................................................................1703 53.7.3 Suspend operation........................................................................................................................................1704 53.7.4 Data length setting.......................................................................................................................................1704 53.7.5 (A)DMA address setting..............................................................................................................................1704 53.7.6 Data port access...........................................................................................................................................1704 53.7.7 Change clock frequency...............................................................................................................................1704 53.7.8 Multi-block read...........................................................................................................................................1705 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 53 General Business Information

Page 54

Section number Title Page Chapter 54 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 54.1 Introduction...................................................................................................................................................................1707 54.1.1 Features........................................................................................................................................................1707 54.1.2 Block diagram..............................................................................................................................................1707 54.1.3 Modes of operation......................................................................................................................................1708 54.2 External signals.............................................................................................................................................................1709 54.3 Memory map and register definition.............................................................................................................................1709 54.3.1 SAI Transmit Control Register (I2Sx_TCSR).............................................................................................1711 54.3.2 SAI Transmit Configuration 1 Register (I2Sx_TCR1)................................................................................1714 54.3.3 SAI Transmit Configuration 2 Register (I2Sx_TCR2)................................................................................1714 54.3.4 SAI Transmit Configuration 3 Register (I2Sx_TCR3)................................................................................1716 54.3.5 SAI Transmit Configuration 4 Register (I2Sx_TCR4)................................................................................1717 54.3.6 SAI Transmit Configuration 5 Register (I2Sx_TCR5)................................................................................1718 54.3.7 SAI Transmit Data Register (I2Sx_TDRn)..................................................................................................1719 54.3.8 SAI Transmit FIFO Register (I2Sx_TFRn).................................................................................................1719 54.3.9 SAI Transmit Mask Register (I2Sx_TMR)..................................................................................................1720 54.3.10 SAI Receive Control Register (I2Sx_RCSR)...............................................................................................1721 54.3.11 SAI Receive Configuration 1 Register (I2Sx_RCR1)..................................................................................1724 54.3.12 SAI Receive Configuration 2 Register (I2Sx_RCR2)..................................................................................1724 54.3.13 SAI Receive Configuration 3 Register (I2Sx_RCR3)..................................................................................1726 54.3.14 SAI Receive Configuration 4 Register (I2Sx_RCR4)..................................................................................1727 54.3.15 SAI Receive Configuration 5 Register (I2Sx_RCR5)..................................................................................1728 54.3.16 SAI Receive Data Register (I2Sx_RDRn)...................................................................................................1729 54.3.17 SAI Receive FIFO Register (I2Sx_RFRn)...................................................................................................1729 54.3.18 SAI Receive Mask Register (I2Sx_RMR)...................................................................................................1730 54.3.19 SAI MCLK Control Register (I2Sx_MCR).................................................................................................1730 54.3.20 SAI MCLK Divide Register (I2Sx_MDR)..................................................................................................1731 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 54 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 55

Section number Title Page 54.4 Functional description...................................................................................................................................................1732 54.4.1 SAI clocking................................................................................................................................................1732 54.4.2 SAI resets.....................................................................................................................................................1733 54.4.3 Synchronous modes.....................................................................................................................................1734 54.4.4 Frame sync configuration.............................................................................................................................1735 54.5 Data FIFO.....................................................................................................................................................................1735 54.5.1 Data alignment.............................................................................................................................................1735 54.5.2 FIFO pointers...............................................................................................................................................1736 54.5.3 Word mask register......................................................................................................................................1737 54.5.4 Interrupts and DMA requests.......................................................................................................................1737 Chapter 55 General-Purpose Input/Output (GPIO) 55.1 Introduction...................................................................................................................................................................1741 55.1.1 Features........................................................................................................................................................1741 55.1.2 Modes of operation......................................................................................................................................1742 55.1.3 GPIO signal descriptions.............................................................................................................................1742 55.2 Memory map and register definition.............................................................................................................................1743 55.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................1745 55.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................1746 55.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................1746 55.2.4 Port Toggle Output Register (GPIOx_PTOR).............................................................................................1747 55.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................1747 55.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................1748 55.3 Functional description...................................................................................................................................................1748 55.3.1 General-purpose input..................................................................................................................................1748 55.3.2 General-purpose output................................................................................................................................1748 Chapter 56 Touch sense input (TSI) 56.1 Introduction...................................................................................................................................................................1751 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 55 General Business Information

Page 56

Section number Title Page 56.2 Features.........................................................................................................................................................................1751 56.3 Overview.......................................................................................................................................................................1752 56.3.1 Electrode capacitance measurement unit.....................................................................................................1753 56.3.2 Electrode scan unit.......................................................................................................................................1754 56.3.3 Touch detection unit.....................................................................................................................................1754 56.4 Modes of operation.......................................................................................................................................................1755 56.4.1 TSI disabled mode.......................................................................................................................................1756 56.4.2 TSI active mode...........................................................................................................................................1756 56.4.3 TSI low-power mode...................................................................................................................................1756 56.4.4 Block diagram..............................................................................................................................................1756 56.5 TSI signal descriptions..................................................................................................................................................1757 56.5.1 TSI_IN[15:0]................................................................................................................................................1757 56.6 Memory map and register definition.............................................................................................................................1758 56.6.1 General Control and Status register (TSIx_GENCS)...................................................................................1759 56.6.2 SCAN Control register (TSIx_SCANC)......................................................................................................1762 56.6.3 Pin Enable register (TSIx_PEN)..................................................................................................................1764 56.6.4 Wake-Up Channel Counter Register (TSIx_WUCNTR).............................................................................1766 56.6.5 Counter Register (TSIx_CNTRn)................................................................................................................1767 56.6.6 Low-Power Channel Threshold register (TSIx_THRESHOLD).................................................................1767 56.7 Functional description...................................................................................................................................................1767 56.7.1 Capacitance measurement............................................................................................................................1768 56.7.2 TSI measurement result...............................................................................................................................1771 56.7.3 Electrode scan unit.......................................................................................................................................1772 56.7.4 Touch detection unit.....................................................................................................................................1775 56.8 Application information................................................................................................................................................1776 56.8.1 TSI module sensitivity.................................................................................................................................1776 56.9 TSI module initialization..............................................................................................................................................1776 56.9.1 Initialization sequence..................................................................................................................................1777 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 56 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 57

Section number Title Page Chapter 57 JTAG Controller (JTAGC) 57.1 Introduction...................................................................................................................................................................1779 57.1.1 Block diagram..............................................................................................................................................1779 57.1.2 Features........................................................................................................................................................1780 57.1.3 Modes of operation......................................................................................................................................1780 57.2 External signal description............................................................................................................................................1782 57.2.1 TCK—Test clock input................................................................................................................................1782 57.2.2 TDI—Test data input...................................................................................................................................1782 57.2.3 TDO—Test data output................................................................................................................................1782 57.2.4 TMS—Test mode select...............................................................................................................................1782 57.3 Register description......................................................................................................................................................1783 57.3.1 Instruction register.......................................................................................................................................1783 57.3.2 Bypass register.............................................................................................................................................1783 57.3.3 Device identification register.......................................................................................................................1783 57.3.4 Boundary scan register.................................................................................................................................1784 57.4 Functional description...................................................................................................................................................1785 57.4.1 JTAGC reset configuration..........................................................................................................................1785 57.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port..............................................................................................1785 57.4.3 TAP controller state machine.......................................................................................................................1785 57.4.4 JTAGC block instructions............................................................................................................................1787 57.4.5 Boundary scan..............................................................................................................................................1790 57.5 Initialization/Application information..........................................................................................................................1790 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 57 General Business Information

Page 58

K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 58 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 59

Chapter 1 About This Document 1.1 Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale K60 microcontroller. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the K60 microcontroller in a system. 1.2 Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems: This suffix Identifies a b Binary number. For example, the binary equivalent of the number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b. d Decimal number. Decimal numbers are followed by this suffix only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix. h Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 59 General Business Information

Page 60

1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers. code Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR. SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the Scaling Mode (SCM) field in the Status Register (SR). REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either: • A subset of a register's named field For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that occupies bits 6–0 of the REVNO register. • A continuous range of individual signals of a bus For example, XAD[7:0] refers to signals 7–0 of the XAD bus. 1.2.3 Special terms The following terms have special meanings: Term Meaning asserted Refers to the state of a signal as follows: • An active-high signal is asserted when high (1). • An active-low signal is asserted when low (0). deasserted Refers to the state of a signal as follows: • An active-high signal is deasserted when low (0). • An active-low signal is deasserted when high (1). In some cases, deasserted signals are described as negated. reserved Refers to a memory space, register, or field that is either reserved for future use or for which, when written to, the module or chip behavior is unpredictable. Conventions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 60 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 61

Chapter 2 Introduction 2.1 Overview This chapter provides high-level descriptions of the modules available on the devices covered by this document. 2.2 Module Functional Categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Table 2-1. Module functional categories Module category Description ARM Cortex-M4 core • 32-bit MCU core from ARM’s Cortex-M class adding DSP instructions, 1.25 DMIPS/MHz, based on ARMv7 architecture System • System integration module • Power management and mode controllers • Multiple power modes available based on run, wait, stop, and power- down modes • Low-leakage wakeup unit • Miscellaneous control module • Crossbar switch • Memory protection unit • Peripheral bridge • Direct memory access (DMA) controller with multiplexer to increase available DMA requests • External watchdog monitor • Watchdog Table continues on the next page... K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 61 General Business Information

Page 62

Table 2-1. Module functional categories (continued) Module category Description Memories • Internal memories include: • Program flash memory • On devices with FlexMemory: FlexMemory • FlexNVM • FlexRAM • On devices with program flash only: Programming acceleration RAM • SRAM • External memory or peripheral bus interface: FlexBus • Serial programming interface: EzPort Clocks • Multiple clock generation options available from internally- and externally- generated clocks • System oscillator to provide clock source for the MCU • RTC oscillator to provide clock source for the RTC Security • Cyclic Redundancy Check module for error detection • Hardware encryption, along with a random number generator Analog • High speed analog-to-digital converter with integrated programmable gain amplifier • Comparator • Digital-to-analog converter • Internal voltage reference Timers • Programmable delay block • FlexTimers • Periodic interrupt timer • Low power timer • Carrier modulator transmitter • Independent real time clock Communications • Ethernet MAC with IEEE 1588 capability • USB OTG controller with built-in FS/LS transceiver • USB device charger detect • USB voltage regulator • CAN • Serial peripheral interface • Inter-integrated circuit (I2C) • UART • Secured Digital host controller • Integrated interchip sound (I2S) Human-Machine Interfaces (HMI) • General purpose input/output controller • Capacitive touch sense input interface enabled in hardware 2.2.1 ARM Cortex-M4 Core Modules The following core modules are available on this device. Module Functional Categories K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 62 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 63

Table 2-2. Core modules Module Description ARM Cortex-M4 The ARM Cortex-M4 is the newest member of the Cortex M Series of processors targeting microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M4 processor is based on the ARMv7 Architecture and Thumb®-2 ISA and is upward compatible with the Cortex M3, Cortex M1, and Cortex M0 architectures. Cortex M4 improvements include an ARMv7 Thumb-2 DSP (ported from the ARMv7-A/R profile architectures) providing 32-bit instructions with SIMD (single instruction multiple data) DSP style multiply- accumulates and saturating arithmetic. NVIC The ARMv7-M exception model and nested-vectored interrupt controller (NVIC) implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels. The NVIC replaces shadow registers with equivalent system and simplified programmability. The NVIC contains the address of the function to execute for a particular handler. The address is fetched via the instruction port allowing parallel register stacking and look-up. The first sixteen entries are allocated to ARM internal sources with the others mapping to MCU-defined interrupts. AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is to detect asynchronous wake-up events in stop modes and signal to clock control logic to resume system clocking. After clock restart, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. Debug interfaces Most of this device's debug is based on the ARM CoreSight™ architecture. Four debug interfaces are supported: • IEEE 1149.1 JTAG • IEEE 1149.7 JTAG (cJTAG) • Serial Wire Debug (SWD) • ARM Real-Time Trace Interface 2.2.2 System Modules The following system modules are available on this device. Table 2-3. System modules Module Description System integration module (SIM) The SIM includes integration logic and several module configuration settings. System mode controller The SMC provides control and protection on entry and exit to each power mode, control for the Power management controller (PMC), and reset entry and exit for the complete MCU. Power management controller (PMC) The PMC provides the user with multiple power options. Ten different modes are supported that allow the user to optimize power consumption for the level of functionality needed. Includes power-on-reset (POR) and integrated low voltage detect (LVD) with reset (brownout) capability and selectable LVD trip points. Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS and VLLS) through various internal peripheral and external pin sources. Miscellaneous control module (MCM) The MCM includes integration logic and embedded trace buffer details. Table continues on the next page... Chapter 2 Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 63 General Business Information

Page 64

Table 2-3. System modules (continued) Module Description Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave. Memory protection unit (MPU) The MPU provides memory protection and task isolation. It concurrently monitors all bus master transactions for the slave connections. Peripheral bridges The peripheral bridge converts the crossbar switch interface to an interface to access a majority of peripherals on the device. DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to a smaller number for the DMA controller. Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control descriptors for data movement via dual-address transfers for 8-, 16-, 32- and 128- bit data values. External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module that monitors both internal and external system operation for fail conditions. Software watchdog (WDOG) The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 KHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency. 2.2.3 Memories and Memory Interfaces The following memories and memory interfaces are available on this device. Table 2-4. Memories and memory interfaces Module Description Flash memory • Program flash memory — non-volatile flash memory that can execute program code • FlexMemory — encompasses the following memory types: • For devices with FlexNVM: FlexNVM — Non-volatile flash memory that can execute program code, store data, or backup EEPROM data • For devices with FlexNVM: FlexRAM — RAM memory that can be used as traditional RAM or as high-endurance EEPROM storage, and also accelerates flash programming • For devices with only program flash memory: Programming acceleration RAM — RAM memory that accelerates flash programming Flash memory controller Manages the interface between the device and the on-chip flash memory. SRAM Internal system RAM. Partial SRAM kept powered in VLLS2 low leakage mode. SRAM controller Manages simultaneous accesses to system RAM by multiple master peripherals and core. System register file 32-byte register file that is accessible during all power modes and is powered by VDD. VBAT register file 32-byte register file that is accessible during all power modes and is powered by VBAT. Table continues on the next page... Module Functional Categories K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 64 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 65

Table 2-4. Memories and memory interfaces (continued) Module Description Serial programming interface (EzPort) Same serial interface as, and subset of, the command set used by industry- standard SPI flash memories. Provides the ability to read, erase, and program flash memory and reset command to boot the system after flash programming. FlexBus External bus interface with multiple independent, user-programmable chip-select signals that can interface with external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals via 8-, 16- and 32-bit port sizes. Configurations include multiplexed or non-multiplexed address and data buses using 8-bit, 16-bit, 32-bit, and 16-byte line-sized transfers. 2.2.4 Clocks The following clock modules are available on this device. Table 2-5. Clock modules Module Description Multi-clock generator (MCG) The MCG provides several clock sources for the MCU that include: • Phase-locked loop (PLL) — Voltage-controlled oscillator (VCO) • Frequency-locked loop (FLL) — Digitally-controlled oscillator (DCO) • Internal reference clocks — Can be used as a clock source for other on-chip peripherals System oscillator The system oscillator, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. Real-time clock oscillator The RTC oscillator has an independent power supply and supports a 32 kHz crystal oscillator to feed the RTC clock. Optionally, the RTC oscillator can replace the system oscillator as the main oscillator source. 2.2.5 Security and Integrity modules The following security and integrity modules are available on this device: Table 2-6. Security and integrity modules Module Description Cryptographic acceleration unit (CAU) Supports DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms via simple C calls to optimized security functions provided by Freescale. Random number generator (RNG) Supports the key generation algorithm defined in the Digital Signature Standard. Cyclic Redundancy Check (CRC) Hardware CRC generator circuit using 16/32-bit shift register. Error detection for all single, double, odd, and most multi-bit errors, programmable initial seed value, and optional feature to transpose input data and CRC result via transpose register. Chapter 2 Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 65 General Business Information

Page 66

2.2.6 Analog modules The following analog modules are available on this device: Table 2-7. Analog modules Module Description 16-bit analog-to-digital converters (ADC) and programmable-gain amplifiers (PGA) 16-bit successive-approximation ADC designed with integrated programmable gain amplifiers (PGA) Analog comparators Compares two analog input voltages across the full range of the supply voltage. 6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed. 12-bit digital-to-analog converters (DAC) Low-power general-purpose DAC, whose output can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. Voltage reference (VREF) Supplies an accurate voltage output that is trimmable in 0.5 mV steps. The VREF can be used in medical applications, such as glucose meters, to provide a reference voltage to biosensors or as a reference to analog peripherals, such as the ADC, DAC, or CMP. 2.2.7 Timer modules The following timer modules are available on this device: Table 2-8. Timer modules Module Description Programmable delay block (PDB) • 16-bit resolution • 3-bit prescaler • Positive transition of trigger event signal initiates the counter • Supports two triggered delay output signals, each with an independently- controlled delay from the trigger event • Outputs can be OR'd together to schedule two conversions from one input trigger event and can schedule precise edge placement for a pulsed output. This feature is used to generate the control signal for the CMP windowing feature and output to a package pin if needed for applications, such as critical conductive mode power factor correction. • Continuous-pulse output or single-shot mode supported, each output is independently enabled, with possible trigger events • Supports bypass mode • Supports DMA Table continues on the next page... Module Functional Categories K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 66 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 67

Table 2-8. Timer modules (continued) Module Description Flexible timer modules (FTM) • Selectable FTM source clock, programmable prescaler • 16-bit counter supporting free-running or initial/final value, and counting is up or up-down • Input capture, output compare, and edge-aligned and center-aligned PWM modes • Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channels with independent outputs • Deadtime insertion is available for each complementary pair • Generation of hardware triggers • Software control of PWM outputs • Up to 4 fault inputs for global fault control • Configurable channel polarity • Programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition • Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position count on external event • DMA support for FTM events Periodic interrupt timers (PIT) • Four general purpose interrupt timers • Interrupt timers for triggering ADC conversions • 32-bit counter resolution • DMA support Low-power timer (LPTimer) • Selectable clock for prescaler/glitch filter of 1 kHz (internal LPO), 32.768 kHz (external crystal), or internal reference clock • Configurable Glitch Filter or Prescaler with 16-bit counter • 16-bit time or pulse counter with compare • Interrupt generated on Timer Compare • Hardware trigger generated on Timer Compare Carrier modulator timer (CMT) • Four CMT modes of operation: • Time with independent control of high and low times • Baseband • Frequency shift key (FSK) • Direct software control of CMT_IRO pin • Extended space operation in time, baseband, and FSK modes • Selectable input clock divider • Interrupt on end of cycle with the ability to disable CMT_IRO pin and use as timer interrupt • DMA support Real-time clock (RTC) • Independent power supply, POR, and 32 kHz Crystal Oscillator • 32-bit seconds counter with 32-bit Alarm • 16-bit Prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm IEEE 1588 timers • The 10/100 Ethernet module contains timers to provide IEEE 1588 time stamping 2.2.8 Communication interfaces The following communication interfaces are available on this device: Chapter 2 Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 67 General Business Information

Page 68

Table 2-9. Communication modules Module Description Ethernet MAC with IEEE 1588 capability (ENET) 10/100 MB/s Ethernet MAC (MII and RMII) with hardware support for IEEE 1588 USB OTG (low-/full-speed) USB 2.0 compliant module with support for host, device, and On-The-Go modes. Includes an on-chip transceiver for full and low speeds. USB Device Charger Detect (USBDCD) The USBDCD monitors the USB data lines to detect a smart charger meeting the USB Battery Charging Specification Rev1.1. This information allows the MCU to better manage the battery charging IC in a portable device. USB voltage regulator Up to 5 V regulator input typically provided by USB VBUS power with 3.3 V regulated output that powers on-chip USB subsystem, capable of sourcing 120 mA to external board components. Controller Area Network (CAN) Supports the full implementation of the CAN Specification Version 2.0, Part B Serial peripheral interface (SPI) Synchronous serial bus for communication to an external device Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System Management Bus (SMBus) Specification, version 2. Universal asynchronous receiver/ transmitters (UART) Asynchronous serial bus communication interface with programmable 8- or 9-bit data format and support of CEA709.1-B (LON), ISO 7816 smart card interface Secure Digital host controller (SDHC) Interface between the host system and the SD, SDIO, MMC, or CE-ATA cards. The SDHC acts as a bridge, passing host bus transactions to the cards by sending commands and performing data accesses to/from the cards. It handles the SD, SDIO, MMC, and CE-ATA protocols at the transmission level. I2S The I2S is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices, such as standard codecs, digital signal processors (DSPs), microprocessors, peripherals, and audio codecs that implement the inter- IC sound bus (I2S) and the Intel® AC97 standards 2.2.9 Human-machine interfaces The following human-machine interfaces (HMI) are available on this device: Table 2-10. HMI modules Module Description General purpose input/output (GPIO) All general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. All GPIO pins have 5 V tolerance. Capacitive touch sense input (TSI) Contains up to 16 channel inputs for capacitive touch sensing applications. Operation is available in low-power modes via interrupts. 2.3 Orderable part numbers The following table summarizes the part numbers of the devices covered by this document. Orderable part numbers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 68 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 69

Table 2-11. Orderable part numbers summary Freescale part number CPU frequenc y Pin count Package Total flash memory Program flash EEPROM SRAM GPIO MK60DN256VLQ10 100 MHz 144 LQFP 256 KB 256 KB — 64 KB 100 MK60DX256VLQ10 100 MHz 144 LQFP 512 KB 256 KB 4 KB 64 KB 100 MK60DN512VLQ10 100 MHz 144 LQFP 512 KB 512 KB — 128 KB 100 MK60DN256VMD10 100 MHz 144 MAPBGA 256 KB 256 KB — 64 KB 100 MK60DX256VMD10 100 MHz 144 MAPBGA 512 KB 256 KB 4 KB 64 KB 100 MK60DN512VMD10 100 MHz 144 MAPBGA 512 KB 512 KB — 128 KB 100 Chapter 2 Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 69 General Business Information

Page 70

Orderable part numbers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 70 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 71

Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: • module block diagrams showing immediate connections within the device, • specific module-to-module interactions not necessarily discussed in the individual module chapters, and • links for more information. 3.2 Core modules 3.2.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at http:// www.arm.com. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 71 General Business Information

Page 72

PPB Modules PPB ARM Cortex-M4 Core Debug Interrupts Crossbar switch SRAM Upper SRAM Lower Figure 3-1. Core configuration Table 3-1. Reference links to related information Topic Related module Reference Full description ARM Cortex-M4 core, r0p1 http://www.arm.com System memory map System memory map Clocking Clock distribution Power management Power management System/instruction/data bus module Crossbar switch Crossbar switch System/instruction/data bus module SRAM SRAM Debug IEEE 1149.1 JTAG Serial Wire Debug (SWD) ARM Real-Time Trace Interface Debug Interrupts Nested Vectored Interrupt Controller (NVIC) NVIC Private Peripheral Bus (PPB) module Miscellaneous Control Module (MCM) MCM Private Peripheral Bus (PPB) module Memory-Mapped Cryptographic Acceleration Unit (MMCAU) MMCAU 3.2.1.1 Buses, interconnects, and interfaces The ARM Cortex-M4 core has four buses as described in the following table. Core modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 72 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 73

Bus name Description Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is connected to the crossbar switch via a single master port. In addition, the CODE bus is also tightly coupled to the lower half of the system RAM (SRAM_L). Data code (DCODE) bus System bus The system bus is connected to a separate master port on the crossbar. In addition, the system bus is tightly coupled to the upper half system RAM (SRAM_U). Private peripheral (PPB) bus The PPB provides access to these modules: • ARM modules such as the NVIC, ETM, ITM, DWT, FBP, and ROM table • Freescale Miscellaneous Control Module (MCM) • Memory-Mapped Cryptographic Acceleration Unit (MMCAU) 3.2.1.2 System Tick Timer The System Tick Timer's clock source is always the core clock, FCLK. This results in the following: • The CLKSOURCE bit in SysTick Control and Status register is always set to select the core clock. • Because the timing reference (FCLK) is a variable frequency, the TENMS bit in the SysTick Calibration Value Register is always zero. • The NOREF bit in SysTick Calibration Value Register is always set, implying that FCLK is the only available source of reference timing. 3.2.1.3 Debug facilities This device has extensive debug capabilities including run control and tracing capabilities. The standard ARM debug port that supports JTAG and SWD interfaces. Also the cJTAG interface is supported on this device. 3.2.1.4 Core privilege levels The ARM documentation uses different terms than this document to distinguish between privilege levels. If you see this term... it also means this term... Privileged Supervisor Unprivileged or user User Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 73 General Business Information

Page 74

3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at http:// www.arm.com. Nested Vectored Interrupt Controller (NVIC) ARM Cortex-M4 core Interrupts Module Module Module PPB Figure 3-2. NVIC configuration Table 3-2. Reference links to related information Topic Related module Reference Full description Nested Vectored Interrupt Controller (NVIC) http://www.arm.com System memory map System memory map Clocking Clock distribution Power management Power management Private Peripheral Bus (PPB) ARM Cortex-M4 core ARM Cortex-M4 core 3.2.2.1 Interrupt priority levels This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source in the IPR registers contains 4 bits. For example, IPR0 is shown below: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R IRQ3 0 0 0 0 IRQ2 0 0 0 0 IRQ1 0 0 0 0 IRQ0 0 0 0 0 W 3.2.2.2 Non-maskable interrupt The non-maskable interrupt request to the NVIC is controlled by the external NMI signal. The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request. Core modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 74 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 75

3.2.2.3 Interrupt channel assignments The interrupt source assignments are defined in the following table. • Vector number — the value stored on the stack when an interrupt is serviced. • IRQ number — non-core interrupt source count, which is the vector number minus 16. The IRQ number is used within ARM's NVIC documentation. Table 3-4. Interrupt vector assignments Address Vector IRQ1 NVIC non-IPR register number 2 NVIC IPR register number 3 Source module Source description ARM Core System Handler Vectors 0x0000_0000 0 – – – ARM core Initial Stack Pointer 0x0000_0004 1 – – – ARM core Initial Program Counter 0x0000_0008 2 – – – ARM core Non-maskable Interrupt (NMI) 0x0000_000C 3 – – – ARM core Hard Fault 0x0000_0010 4 – – – ARM core MemManage Fault 0x0000_0014 5 – – – ARM core Bus Fault 0x0000_0018 6 – – – ARM core Usage Fault 0x0000_001C 7 – – – — — 0x0000_0020 8 – – – — — 0x0000_0024 9 – – – — — 0x0000_0028 10 – – – — — 0x0000_002C 11 – – – ARM core Supervisor call (SVCall) 0x0000_0030 12 – – – ARM core Debug Monitor 0x0000_0034 13 – – – — — 0x0000_0038 14 – – – ARM core Pendable request for system service (PendableSrvReq) 0x0000_003C 15 – – – ARM core System tick timer (SysTick) Non-Core Vectors 0x0000_0040 16 0 0 0 DMA DMA channel 0 transfer complete 0x0000_0044 17 1 0 0 DMA DMA channel 1 transfer complete 0x0000_0048 18 2 0 0 DMA DMA channel 2 transfer complete 0x0000_004C 19 3 0 0 DMA DMA channel 3 transfer complete 0x0000_0050 20 4 0 1 DMA DMA channel 4 transfer complete 0x0000_0054 21 5 0 1 DMA DMA channel 5 transfer complete 0x0000_0058 22 6 0 1 DMA DMA channel 6 transfer complete 0x0000_005C 23 7 0 1 DMA DMA channel 7 transfer complete 0x0000_0060 24 8 0 2 DMA DMA channel 8 transfer complete Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 75 General Business Information

Page 76

Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC non-IPR register number 2 NVIC IPR register number 3 Source module Source description 0x0000_0064 25 9 0 2 DMA DMA channel 9 transfer complete . 0x0000_0068 26 10 0 2 DMA DMA channel 10 transfer complete 0x0000_006C 27 11 0 2 DMA DMA channel 11 transfer complete 0x0000_0070 28 12 0 3 DMA DMA channel 12 transfer complete 0x0000_0074 29 13 0 3 DMA DMA channel 13 transfer complete 0x0000_0078 30 14 0 3 DMA DMA channel 14 transfer complete 0x0000_007C 31 15 0 3 DMA DMA channel 15 transfer complete 0x0000_0080 32 16 0 4 DMA DMA error interrupt channels 0-15 0x0000_0084 33 17 0 4 MCM Normal interrupt 0x0000_0088 34 18 0 4 Flash memory Command complete 0x0000_008C 35 19 0 4 Flash memory Read collision 0x0000_0090 36 20 0 5 Mode Controller Low-voltage detect, low-voltage warning 0x0000_0094 37 21 0 5 LLWU Low Leakage Wakeup NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. 0x0000_0098 38 22 0 5 WDOG or EWM Both watchdog modules share this interrupt. 0x0000_009C 39 23 0 5 RNG Randon Number Generator 0x0000_00A0 40 24 0 6 I2C0 — 0x0000_00A4 41 25 0 6 I2C1 — 0x0000_00A8 42 26 0 6 SPI0 Single interrupt vector for all sources 0x0000_00AC 43 27 0 6 SPI1 Single interrupt vector for all sources 0x0000_00B0 44 28 0 7 SPI2 Single interrupt vector for all sources 0x0000_00B4 45 29 0 7 CAN0 OR'ed Message buffer (0-15) 0x0000_00B8 46 30 0 7 CAN0 Bus Off 0x0000_00BC 47 31 0 7 CAN0 Error 0x0000_00C0 48 32 1 8 CAN0 Transmit Warning 0x0000_00C4 49 33 1 8 CAN0 Receive Warning 0x0000_00C8 50 34 1 8 CAN0 Wake Up 0x0000_00CC 51 35 1 8 I2S0 Transmit 0x0000_00D0 52 36 1 9 I2S0 Receive 0x0000_00D4 53 37 1 9 CAN1 OR'ed Message buffer (0-15) 0x0000_00D8 54 38 1 9 CAN1 Bus off Table continues on the next page... Core modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 76 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 77

Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC non-IPR register number 2 NVIC IPR register number 3 Source module Source description 0x0000_00DC 55 39 1 9 CAN1 Error 0x0000_00E0 56 40 1 10 CAN1 Transmit Warning 0x0000_00E4 57 41 1 10 CAN1 Receive Warning 0x0000_00E8 58 42 1 10 CAN1 Wake Up 0x0000_00EC 59 43 1 10 — — 0x0000_00F0 60 44 1 11 UART0 Single interrupt vector for UART LON sources 0x0000_00F4 61 45 1 11 UART0 Single interrupt vector for UART status sources 0x0000_00F8 62 46 1 11 UART0 Single interrupt vector for UART error sources 0x0000_00FC 63 47 1 11 UART1 Single interrupt vector for UART status sources 0x0000_0100 64 48 1 12 UART1 Single interrupt vector for UART error sources 0x0000_0104 65 49 1 12 UART2 Single interrupt vector for UART status sources 0x0000_0108 66 50 1 12 UART2 Single interrupt vector for UART error sources 0x0000_010C 67 51 1 12 UART3 Single interrupt vector for UART status sources 0x0000_0110 68 52 1 13 UART3 Single interrupt vector for UART error sources 0x0000_0114 69 53 1 13 UART4 Single interrupt vector for UART status sources 0x0000_0118 70 54 1 13 UART4 Single interrupt vector for UART error sources 0x0000_011C 71 55 1 13 UART5 Single interrupt vector for UART status sources 0x0000_0120 72 56 1 14 UART5 Single interrupt vector for UART error sources 0x0000_0124 73 57 1 14 ADC0 — 0x0000_0128 74 58 1 14 ADC1 — 0x0000_012C 75 59 1 14 CMP0 — 0x0000_0130 76 60 1 15 CMP1 — 0x0000_0134 77 61 1 15 CMP2 — 0x0000_0138 78 62 1 15 FTM0 Single interrupt vector for all sources 0x0000_013C 79 63 1 15 FTM1 Single interrupt vector for all sources 0x0000_0140 80 64 2 16 FTM2 Single interrupt vector for all sources 0x0000_0144 81 65 2 16 CMT — Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 77 General Business Information

Page 78

Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC non-IPR register number 2 NVIC IPR register number 3 Source module Source description 0x0000_0148 82 66 2 16 RTC Alarm interrupt 0x0000_014C 83 67 2 16 RTC Seconds interrupt 0x0000_0150 84 68 2 17 PIT Channel 0 0x0000_0154 85 69 2 17 PIT Channel 1 0x0000_0158 86 70 2 17 PIT Channel 2 0x0000_015C 87 71 2 17 PIT Channel 3 0x0000_0160 88 72 2 18 PDB — 0x0000_0164 89 73 2 18 USB OTG — 0x0000_0168 90 74 2 18 USB Charger Detect — 0x0000_016C 91 75 2 18 Ethernet MAC IEEE 1588 Timer Interrupt 0x0000_0170 92 76 2 19 Ethernet MAC Transmit interrupt 0x0000_0174 93 77 2 19 Ethernet MAC Receive interrupt 0x0000_0178 94 78 2 19 Ethernet MAC Error and miscellaneous interrupt 0x0000_017C 95 79 2 19 — — 0x0000_0180 96 80 2 20 SDHC — 0x0000_0184 97 81 2 20 DAC0 — 0x0000_0188 98 82 2 20 DAC1 — 0x0000_018C 99 83 2 20 TSI Single interrupt vector for all sources 0x0000_0190 100 84 2 21 MCG — 0x0000_0194 101 85 2 21 Low Power Timer — 0x0000_0198 102 86 2 21 — — 0x0000_019C 103 87 2 21 Port control module Pin detect (Port A) 0x0000_01A0 104 88 2 22 Port control module Pin detect (Port B) 0x0000_01A4 105 89 2 22 Port control module Pin detect (Port C) 0x0000_01A8 106 90 2 22 Port control module Pin detect (Port D) 0x0000_01AC 107 91 2 22 Port control module Pin detect (Port E) 0x0000_01B0 108 92 2 23 — — 0x0000_01B4 109 93 2 23 — — 0x0000_01B8 110 94 2 23 Software Software interrupt4 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 4. This interrupt can only be pended or cleared via the NVIC registers. Core modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 78 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 79

3.2.2.3.1 Determining the bitfield and register location for configuring a particular interrupt Suppose you need to configure the low-power timer (LPTMR) interrupt. The following table is an excerpt of the LPTMR row from Interrupt channel assignments. Table 3-5. LPTMR interrupt vector assignment Address Vector IRQ1 NVIC non-IPR register number 2 NVIC IPR register number 3 Source module Source description 0x0000_0194 101 85 2 21 Low Power Timer — 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 • The NVIC registers you would use to configure the interrupt are: • NVICISER2 • NVICICER2 • NVICISPR2 • NVICICPR2 • NVICIABR2 • NVICIPR21 • To determine the particular IRQ's bitfield location within these particular registers: • NVICISER2, NVICICER2, NVICISPR2, NVICICPR2, NVICIABR2 bit location = IRQ mod 32 = 21 • NVICIPR21 bitfield starting location = 8 * (IRQ mod 4) + 4 = 12 Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR21 bitfield range is 12-15 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: • NVICISER2[21] • NVICICER2[21] • NVICISPR2[21] • NVICICPR2[21] • NVICIABR2[21] • NVICIPR21[15:12] Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 79 General Business Information

Page 80

3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at http:// www.arm.com. Asynchronous Wake-up Interrupt Controller (AWIC) Nested vectored interrupt controller (NVIC) Wake-up requests Module Module Clock logic Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration Table 3-6. Reference links to related information Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management Nested Vectored Interrupt Controller (NVIC) NVIC Wake-up requests AWIC wake-up sources 3.2.3.1 Wake-up sources The device uses the following internal and external inputs to the AWIC module. Table 3-7. AWIC Stop and VLPS Wake-up Sources Wake-up source Description Available system resets RESET pin and WDOG when LPO is its clock source, and JTAG Low-voltage detect Mode Controller Low-voltage warning Mode Controller Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system ADCx The ADC is functional when using internal clock source CMPx Since no system clocks are available, functionality is limited I2C Address match wakeup Table continues on the next page... Core modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 80 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 81

Table 3-7. AWIC Stop and VLPS Wake-up Sources (continued) Wake-up source Description UART Active edge on RXD USB Wakeup LPTMR Functional in Stop/VLPS modes RTC Functional in Stop/VLPS modes Ethernet Magic Packet wakeup SDHC Wakeup I2S Functional when using an external bit clock or external master clock 1588 Timer Wakeup TSI CAN NMI Non-maskable interrupt 3.2.4 JTAG Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing JTAG controller cJTAG Figure 3-4. JTAGC Controller configuration Table 3-8. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control Signal multiplexing 3.3 System modules Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 81 General Business Information

Page 82

3.3.1 SIM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Register access Peripheral bridge System integration module (SIM) Figure 3-5. SIM configuration Table 3-9. Reference links to related information Topic Related module Reference Full description SIM SIM System memory map System memory map Clocking Clock distribution Power management Power management 3.3.2 System Mode Controller (SMC) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. System modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 82 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 83

Power Management Controller (PMC) Register access Peripheral bridge System Mode Controller (SMC) Resets Figure 3-6. System Mode Controller configuration Table 3-10. Reference links to related information Topic Related module Reference Full description System Mode Controller (SMC) SMC System memory map System memory map Power management Power management Power management controller (PMC) PMC Low-Leakage Wakeup Unit (LLWU) LLWU Reset Control Module (RCM) Reset 3.3.3 PMC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 83 General Business Information

Page 84

Register access Power Management Controller (PMC) Module signals Peripheral bridge Module signals System Mode Controller (SMC) Low-Leakage Wakeup Unit Figure 3-7. PMC configuration Table 3-11. Reference links to related information Topic Related module Reference Full description PMC PMC System memory map System memory map Power management Power management Full description System Mode Controller (SMC) System Mode Controller Low-Leakage Wakeup Unit (LLWU) LLWU Reset Control Module (RCM) Reset 3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. System modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 84 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 85

Low-Leakage Wake-up Unit (LLWU) Power Management Controller (PMC) Peripheral bridge 0 Register access Wake-up requests Module Module Figure 3-8. Low-Leakage Wake-up Unit configuration Table 3-12. Reference links to related information Topic Related module Reference Full description LLWU LLWU System memory map System memory map Clocking Clock distribution Power management Power management chapter Power Management Controller (PMC) Power Management Controller (PMC) Mode Controller Mode Controller Wake-up requests LLWU wake-up sources 3.3.4.1 Wake-up Sources This chip uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module: • LLWU_P0-15 are external pin inputs. Any digital function multiplexed on the pin can be selected as the wakeup source. See the chip's signal multiplexing table for the digital signal options. • LLWU_M0IF-M7IF are connections to the internal peripheral interrupt flags. NOTE RESET is also a wakeup source, depending on the bit setting in the LLWU_RST register. On devices where RESET is not a dedicated pin, it must also be enabled in the explicit port mux control. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 85 General Business Information

Page 86

Table 3-13. Wakeup sources for LLWU inputs Input Wakeup source Input Wakeup source LLWU_P0 PTE1/LLWU_P0 pin LLWU_P12 PTD0/LLWU_P12 pin LLWU_P1 PTE2/LLWU_P1 pin LLWU_P13 PTD2/LLWU_P13 pin LLWU_P2 PTE4/LLWU_P2 pin LLWU_P14 PTD4/LLWU_P14 pin LLWU_P3 PTA4/LLWU_P3 pin1 LLWU_P15 PTD6/LLWU_P15 pin LLWU_P4 PTA13/LLWU_P4 pin LLWU_M0IF LPTMR2 LLWU_P5 PTB0/LLWU_P5 pin LLWU_M1IF CMP02 LLWU_P6 PTC1/LLWU_P6 pin LLWU_M2IF CMP12 LLWU_P7 PTC3/LLWU_P7 pin LLWU_M3IF CMP22 LLWU_P8 PTC4/LLWU_P8 pin LLWU_M4IF TSI2 LLWU_P9 PTC5/LLWU_P9 pin LLWU_M5IF RTC Alarm2 LLWU_P10 PTC6/LLWU_P10 pin LLWU_M6IF Reserved LLWU_P11 PTC11/LLWU_P11 pin LLWU_M7IF RTC Seconds2 1. The EZP_CS signal is checked only on Chip Reset not VLLS, so a VLLS wakeup via a non-reset source does not cause EzPort mode entry. If NMI was enabled on entry to LLS/VLLS, asserting the NMI pin generates an NMI interrupt on exit from the low power mode. NMI can also be disabled via the FOPT[NMI_DIS] bit. 2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism. 3.3.5 MCM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Miscellaneous Control Module (MCM) Transfers ARM Cortex-M4 core PPB Figure 3-9. MCM configuration Table 3-14. Reference links to related information Topic Related module Reference Full description Miscellaneous control module (MCM) MCM System memory map System memory map Clocking Clock distribution Power management Power management Transfers Private Peripheral Bus (PPB) ARM Cortex-M4 core ARM Cortex-M4 core System modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 86 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 87

3.3.6 Crossbar Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Crossbar Switch Slave Modules SDHC Master Modules M2 M5 M0 M1 S0 S3 ARM core code bus ARM core system bus DMA EzPort Mux Flash controller S1 SRAM backdoor S2 Peripheral bridge 0 Memory protection unit (MPU) Mux Peripheral bridge 1 GPIO controller S4 FlexBus MPU USB M4 Ethernet M3 Figure 3-10. Crossbar switch configuration Table 3-15. Reference links to related information Topic Related module Reference Full description Crossbar switch Crossbar Switch System memory map System memory map Clocking Clock Distribution Memory protection MPU MPU Crossbar switch master ARM Cortex-M4 core ARM Cortex-M4 core Crossbar switch master DMA controller DMA controller Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 87 General Business Information

Page 88

Table 3-15. Reference links to related information (continued) Topic Related module Reference Crossbar switch master EzPort EzPort Crossbar switch master Ethernet Ethernet Crossbar switch master USB FS/LS USB FS/LS Crossbar switch master SDHC SDHC Crossbar switch slave Flash Flash Crossbar switch slave SRAM backdoor SRAM backdoor Crossbar switch slave Peripheral bridges Peripheral bridge Crossbar switch slave GPIO controller GPIO controller Crossbar switch slave FlexBus FlexBus 3.3.6.1 Crossbar Switch Master Assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core code bus 0 ARM core system bus 1 DMA/EzPort 2 Ethernet 3 USB OTG 4 SDHC 5 NOTE The DMA and EzPort share a master port. Since these modules never operate at the same time, no configuration or arbitration explanations are necessary. 3.3.6.2 Crossbar Switch Slave Assignments The slaves connected to the crossbar switch are assigned as follows: Slave module Slave port number Protected by MPU? Flash memory controller 0 Yes SRAM backdoor 1 Yes Peripheral bridge 01 2 No. Protection built into bridge. Peripheral bridge 1/GPIO1 3 No. Protection built into bridge. FlexBus 4 Yes System modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 88 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 89

See System memory map for access restrictions. 3.3.6.3 PRS register reset values The AXBS_PRSn registers reset to 0054_3210h. 3.3.7 Memory Protection Unit (MPU) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Memory Protection Unit (MPU) Transfers Slave Slave Slave Peripheral bridge 0 Register access Transfers Logical Master Logical Master Logical Master Figure 3-11. Memory Protection Unit configuration Table 3-16. Reference links to related information Topic Related module Reference Full description Memory Protection Unit (MPU) MPU System memory map System memory map Clocking Clock distribution Power management Power management Logical masters Logical master assignments Slave modules Slave module assignments Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 89 General Business Information

Page 90

3.3.7.1 MPU Slave Port Assignments The memory-mapped resources protected by the MPU are: Table 3-17. MPU Slave Port Assignments Source MPU Slave Port Assignment Destination Crossbar slave port 0 MPU slave port 0 Flash Controller Crossbar slave port 1 MPU slave port 1 SRAM backdoor Code Bus MPU slave port 2 SRAM_L frontdoor System Bus MPU slave port 3 SRAM_U frontdoor Crossbar slave port 4 MPU slave port 4 FlexBus 3.3.7.2 MPU Logical Bus Master Assignments The logical bus master assignments for the MPU are: Table 3-18. MPU Logical Bus Master Assignments MPU Logical Bus Master Number Bus Master 0 Core 1 Debugger 2 DMA 3 ENET 4 USB 5 SDHC 6 none 7 none 3.3.7.3 MPU Access Violation Indications Access violations detected by the MPU are signaled to the appropriate bus master as shown below: Table 3-19. Access Violation Indications Bus Master Core Indication Core Bus fault (interrupt vector #5) Note: To enable bus faults set the core's System Handler Control and State Register's BUSFAULTENA bit. If this bit is not set, MPU violations result in a hard fault (interrupt vector #3). Debugger The STICKYERROR flag is set in the Debug Port Control/Status Register. DMA Interrupt vector #32 Ethernet Interrupt vector #94 Table continues on the next page... System modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 90 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 91

Table 3-19. Access Violation Indications (continued) Bus Master Core Indication USB_OTG Interrupt vector #89 SDHC Interrupt vector #96 3.3.7.4 Reset Values for RGD0 Registers At reset, the MPU is enabled with a single region descriptor (RGD0) that maps the entire 4 GB address space with read, write and execute permissions given to the core, debugger and the DMA bus masters. The following table shows the chip-specific reset values for RGD0 and RGDAAC0. Table 3-20. Reset Values for RGD0 Registers Register Reset value RGD0_WORD0 0000_0000h RGD0_WORD1 FFFF_FFFFh RGD0_WORD2 0061_F7DFh RGD0_WORD3 0000_0001h RGDAAC0 0061_F7DFh 3.3.7.5 Write Access Restrictions for RGD0 Registers In addition to configuring the initial state of RGD0, the MPU implements further access control on writes to the RGD0 registers. Specifically, the MPU assigns a priority scheme where the debugger is treated as the highest priority master followed by the core and then all the remaining masters. The MPU does not allow writes from the core to affect the RGD0 start or end addresses nor the permissions associated with the debugger; it can only write the permission fields associated with the other masters. These protections (summarized below) guarantee that the debugger always has access to the entire address space and those rights cannot be changed by the core or any other bus master. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 91 General Business Information

Page 92

Table 3-21. Write Access to RGD0 Registers Bus Master Write Access? Core Partial. The Core cannot write to the following registers or register fields: • RGD0_WORD0, RGD0_WORD1, RGD0_WORD3 • RGD0_WORD2[M1SM, M1UM] • RGDAAC0[M1SM, M1UM] NOTE: Changes to the RGD0_WORD2 alterable fields should be done via a write to RGDAAC0. Debugger Yes All other masters No 3.3.8 Peripheral Bridge Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripherals Transfers AIPS-Lite peripheral bridge Transfers Crossbar switch Figure 3-12. Peripheral bridge configuration Table 3-22. Reference links to related information Topic Related module Reference Full description Peripheral bridge (AIPS-Lite) Peripheral bridge (AIPS-Lite) System memory map System memory map Clocking Clock Distribution Crossbar switch Crossbar switch Crossbar switch 3.3.8.1 Number of peripheral bridges This device contains two identical peripheral bridges. System modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 92 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 93

3.3.8.2 Memory maps The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map and AIPS1 Memory Map for the memory slot assignment for each module. 3.3.8.3 MPRA register Each of the two peripheral bridges supports up to 8 crossbar switch masters, each assigned to a MPROTx field in the MPRA register. However, fewer are supported on this device. See Crossbar switch for details of the master port assignments for this device. 3.3.8.4 AIPS_Lite MPRA register reset value • AIPSx_MPRA reset value is 0x7770_0000 Therefore, masters 0, 1, and 2 are trusted bus masters after reset. 3.3.8.5 PACR registers Each of the two peripheral bridges support up to 128 peripherals each assigned to an PACRx field within the PACRA-PACRP registers. However, fewer peripherals are supported on this device. See AIPS0 Memory MapandAIPS1 Memory Map for details of the peripheral slot assignments for this device. Unused PACRx fields are reserved. 3.3.8.6 AIPS_Lite PACRE-P register reset values The AIPSx_PACRE-P reset values depend on if the module is available on your particular device. For each populated slot in slots 32-127 in Peripheral Bridge 0 (AIPS- Lite 0) Memory Map and Peripheral Bridge 1 (AIPS-Lite 1) Memory Map, the corresponding module's PACR[32:127] field resets to 0x4. 3.3.9 DMA request multiplexer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 93 General Business Information

Page 94

DMA Request Multiplexer DMA controller Requests Module Module Module Peripheral bridge 0 Register access Channel request Figure 3-13. DMA request multiplexer configuration Table 3-23. Reference links to related information Topic Related module Reference Full description DMA request multiplexer DMA Mux System memory map System memory map Clocking Clock distribution Power management Power management Channel request DMA controller DMA Controller Requests DMA request sources 3.3.9.1 DMA MUX request sources This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 16 DMA channels. Because of the mux there is not a hard correlation between any of the DMA request sources and a specific DMA channel. Table 3-24. DMA request sources - MUX 0 Source number Source module Source description 0 — Channel disabled1 1 Reserved Not used 2 UART0 Receive 3 UART0 Transmit 4 UART1 Receive 5 UART1 Transmit 6 UART2 Receive 7 UART2 Transmit 8 UART3 Receive Table continues on the next page... System modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 94 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 95

Table 3-24. DMA request sources - MUX 0 (continued) Source number Source module Source description 9 UART3 Transmit 10 UART4 Receive 11 UART4 Transmit 12 UART5 Receive 13 UART5 Transmit 14 I2S0 Receive 15 I2S0 Transmit 16 SPI0 Receive 17 SPI0 Transmit 18 SPI1 Receive 19 SPI1 Transmit 20 SPI2 Receive 21 SPI2 Transmit 22 I2C0 — 23 I2C1 — 24 FTM0 Channel 0 25 FTM0 Channel 1 26 FTM0 Channel 2 27 FTM0 Channel 3 28 FTM0 Channel 4 29 FTM0 Channel 5 30 FTM0 Channel 6 31 FTM0 Channel 7 32 FTM1 Channel 0 33 FTM1 Channel 1 34 FTM2 Channel 0 35 FTM2 Channel 1 36 IEEE 1588 Timers Timer 0 37 IEEE 1588 Timers Timer 1 38 IEEE 1588 Timers Timer 2 39 IEEE 1588 Timers Timer 3 40 ADC0 — 41 ADC1 — 42 CMP0 — 43 CMP1 — 44 CMP2 — 45 DAC0 — 46 DAC1 — 47 CMT — Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 95 General Business Information

Page 96

Table 3-24. DMA request sources - MUX 0 (continued) Source number Source module Source description 48 PDB — 49 Port control module Port A 50 Port control module Port B 51 Port control module Port C 52 Port control module Port D 53 Port control module Port E 54 DMA MUX Always enabled 55 DMA MUX Always enabled 56 DMA MUX Always enabled 57 DMA MUX Always enabled 58 DMA MUX Always enabled 59 DMA MUX Always enabled 60 DMA MUX Always enabled 61 DMA MUX Always enabled 62 DMA MUX Always enabled 63 DMA MUX Always enabled 1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel. 3.3.9.2 DMA transfers via PIT trigger The PIT module can trigger a DMA transfer on the first four DMA channels. The assignments are detailed at PIT/DMA Periodic Trigger Assignments . 3.3.10 DMA Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. System modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 96 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 97

DMA Controller Crossbar switch Requests Peripheral bridge 0 Register access Transfers DMA Multiplexer Figure 3-14. DMA Controller configuration Table 3-25. Reference links to related information Topic Related module Reference Full description DMA Controller DMA Controller System memory map System memory map Register access Peripheral bridge (AIPS-Lite 0) AIPS-Lite 0 Clocking Clock distribution Power management Power management Transfers Crossbar switch Crossbar switch 3.3.11 External Watchdog Monitor (EWM) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 97 General Business Information

Page 98

External Watchdog Monitor (EWM) Peripheral bridge 0 Register access Signal multiplexing Module signals Figure 3-15. External Watchdog Monitor configuration Table 3-26. Reference links to related information Topic Related module Reference Full description External Watchdog Monitor (EWM) EWM System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port Control Module Signal multiplexing 3.3.11.1 EWM clocks This table shows the EWM clocks and the corresponding chip clocks. Table 3-27. EWM clock connections Module clock Chip clock Low Power Clock 1 kHz LPO Clock 3.3.11.2 EWM low-power modes This table shows the EWM low-power modes and the corresponding chip low-power modes. Table 3-28. EWM low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS, LLS Power Down VLLS3, VLLS2, VLLS1 System modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 98 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 99

3.3.11.3 EWM_OUT pin state in low power modes During Wait, Stop and Power Down modes the EWM_OUT pin enters a high-impedance state. A user has the option to control the logic state of the pin using an external pull device or by configuring the internal pull device. When the CPU enters a Run mode from Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop mode. When the CPU enters Run mode from Power Down, the pin returns to its reset state. 3.3.12 Watchdog Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. WDOG Mode Controller Peripheral bridge 0 Register access Figure 3-16. Watchdog configuration Table 3-29. Reference links to related information Topic Related module Reference Full description Watchdog Watchdog System memory map System memory map Clocking Clock distribution Power management Power management Mode Controller (MC) System Mode Controller 3.3.12.1 WDOG clocks This table shows the WDOG module clocks and the corresponding chip clocks. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 99 General Business Information

Page 100

Table 3-30. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Alt Clock Bus Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock 3.3.12.2 WDOG low-power modes This table shows the WDOG low-power modes and the corresponding chip low-power modes. Table 3-31. WDOG low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS Power Down LLS, VLLSx 3.4 Clock modules 3.4.1 MCG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Clock modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 100 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 101

Register access Peripheral bridge Multipurpose Clock Generator (MCG) RTC oscillator System oscillator System integration module (SIM) Figure 3-17. MCG configuration Table 3-32. Reference links to related information Topic Related module Reference Full description MCG MCG System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.4.2 OSC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access Peripheral bridge System oscillator MCG Module signals Figure 3-18. OSC configuration Table 3-33. Reference links to related information Topic Related module Reference Full description OSC OSC System memory map System memory map Clocking Clock distribution Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 101 General Business Information

Page 102

Table 3-33. Reference links to related information (continued) Topic Related module Reference Power management Power management Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details. 3.4.3 RTC OSC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing 32-kHz RTC oscillator MCG Module signals Figure 3-19. RTC OSC configuration Table 3-34. Reference links to related information Topic Related module Reference Full description RTC OSC RTC OSC Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3.5 Memories and memory interfaces 3.5.1 Flash Memory Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Memories and memory interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 102 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 103

Register access Flash memory Transfers Flash memory controller Peripheral bus controller 0 Figure 3-20. Flash memory configuration Table 3-35. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory System memory map System memory map Clocking Clock Distribution Transfers Flash memory controller Flash memory controller Register access Peripheral bridge Peripheral bridge 3.5.1.1 Flash memory types This device contains the following types of flash memory: • Program flash memory — non-volatile flash memory that can execute program code • FlexMemory — encompasses the following memory types: • For devices with FlexNVM: FlexNVM — Non-volatile flash memory that can execute program code, store data, or backup EEPROM data • For devices with FlexNVM: FlexRAM — RAM memory that can be used as traditional RAM or as high-endurance EEPROM storage, and also accelerates flash programming • For devices with only program flash memory: Programming acceleration RAM — RAM memory that accelerates flash programming 3.5.1.2 Flash Memory Sizes The devices covered in this document contain: • For devices with program flash only: 2 blocks of program flash consisting of 2 KB sectors Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 103 General Business Information

Page 104

• For devices that contain FlexNVM: 1 block of program flash consisting of 2 KB sectors • For devices that contain FlexNVM: 1 block of FlexNVM consisting of 2 KB sectors • For devices that contain FlexNVM: 1 block of FlexRAM The amounts of flash memory for the devices covered in this document are: Device Program flash (KB) Block 0 (P- Flash) address range1 FlexNVM (KB) Block 1 (FlexNVM/ P- Flash) address range1 FlexRAM/ Programming Acceleration RAM (KB) FlexRAM/ Programming Acceleration RAM address range MK60DN256VL Q10 256 0x0000_0000 – 0x0001_FFFF — 0x0002_0000 – 0x0003_FFFF 4 0x1400_0000 – 0x1400_0FFF MK60DX256VL Q10 256 0x0000_0000 – 0x0003_FFFF 256 0x1000_0000 – 0x1003_FFFF 4 0x1400_0000 – 0x1400_0FFF MK60DN512VL Q10 512 0x0000_0000 – 0x0003_FFFF — 0x0004_0000 – 0x0007_FFFF 4 0x1400_0000 – 0x1400_0FFF MK60DN256VM D10 256 0x0000_0000 – 0x0001_FFFF — 0x0002_0000 – 0x0003_FFFF 4 0x1400_0000 – 0x1400_0FFF MK60DX256VM D10 256 0x0000_0000 – 0x0003_FFFF 256 0x1000_0000 – 0x1003_FFFF 4 0x1400_0000 – 0x1400_0FFF MK60DN512VM D10 512 0x0000_0000 – 0x0003_FFFF — 0x0004_0000 – 0x0007_FFFF 4 0x1400_0000 – 0x1400_0FFF 1. For program flash only devices: The addresses shown assume program flash swap is disabled (default configuration). 3.5.1.3 Flash Memory Size Considerations Since this document covers devices that contain program flash only and devices that contain program flash and FlexNVM, there are some items to consider when reading the flash memory chapter. • The flash memory chapter shows a mixture of information depending on the device you are using. • For the program flash only devices: • Two program flash blocks are supported: program flash 1 and program flash 2. The two blocks are contiguous in the system memory map. • The program flash blocks support a swap feature in which the starting address of the program flash blocks can be swapped. • The programming acceleration RAM is used for the Program Section command. • For the devices containing program flash and FlexNVM: • Since there is only one program flash block, the program flash swap feature is not available. Memories and memory interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 104 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 105

3.5.1.4 Flash Memory Map The various flash memories and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. Program flash Flash configuration field Program flash base address Flash memory base address Registers RAM Programming acceleration RAM base address Figure 3-21. Flash memory map for devices containing only program flash Program flash Flash configuration field FlexNVM base address Program flash base address Flash memory base address Registers FlexNVM FlexRAM FlexRAM base address Figure 3-22. Flash memory map for devices containing FlexNVM 3.5.1.5 Flash Security How flash security is implemented on this device is described in Chip Security. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 105 General Business Information

Page 106

3.5.1.6 Flash Modes The flash memory operates in NVM normal and NVM special modes. The flash memory enters NVM special mode when the EzPort is enabled (EZP_CS asserted during reset). Otherwise, flash memory operates in NVM normal mode. 3.5.1.7 Erase All Flash Contents In addition to software, the entire flash memory may be erased external to the flash memory in two ways:

Via the EzPort by issuing a bulk erase (BE) command. See the EzPort chapter for more details.
Via the SWJ-DP debug port by setting DAP_CONTROL[0]. DAP_STATUS[0] is set to indicate the mass erase command has been accepted. DAP_STATUS[0] is cleared when the mass erase completes. 3.5.1.8 FTFL_FOPT Register The flash memory's FTFL_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition. 3.5.2 Flash Memory Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Memories and memory interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 106 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 107

Register access Flash memory controller Transfers Memory protection unit Peripheral bus controller 0 Transfers Flash memory Crossbar switch Figure 3-23. Flash memory controller configuration Table 3-36. Reference links to related information Topic Related module Reference Full description Flash memory controller Flash memory controller System memory map System memory map Clocking Clock Distribution Transfers Flash memory Flash memory Transfers MPU MPU Transfers Crossbar switch Crossbar Switch Register access Peripheral bridge Peripheral bridge 3.5.2.1 Number of masters The Flash Memory Controller supports up to eight crossbar switch masters. However, this device has a different number of crossbar switch masters. See Crossbar Switch Configuration for details on the master port assignments. 3.5.2.2 Program Flash Swap On devices that contain program flash memory only, the program flash memory blocks may swap their base addresses. While not using swap: If swap is used, the opposite is true: 3.5.3 SRAM Configuration This section summarizes how the module has been configured in the chip. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 107 General Business Information

Page 108

SRAM upper Transfers SRAM controller Cortex-M4 core MPU Crossbar switch SRAM lower MPU Figure 3-24. SRAM configuration Table 3-37. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution Transfers SRAM controller SRAM controller ARM Cortex-M4 core ARM Cortex-M4 core Memory protection unit Memory protection unit 3.5.3.1 SRAM sizes This device contains SRAM tightly coupled to the ARM Cortex-M4 core. The amount of SRAM for the devices covered in this document is shown in the following table. Device SRAM (KB) MK60DN256VLQ10 64 MK60DX256VLQ10 64 MK60DN512VLQ10 128 MK60DN256VMD10 64 MK60DX256VMD10 64 MK60DN512VMD10 128 3.5.3.2 SRAM Arrays The on-chip SRAM is split into two equally-sized logical arrays, SRAM_L and SRAM_U. The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. As such: Memories and memory interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 108 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 109

• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address. • SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address. Valid address ranges for SRAM_L and SRAM_U are then defined as: • SRAM_L = [0x2000_0000–(SRAM_size/2)] to 0x1FFF_FFFF • SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size/2)-1] This is illustrated in the following figure. SRAM_U 0x2000_0000 SRAM size / 2 SRAM_L 0x1FFF_FFFF SRAM size / 2 0x2000_0000 – SRAM_size/2 0x2000 0000 + SRAM size/2 - 1 Figure 3-25. SRAM blocks memory map For example, for a device containing 64 KB of SRAM the ranges are: • SRAM_L: 0x1FFF_8000 – 0x1FFF_FFFF • SRAM_U: 0x2000_0000 – 0x2000_7FFF 3.5.3.3 SRAM retention in low power modes The SRAM is retained down to VLLS3 mode. In VLLS2 the 4 or 16 KB (user option) region of SRAM_U from 0x2000_0000 is powered. These different regions (or partitions) of SRAM are labeled as follows: • RAM1: the 4 KB region always powered in VLLS2 • RAM2: the additional 12 KB region optionally powered in VLLS2 • RAM3: the rest of system RAM In VLLS1 no SRAM is retained; however, the 32-byte register file is available. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 109 General Business Information

Page 110

3.5.3.4 SRAM accesses The SRAM is split into two logical arrays that are 32-bits wide. • SRAM_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor port. • SRAM_U — Accessible by the system bus of the Cortex-M4 core and by the backdoor port. The backdoor port makes the SRAM accessible to the non-core bus masters (such as DMA). The following figure illustrates the SRAM accesses within the device. Cortex-M4 core Code bus System bus SRAM controller Backdoor SRAM_L SRAM_U Crossbar switch non-core master non-core master non-core master Frontdoor MPU MPU Figure 3-26. SRAM access diagram The following simultaneous accesses can be made to different logical halves of the SRAM: • Core code and core system • Core code and non-core master • Core system and non-core master NOTE Two non-core masters cannot access SRAM simultaneously. The required arbitration and serialization is provided by the crossbar switch. The SRAM_{L,U} arbitration is controlled by the SRAM controller based on the configuration bits in the MCM module. NOTE Burst-access cannot occur across the 0x2000_0000 boundary that separates the two SRAM arrays. The two arrays should be treated as separate memory ranges for burst accesses. Memories and memory interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 110 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 111

3.5.3.5 SRAM arbitration and priority control The MCM's SRAMAP register controls the arbitration and priority schemes for the two SRAM arrays. 3.5.4 SRAM Controller Configuration This section summarizes how the module has been configured in the chip. Cortex-M4 core MPU Crossbar switch SRAM controller Transfers SRAM upper SRAM lower MPU Figure 3-27. SRAM controller configuration Table 3-38. Reference links to related information Topic Related module Reference System memory map System memory map Power management Power management Power management controller (PMC) PMC Transfers SRAM SRAM ARM Cortex-M4 core ARM Cortex-M4 core MPU Memory protection unit Configuration MCM MCM 3.5.5 System Register File Configuration This section summarizes how the module has been configured in the chip. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 111 General Business Information

Page 112

Register file Peripheral bridge 0 Register access Figure 3-28. System Register file configuration Table 3-39. Reference links to related information Topic Related module Reference Full description Register file Register file System memory map System memory map Clocking Clock distribution Power management Power management 3.5.5.1 System Register file This device includes a 32-byte register file that is powered in all power modes. Also, it retains contents during low-voltage detect (LVD) events and is only reset during a power-on reset. 3.5.6 VBAT Register File Configuration This section summarizes how the module has been configured in the chip. Memories and memory interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 112 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 113

VBAT register file Peripheral bridge Register access Figure 3-29. VBAT Register file configuration Table 3-40. Reference links to related information Topic Related module Reference Full description VBAT register file VBAT register file System memory map System memory map Clocking Clock distribution Power management Power management 3.5.6.1 VBAT register file This device includes a 32-byte register file that is powered in all power modes and is powered by VBAT. It is only reset during VBAT power-on reset. 3.5.7 EzPort Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals EzPort Transfers Crossbar switch Figure 3-30. EzPort configuration Table 3-41. Reference links to related information Topic Related module Reference Full description EzPort EzPort Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 113 General Business Information

Page 114

Table 3-41. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.5.7.1 JTAG instruction The system JTAG controller implements an EZPORT instruction. When executing this instruction, the JTAG controller resets the core logic and asserts the EzPort chip select signal to force the processor into EzPort mode. 3.5.7.2 Flash Option Register (FOPT) The FOPT[EZPORT_DIS] bit can be used to prevent entry into EzPort mode during reset. If the FOPT[EZPORT_DIS] bit is cleared, then the state of the chip select signal (EZP_CS) is ignored and the MCU always boots in normal mode. This option is useful for systems that use the EZP_CS/NMI signal configured for its NMI function. Disabling EzPort mode prevents possible unwanted entry into EzPort mode if the external circuit that drives the NMI signal asserts it during reset. The FOPT register is loaded from the flash option byte. If the flash option byte is modified the new value takes effect for any subsequent resets, until the value is changed again. 3.5.8 FlexBus Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Memories and memory interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 114 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 115

Signal multiplexing Module signals Register access FlexBus Transfers Memory protection unit Peripheral bridge 0 Crossbar switch Figure 3-31. FlexBus configuration Table 3-42. Reference links to related information Topic Related module Reference Full description FlexBus FlexBus System memory map System memory map Clocking Clock distribution Power management Power management Transfers Memory protection unit (MPU) Memory protection unit (MPU) Signal multiplexing Port control Signal multiplexing 3.5.8.1 FlexBus clocking The system provides a dedicated clock source to the FlexBus module's external CLKOUT. Its clock frequency is derived from a divider of the MCGOUTCLK. See Clock Distribution for more details. 3.5.8.2 FlexBus signal multiplexing The multiplexing of the FlexBus address and data signals is controlled by the port control module. However, the multiplexing of some of the FlexBus control signals are controlled by the port control and FlexBus modules. The port control module registers control whether the FlexBus or another module signals are available on the external pin, while the FlexBus's CSPMCR register configures which FlexBus signals are available from the module. The control signals are grouped as illustrated: Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 115 General Business Information

Page 116

Group3 Group2 Group1 Group4 Group5 CSPMCR FlexBus Port Control Module To other modules To other modules To other modules To other modules To other modules External Pins FB_ALE Reserved FB_TSIZ0 Reserved FB_TSIZ1 Reserved Reserved Reserved FB_CS1 FB_TS FB_CS4 FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 FB_CS5 FB_TBST FB_CS2 FB_TA FB_CS3 Figure 3-32. FlexBus control signal multiplexing Memories and memory interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 116 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 117

Therefore, use the CSPMCR and port control registers to configure which control signal is available on the external pin. All control signals, except for FB_TA, are assigned to the ALT5 function in the port control module. Since, unlike the other control signals, FB_TA is an input signal, it is assigned to the ALT6 function. 3.5.8.3 FlexBus CSCR0 reset value On this device the CSCR0 resets to 0x003F_FC00. Configure this register as needed before performing any FlexBus access. 3.5.8.4 FlexBus Security When security is enabled on the device, FlexBus accesses may be restricted by configuring the FBSL field in the SIM's SOPT2 register. See System Integration Module (SIM) for details. 3.5.8.5 FlexBus line transfers Line transfers are not possible from the ARM Cortex-M4 core. Ignore any references to line transfers in the FlexBus chapter. 3.6 Security 3.6.1 CRC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 117 General Business Information

Page 118

Register access Peripheral bridge CRC Figure 3-33. CRC configuration Table 3-43. Reference links to related information Topic Related module Reference Full description CRC CRC System memory map System memory map Power management Power management 3.6.2 MMCAU Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. MMCAU Transfers ARM Cortex M4 Core PPB Figure 3-34. MMCAU configuration Table 3-44. Reference links to related information Topic Related module Reference Full description MMCAU MMCAU System memory map System memory map Clocking Clock Distribution Power Management Power Management Transfers Private Peripheral Bus (PPB) ARM Cortex M4 Core Security K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 118 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 119

3.6.3 RNG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Register access Peripheral bridge Random number generator Figure 3-35. RNG configuration Table 3-45. Reference links to related information Topic Related module Reference Full description RNG RNG System memory map System memory map Clocking Clock distribution Power management Power management 3.7 Analog 3.7.1 16-bit SAR ADC with PGA Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 119 General Business Information

Page 120

Signal multiplexing Module signals Register access 16-bit SAR ADC Peripheral bus controller 0 Other peripherals Transfers Figure 3-36. 16-bit SAR ADC with PGA configuration Table 3-46. Reference links to related information Topic Related module Reference Full description 16-bit SAR ADC with PGA 16-bit SAR ADC with PGA System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.1.1 ADC instantiation information This device contains two ADCs. Each ADC contains a PGA channel for a total of two separate PGAs. 3.7.1.1.1 Number of ADC channels The number of ADC channels present on the device is determined by the pinout of the specific device package. For details regarding the number of ADC channel available on a particular package, refer to the signal multiplexing chapter of this MCU. 3.7.1.2 DMA Support on ADC Applications may require continuous sampling of the ADC (4K samples/sec) that may have considerable load on the CPU. Though using PDB to trigger ADC may reduce some CPU load, The ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate or cases were PDB is bypassed. The ADC can trigger the DMA (via DMA req) on conversion completion. Analog K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 120 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 121

3.7.1.3 Connections/channel assignment 3.7.1.3.1 ADC0 Connections/Channel Assignment NOTE As indicated by the following sections, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode. 3.7.1.3.1.1 ADC0 Channel Assignment for 144-Pin Package ADC Channel (SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 00000 DAD0 ADC0_DP0 and ADC0_DM01 ADC0_DP02 00001 DAD1 ADC0_DP1 and ADC0_DM1 ADC0_DP1 00010 DAD2 PGA0_DP and PGA0_DM PGA0_DP 00011 DAD3 ADC0_DP3 and ADC0_DM33 ADC0_DP34 001005 AD4a Reserved Reserved 001015 AD5a Reserved Reserved 001105 AD6a Reserved Reserved 001115 AD7a Reserved Reserved 001005 AD4b Reserved ADC0_SE4b 001015 AD5b Reserved ADC0_SE5b 001105 AD6b Reserved ADC0_SE6b 001115 AD7b Reserved ADC0_SE7b 01000 AD8 Reserved ADC0_SE86 01001 AD9 Reserved ADC0_SE97 01010 AD10 Reserved ADC0_SE10 01011 AD11 Reserved ADC0_SE11 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved ADC0_SE14 01111 AD15 Reserved ADC0_SE15 10000 AD16 Reserved ADC0_SE16 10001 AD17 Reserved ADC0_SE17 10010 AD18 Reserved ADC0_SE18 10011 AD19 Reserved ADC0_DM08 10100 AD20 Reserved ADC0_DM1 10101 AD21 Reserved ADC0_SE21 10110 AD22 Reserved ADC0_SE22 Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 121 General Business Information

Page 122

ADC Channel (SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 10111 AD23 Reserved 12-bit DAC0 Output/ ADC0_SE23 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff)9 Bandgap (S.E)9 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled 1. Interleaved with ADC1_DP3 and ADC1_DM3 2. Interleaved with ADC1_DP3 3. Interleaved with ADC1_DP0 and ADC1_DM0 4. Interleaved with ADC1_DP0 5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 6. Interleaved with ADC1_SE8 7. Interleaved with ADC1_SE9 8. Interleaved with ADC1_DM3 9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification. 3.7.1.4 ADC1 Connections/Channel Assignment NOTE As indicated in the following tables, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode. 3.7.1.4.1 ADC1 Channel Assignment for 144-Pin Package ADC Channel (SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 00000 DAD0 ADC1_DP0 and ADC1_DM01 ADC1_DP02 00001 DAD1 ADC1_DP1 and ADC1_DM1 ADC1_DP1 00010 DAD2 PGA1_DP and PGA1_DM PGA1_DP 00011 DAD3 ADC1_DP3 and ADC1_DM33 ADC1_DP34 001005 AD4a Reserved ADC1_SE4a 001015 AD5a Reserved ADC1_SE5a 001105 AD6a Reserved ADC1_SE6a 001115 AD7a Reserved ADC1_SE7a Table continues on the next page... Analog K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 122 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 123

ADC Channel (SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 001005 AD4b Reserved ADC1_SE4b 001015 AD5b Reserved ADC1_SE5b 001105 AD6b Reserved ADC1_SE6b 001115 AD7b Reserved ADC1_SE7b 01000 AD8 Reserved ADC1_SE86 01001 AD9 Reserved ADC1_SE97 01010 AD10 Reserved ADC1_SE10 01011 AD11 Reserved ADC1_SE11 01100 AD12 Reserved ADC1_SE12 01101 AD13 Reserved ADC1_SE13 01110 AD14 Reserved ADC1_SE14 01111 AD15 Reserved ADC1_SE15 10000 AD16 Reserved ADC1_SE16 10001 AD17 Reserved ADC1_SE17 10010 AD18 Reserved VREF Output 10011 AD19 Reserved ADC1_DM08 10100 AD20 Reserved ADC1_DM1 10101 AD21 Reserved Reserved 10110 AD22 Reserved 10111 AD23 Reserved 12-bit DAC1 Output/ ADC1_SE23 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff)9 Bandgap (S.E)9 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled 1. Interleaved with ADC0_DP3 and ADC0_DM3 2. Interleaved with ADC0_DP3 3. Interleaved with ADC0_DP0 and ADC0_DM0 4. Interleaved with ADC0_DP0 5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 6. Interleaved with ADC0_SE8 7. Interleaved with ADC0_SE9 8. Interleaved with ADC0_DM3 9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 123 General Business Information

Page 124

3.7.1.5 ADC Channels MUX Selection The following figure shows the assignment of ADCx_SEn channels a and b through a MUX selection to ADC. To select between alternate set of channels, refer to ADCx_CFG2[MUXSEL] bit settings for more details. <0A>#<23>&<26><17><02>=<3D><12><12><13><12><13>? ADCx_SE4a ADCx_SE5a ADCx_SE6a ADCx_SE7a ADCx_SE4b ADCx_SE5b ADCx_SE6b ADCx_SE7b <0A>#<23>&<26><16><02>=<3D><12><12><13><12><12>? <0A>#<23>&<26><18><02>=<3D><12><12><13><13><12>? <0A>#<23>&<26><19><02>=<3D><12><12><13><13><13>? ADC Figure 3-37. ADCx_SEn channels a and b selection 3.7.1.6 ADC Hardware Interleaved Channels The AD8 and AD9 channels on ADCx are interleaved in hardware using the following configuration. ADC0 AD8 AD9 ADC1 AD8 AD9 ADC0_SE8/ADC1_SE8 ADC0_SE9/ADC1_SE9 Figure 3-38. ADC hardware interleaved channels integration Analog K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 124 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 125

3.7.1.7 ADC and PGA Reference Options The ADC supports the following references: • VREFH/VREFL - connected as the primary reference option • 1.2 V VREF_OUT - connected as the VALT reference option ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to REFSEL description in ADC chapter for more details. The only reference option for the PGA is the 1.2 V VREF_OUT source. The VREF_OUT signal can either be driven by an external voltage source via the VREF_OUT pin or from the output of the VREF module. Ensure that the VREF module is disabled when an external voltage source is used instead. For PGA maximum differential input signal swing range, refer to the device data sheet for 16-bit ADC with PGA characteristics. 3.7.1.8 ADC triggers The ADC supports both software and hardware triggers. The primary hardware mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The PDB trigger can receive the RTC (alarm/seconds) trigger input forcing ADC conversions in run mode (where PDB is enabled). On the other hand, the ADC can conduct conversions in low power modes, not triggered by PDB. This allows the ADC to do conversions in low power mode and store the output in the result register. The ADC generates interrupt when the data is ready in the result register that wakes the system from low power mode. The PDB can also be bypassed by using the ADCxTRGSEL bits in the SOPT7 register. For operation of triggers in different modes, refer to Power Management chapter. 3.7.1.9 Alternate clock For this device, the alternate clock is connected to OSCERCLK. NOTE This clock option is only usable when OSCERCLK is in the MHz range. A system with OSCERCLK in the kHz range has the optional clock source below minimum ADC clock operating frequency. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 125 General Business Information

Page 126

3.7.1.10 ADC low-power modes This table shows the ADC low-power modes and the corresponding chip low-power modes. Table 3-47. ADC low-power modes Module mode Chip mode Wait Wait, VLPW Normal Stop Stop, VLPS Low Power Stop LLS, VLLS3, VLLS2, VLLS1 3.7.1.11 PGA Integration • No additional external pins are required for the PGA as it is part of the ADC and is selected as a separate channel • Each PGA connects to the differential ADC channels • The PGA outputs differential pairs that are connected to ADC differential input • When the PGA is used, differential input from the pins is connected to differential input channel 2 on ADCx Analog K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 126 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 127

ADC0 DAD1 DAD0 DAD2 DAD3 ADC1 DAD3 DAD2 DAD0 DAD1 PGA1 PGA0 PGA0_DP/ADC0_DP0/ADC1_DP3 PGA0_DM/ADC0_DM0/ADC1_DM3 PGA1_DP/ADC1_DP0/ADC0_DP3 PGA1_DM/ADC1_DM0/ADC0_DM3 ADC1_DP1 ADC1_DM1 ADC0_DP1 ADC0_DM1 Figure 3-39. PGA Integration 3.7.2 CMP Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 127 General Business Information

Page 128

Signal multiplexing Module signals Register access CMP Peripheral bridge 0 Other peripherals Figure 3-40. CMP configuration Table 3-48. Reference links to related information Topic Related module Reference Full description Comparator (CMP) Comparator System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.2.1 CMP input connections The following table shows the fixed internal connections to the CMP. CMP Inputs CMP0 CMP1 CMP2 IN0 CMP0_IN0 CMP1_IN0 CMP2_IN0 IN1 CMP0_IN1 CMP1_IN1 CMP2_IN1 IN2 CMP0_IN2 CMP1_IN2 CMP2_IN2 IN3 CMP0_IN3 12-bit DAC0_OUT/ CMP1_IN3 12-bit DAC1_OUT/ CMP2_IN3 IN4 12-bit DAC1_OUT/ CMP0_IN4 — — IN5 VREF output/CMP0_IN5 VREF output/CMP1_IN5 — IN6 Bandgap Bandgap Bandgap IN7 6b DAC0 reference 6b DAC1 reference 6b DAC2 reference 3.7.2.2 CMP external references The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows: Analog K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 128 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 129

• VREF_OUT - Vin1 input • VDD - Vin2 input 3.7.2.3 External window/sample input Individual PDB pulse-out signals control each CMP Sample/Window timing. 3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access 12-bit DAC Peripheral bus controller 0 Other peripherals Transfers Figure 3-41. 12-bit DAC configuration Table 3-49. Reference links to related information Topic Related module Reference Full description 12-bit DAC 12-bit DAC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.3.1 12-bit DAC Overview This device contains two 12-bit digital-to-analog converters (DAC) with programmable reference generator output. The DAC includes a FIFO for DMA support. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 129 General Business Information

Page 130

3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. 3.7.3.3 12-bit DAC Reference For this device VREF_OUT and VDDA are selectable as the DAC reference. VREF_OUT is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options. Be aware that if the DAC and ADC use the VREF_OUT reference simultaneously, some degradation of ADC accuracy is to be expected due to DAC switching. 3.7.4 VREF Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access VREF Peripheral bus controller 0 Other peripherals Transfers Figure 3-42. VREF configuration Table 3-50. Reference links to related information Topic Related module Reference Full description VREF VREF System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing Analog K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 130 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 131

3.7.4.1 VREF Overview This device includes a voltage reference (VREF) to supply an accurate 1.2 V voltage output. The voltage reference can provide a reference voltage to external peripherals or a reference to analog peripherals, such as the ADC, DAC, or CMP. NOTE PMC_REGSC[BGEN] bit must be set if the VREF regulator is required to remain operating in VLPx modes. NOTE For either an internal or external reference if the VREF_OUT functionality is being used, VREF_OUT signal must be connected to an output load capacitor. Refer the device data sheet for more details. 3.8 Timers 3.8.1 PDB Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access PDB Peripheral bus controller 0 Other peripherals Transfers Figure 3-43. PDB configuration Table 3-51. Reference links to related information Topic Related module Reference Full description PDB PDB System memory map System memory map Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 131 General Business Information

Page 132

Table 3-51. Reference links to related information (continued) Topic Related module Reference Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.1.1 PDB Instantiation 3.8.1.1.1 PDB Output Triggers Table 3-52. PDB output triggers Number of PDB channels for ADC trigger 2 Number of pre-triggers per PDB channel 2 Number of DAC triggers 2 Number of PulseOut 3 3.8.1.1.2 PDB Input Trigger Connections Table 3-53. PDB Input Trigger Options PDB Trigger PDB Input 0000 External Trigger 0001 CMP 0 0010 CMP 1 0011 CMP 2 0100 PIT Ch 0 Output 0101 PIT Ch 1 Output 0110 PIT Ch 2 Output 0111 PIT Ch 3 Output 1000 FTM0 Init and Ext Trigger Outputs 1001 FTM1 Init and Ext Trigger Outputs 1010 FTM2 Init and Ext Trigger Outputs 1011 Reserved 1100 RTC Alarm 1101 RTC Seconds 1110 LPTMR Output 1111 Software Trigger Timers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 132 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 133

3.8.1.2 PDB Module Interconnections PDB trigger outputs Connection Channel 0 triggers ADC0 trigger Channel 1 triggers ADC1 trigger and synchronous input 1 of FTM0 DAC triggers DAC0 and DAC1 trigger Pulse-out Pulse-out connected to each CMP module's sample/window input to control sample operation 3.8.1.3 Back-to-back acknowledgement connections In this MCU, PDB back-to-back operation acknowledgment connections are implemented as follows: • PDB channel 0 pre-trigger 0 acknowledgement input: ADC1SC1B_COCO • PDB channel 0 pre-trigger 1 acknowledgement input: ADC0SC1A_COCO • PDB channel 1 pre-trigger 0 acknowledgement input: ADC0SC1B_COCO • PDB channel 1 pre-trigger 1 acknowledgement input: ADC1SC1A_COCO So, the back-to-back chain is connected as a ring: Channel 0 pre-trigger 0 Channel 1 pre-trigger 0 Channel 0 pre-trigger 1 Channel 1 pre-trigger 1 Figure 3-44. PDB back-to-back chain The application code can set the PDBx_CHnC1[BB] bits to configure the PDB pre- triggers as a single chain or several chains. 3.8.1.4 PDB Interval Trigger Connections to DAC In this MCU, PDB interval trigger connections to DAC are implemented as follows. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 133 General Business Information

Page 134

• PDB interval trigger 0 connects to DAC0 hardware trigger input. • PDB interval trigger 1 connects to DAC1 hardware trigger input. 3.8.1.5 DAC External Trigger Input Connections In this MCU, the following DAC external trigger inputs are implemented. • DAC external trigger input 0: ADC0SC1A_COCO • DAC external trigger input 1: ADC1SC1A_COCO NOTE Application code can set the PDBx_DACINTCn[EXT] bit to allow DAC external trigger input when the corresponding ADC Conversion complete flag, ADCx_SC1n[COCO], is set. 3.8.1.6 Pulse-Out Connection Individual PDB Pulse-Out signals are connected to each CMP block and used for sample window. 3.8.1.7 Pulse-Out Enable Register Implementation The following table shows the comparison of pulse-out enable register at the module and chip level. Table 3-54. PDB pulse-out enable register Register Module implementation Chip implementation POnEN 7:0 - POEN 31:8 - Reserved 0 - POEN[0] for CMP0 1 - POEN[1] for CMP1 2 - POEN[2] for CMP2 31:3 - Reserved 3.8.2 FlexTimer Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Timers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 134 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 135

Signal multiplexing Module signals Register access FlexTimer Peripheral bus controller 0 Other peripherals Transfers Figure 3-45. FlexTimer configuration Table 3-55. Reference links to related information Topic Related module Reference Full description FlexTimer FlexTimer System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.2.1 Instantiation Information This device contains three FlexTimer modules. The following table shows how these modules are configured. Table 3-56. FTM Instantiations FTM instance Number of channels Features/usage FTM0 8 3-phase motor + 2 general purpose or stepper motor FTM1 21 Quadrature decoder or general purpose FTM2 21 Quadrature decoder or general purpose 1. Only channels 0 and 1 are available. Compared with the FTM0 configuration, the FTM1 and FTM2 configuration adds the Quadrature decoder feature and reduces the number of channels. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 135 General Business Information

Page 136

3.8.2.2 External Clock Options By default each FTM is clocked by the internal bus clock (the FTM refers to it as system clock). Each module contains a register setting that allows the module to be clocked from an external clock instead. There are two external FTM_CLKINx pins that can be selected by any FTM module via the SOPT4 register in the SIM module. 3.8.2.3 Fixed frequency clock The fixed frequency clock for each FTM is MCGFFCLK. 3.8.2.4 FTM Interrupts The FlexTimer has multiple sources of interrupt. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller. When an FTM interrupt occurs, read the FTM status registers (FMS, SC, and STATUS) to determine the exact interrupt source. 3.8.2.5 FTM Fault Detection Inputs The following fault detection input options for the FTM modules are selected via the SOPT4 register in the SIM module. The external pin option is selected by default. • FTM0 FAULT0 = FTM0_FLT0 pin or CMP0 output • FTM0 FAULT1 = FTM0_FLT1 pin or CMP1 output • FTM0 FAULT2 = FTM0_FLT2 pin or CMP2 output • FTM0 FAULT3 = FTM0_FLT3 pin • FTM1 FAULT0 = FTM1_FLT0 pin or CMP0 output • FTM1 FAULT1 = CMP1 output • FTM1 FAULT2 = CMP2 output • FTM2 FAULT0 = FTM2_FLT0 pin or CMP0 output • FTM2 FAULT1 = CMP1 output • FTM2 FAULT2 = CMP2 output 3.8.2.6 FTM Hardware Triggers The FTM synchronization hardware triggers are connected in the chip as follows: Timers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 136 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 137

• FTM0 hardware trigger 0 = CMP0 Output or FTM1 Match (when enabled in the FTM1 External Trigger (EXTTRIG) register) • FTM0 hardware trigger 1 = PDB channel 1 Trigger Output or FTM2 Match (when enabled in the FTM2 External Trigger (EXTTRIG) register) • FTM0 hardware trigger 2 = FTM0_FLT0 pin • FTM1 hardware trigger 0 = CMP0 Output • FTM1 hardware trigger 1 = CMP1 Output • FTM1 hardware trigger 2 = FTM1_FLT0 pin • FTM2 hardware trigger 0 = CMP0 Output • FTM2 hardware trigger 1 = CMP2 Output • FTM2 hardware trigger 2 = FTM2_FLT0 pin For the triggers with more than one option, the SOPT4 register in the SIM module controls the selection. 3.8.2.7 Input capture options for FTM module instances The following channel 0 input capture source options are selected via the SOPT4 register in the SIM module. The external pin option is selected by default. • FTM1 channel 0 input capture = FTM1_CH0 pin or CMP0 output or CMP1 output or USB start of frame pulse • FTM2 channel 0 input capture = FTM2_CH0 pin or CMP0 output or CMP1 output NOTE When the USB start of frame pulse option is selected as an FTM channel input capture, disable the USB SOF token interrupt in the USB Interrupt Enable register (INTEN[SOFTOKEN]) to avoid USB enumeration conflicts. 3.8.2.8 FTM output triggers for other modules FTM output triggers can be selected as input triggers for the PDB and ADC modules. See PDB Instantiation and ADC triggers. 3.8.2.9 FTM Global Time Base This chip provides the optional FTM global time base feature (see Global time base (GTB)). Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 137 General Business Information

Page 138

FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: gtb_in FTM1 GTBEEN = 1 FTM Counter CONF Register GTBEOUT = 0 FTM0 GTBEEN = 1 FTM Counter CONF Register GTBEOUT = 1 gtb_out gtb_in gtb_in FTM2 GTBEEN = 1 FTM Counter CONF Register GTBEOUT = 0 Figure 3-46. FTM Global Time Base Configuration 3.8.2.10 FTM BDM and debug halt mode In the FTM chapter, references to the chip being in "BDM" are the same as the chip being in “debug halt mode". 3.8.3 PIT Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Register access Peripheral bridge Periodic interrupt timer Figure 3-47. PIT configuration Table 3-57. Reference links to related information Topic Related module Reference Full description PIT PIT Table continues on the next page... Timers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 138 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 139

Table 3-57. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.3.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA Mux as shown in the table below. Table 3-58. PIT channel assignments for periodic DMA triggering DMA Channel Number PIT Channel DMA Channel 0 PIT Channel 0 DMA Channel 1 PIT Channel 1 DMA Channel 2 PIT Channel 2 DMA Channel 3 PIT Channel 3 3.8.3.2 PIT/ADC Triggers PIT triggers are selected as ADCx trigger sources using the SOPT7[ADCxTRGSEL] bits in the SIM module. For more details, refer to SIM chapter. 3.8.4 Low-power timer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 139 General Business Information

Page 140

Signal multiplexing Register access Peripheral bridge Module signals Low-power timer Figure 3-48. LPT configuration Table 3-59. Reference links to related information Topic Related module Reference Full description Low-power timer Low-power timer System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.8.4.1 LPTMR prescaler/glitch filter clocking options The prescaler and glitch filter of the LPTMR module can be clocked from one of four sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the chip-specific clock assignments for this bitfield. NOTE The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes. LPTMR0_PSR[PCS] Prescaler/glitch filter clock number Chip clock 00 0 MCGIRCLK — internal reference clock (not available in VLPS/LLS/VLLS modes) 01 1 LPO — 1 kHz clock 10 2 ERCLK32K — secondary external reference clock 11 3 OSCERCLK — external reference clock See Clock Distribution for more details on these clocks. Timers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 140 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 141

3.8.4.2 LPTMR pulse counter input options The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input 00 0 CMP0 output 01 1 LPTMR_ALT1 pin 10 2 LPTMR_ALT2 pin 11 3 3.8.5 CMT Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access CMT Peripheral bus controller 0 Figure 3-49. CMT configuration Table 3-60. Reference links to related information Topic Related module Reference Full description Carrier modulator transmitter (CMT) CMT System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.5.1 Instantiation Information This device contains one CMT module. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 141 General Business Information

Page 142

3.8.5.2 IRO Drive Strength The IRO pad requires higher current drive than can be obtained from a single pad. For this device, the pin associated with the CMT_IRO signal is doubled bonded to two pads. The SOPT2[PTD7PAD] field in SIM module can be used to configure the pin associated with the CMT_IRO signal as a higher current output port pin. 3.8.6 RTC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access Peripheral bridge Module signals Real-time clock Figure 3-50. RTC configuration Table 3-61. Reference links to related information Topic Related module Reference Full description RTC RTC System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.6.1 RTC_CLKOUT signal When the RTC is enabled and the port control module selects the RTC_CLKOUT function, the RTC_CLKOUT signal outputs a 1 Hz or 32 kHz output derived from RTC oscillator as shown below. Timers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 142 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 143

SIM_SOPT2[RTCCLKOUTSEL] RTC_CLKOUT RTC 1Hz clock RTC 32kHz clock RTC_CR[CLKO] Figure 3-51. RTC_CLKOUT generation 3.9 Communication interfaces 3.9.1 Ethernet Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access Ethernet Peripheral bridge 1 Crossbar switch Transfers Figure 3-52. Ethernet configuration Table 3-62. Reference links to related information Topic Related module Reference Full description Ethernet Ethernet System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 143 General Business Information

Page 144

3.9.1.1 Ethernet Clocking Options The Ethernet module uses the following clocks: • The device's system clock is connected to the module clock, as named in the Ethernet chapter. The minimum system clock frequency for 100 Mbps operation is 25 MHz. • An externally-supplied 25 MHz MII clock or 50 MHz RMII clock. This clock is used as the timing reference for the external MII or RMII interface. • A time-stamping clock for the IEEE 1588 timers. For more details on the Ethernet module clocking options, see Ethernet Clocking. 3.9.1.2 RMII Clocking On this device, RMII_REF_CLK is internally tied to EXTAL. See Clock Distribution for clocking requirements. 3.9.1.3 IEEE 1588 Timers The ethernet module includes a four channel timer module for IEEE 1588 timestamping. The timer supports input capture (rising, falling, or both edges), output compare (toggle or pulse with programmable polarity). The timer matches on greater than or equal (the 1588 can skip numbers, so the counter might not ever exactly match the compare value). The counter is able to operate asynchronously to the ethernet bus by using one of four clock sources. See Ethernet Clocking for more details. 3.9.1.4 Ethernet Operation in Low Power Modes The Ethernet module is not fully operational in any low power modes. However, the module does support magic packet detection that can generate a wakeup in stop mode if enabled. During low power operation: • The MAC transmit logic is disabled • The core FIFO receive/transmit functions are disabled • The MAC receive logic is kept in normal mode, but it ignores all traffic from the line except magic packets. Communication interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 144 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 145

The recieve logic needed for magic packet detection is clocked using the externally- supplied MII or RMII clock. This allows for the wakeup functionality in stop mode. No Ethernet operation, including magic packet wakeup, is supported in VLPx modes. 3.9.1.4.1 IEEE 1588 Timer Operation in Low Power Modes The 1588 counter and 1588 timer channels can continue operating in low power modes provided their clock is enabled in that mode. The 1588 timer channels can also generate an interrupt to exit the low power mode if the clock is enabled in that mode. 3.9.1.5 Ethernet Doze Mode The doze mode for the Ethernet module is the same as the wait and VLPW modes for the chip. 3.9.1.6 Ethernet Interrupts The Ethernet has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate an interrupt request. See below for a summary: Interrupt request Interrupt source IEEE 1588 timer interrupt • Periodic timer overflow • Time stamp available • 1588 timer interrupt Transmit interrupt • Transmit frame interrupt • Transmit buffer interrupt Receive interrupt • Receive frame interrupt • Receive buffer interrupt Error and miscellaneous interrupt • Wake-up • Payload receive error • Babbling receive error • Babbling transmit error • Graceful stop complete • MII interrupt – Data transfer done • Ethernet bus error • Late collision • Collision retry limit Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 145 General Business Information

Page 146

3.9.1.7 Ethernet event signal The event signal output is not supported on this device. Therefore, ATCR[PINPER] has no effect. 3.9.2 Universal Serial Bus (USB) FS Subsystem The USB FS subsystem includes these components: • Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) device or FS/LS host. The module complies with the USB 2.0 specification. • USB transceiver that includes internal 15 kΩ pulldowns on the D+ and D- lines for host mode functionality. • A 3.3 V regulator. • USB device charger detection module. • VBUS detect signal: To detect a valid VBUS in device mode, use a GPIO signal that can wake the chip in all power modes. USB controller FS/LS transceiver USB voltage regulator D+ D- VREGIN Device charger detect VOUT33 Figure 3-53. USB Subsystem Overview 3.9.2.1 USB Wakeup When the USB detects that there is no activity on the USB bus for more than 3 ms, the INT_STAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the appropriate action. Waking from a low power mode (except in LLS/VLLS mode where USB is not powered) occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting the USBTRC0[USBRESMEN] bit enables this function. Communication interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 146 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 147

[Error processing page 147: code=7: object is not a stream]

Page 148

USB Regulator USB XCVR USB Controller USB0_DM USB0_DP VDD VOUT33 VREGIN TYPE A D+ D- VBUS Cstab To PMC and Pads Chip Charger Detect VBUS Sense VSS Charger Li-Ion Si2301 Figure 3-55. USB regulator Li-ion usecase 3.9.2.2.3 USB bus power supply The chip can also be powered by the USB bus directly. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU, then to power USB transceiver or external sensor. USB Regulator USB XCVR USB Controller USB0_DP USB0_DM VDD VOUT33 VREGIN TYPE A D+ D- VBUS Cstab To PMC and Pads Chip Figure 3-56. USB regulator bus supply Communication interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 148 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 149

3.9.2.3 USB power management The regulator should be put into STANDBY mode whenever the chip is in Stop mode. This can be done by setting the SIM_SOPT1[USBSTBY] bit. 3.9.2.4 USB controller configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access USB controller Peripheral bridge 0 Crossbar switch Transfers Figure 3-57. USB controller configuration Table 3-63. Reference links to related information Topic Related module Reference Full description USB controller USB controller System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing NOTE When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating. 3.9.2.5 USB DCD Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 149 General Business Information

Page 150

Register access USB Device Charger Detect Peripheral bridge 0 USB OTG Figure 3-58. USB DCD configuration Table 3-64. Reference links to related information Topic Related module Reference Full description USB DCD USB DCD System memory map System memory map Clocking Clock Distribution USB controller USB controller 3.9.2.6 USB Voltage Regulator Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals USB Voltage Regulator USB OTG Figure 3-59. USB Voltage Regulator configuration Table 3-65. Reference links to related information Topic Related module Reference Full description USB Voltage Regulator USB Voltage Regulator System memory map System memory map Clocking Clock Distribution USB controller USB controller Signal Multiplexing Port control Signal Multiplexing Communication interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 150 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 151

NOTE When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating. 3.9.3 CAN Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access FlexCAN Peripheral bridge Module signals Figure 3-60. CAN configuration Table 3-66. Reference links to related information Topic Related module Reference Full description CAN CAN System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.3.1 Number of FlexCAN modules This device contains 2 identical FlexCAN modules. 3.9.3.2 Reset value of MDIS bit The CAN_MCR[MDIS] bit is set after reset. Therefore, FlexCAN module is disabled following a reset. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 151 General Business Information

Page 152

3.9.3.3 Number of message buffers Each FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes. 3.9.3.4 FlexCAN Clocking 3.9.3.4.1 Clocking Options The FlexCAN module has a register bit CANCTRL[CLK_SRC] that selects between clocking the FlexCAN from the internal bus clock or the input clock (EXTAL). 3.9.3.4.2 Clock Gating The clock to each CAN module can be gated on and off using the SCGCn[CANx] bits. These bits are cleared after any reset, which disables the clock to the corresponding module. The appropriate clock enable bit should be set by software at the beginning of the FlexCAN initialization routine to enable the module clock before attempting to initialize any of the FlexCAN registers. 3.9.3.5 FlexCAN Interrupts The FlexCAN has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate a single interrupt request. See below for the mapping of the individual interrupt sources to the interrupt request: Request Sources Message buffer Message buffers 0-15 Bus off Bus off Error • Bit1 error • Bit0 error • Acknowledge error • Cyclic redundancy check (CRC) error • Form error • Stuffing error • Transmit error warning • Receive error warning Transmit Warning Transmit Warning Receive Warning Receive Warning Wake-up Wake-up Communication interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 152 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 153

3.9.3.6 FlexCAN Operation in Low Power Modes The FlexCAN module is operational in VLPR and VLPW modes. With the 2 MHz bus clock, the fastest supported FlexCAN transfer rate is 256 kbps. The bit timing parameters in the module must be adjusted for the new frequency, but full functionality is possible. The FlexCAN module can be configured to generate a wakeup interrupt in STOP and VLPS modes. When the FlexCAN is configured to generate a wakeup, a recessive to dominant transition on the CAN bus generates an interrupt. 3.9.3.7 FlexCAN Doze Mode The Doze mode for the FlexCAN module is the same as the Wait and VLPW modes for the chip. 3.9.4 SPI configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access SPI Peripheral bridge Module signals Figure 3-61. SPI configuration Table 3-67. Reference links to related information Topic Related module Reference Full description SPI SPI System memory map System memory map Clocking Clock Distribution Signal Multiplexing Port control Signal Multiplexing Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 153 General Business Information

Page 154

3.9.4.1 SPI Modules Configuration This device contains three SPI modules. 3.9.4.2 SPI clocking The SPI module is clocked by the internal bus clock (the DSPI refers to it as system clock). The module has an internal divider, with a minimum divide is two. So, the SPI can run at a maximum frequency of bus clock/2. 3.9.4.3 Number of CTARs SPI CTAR registers define different transfer attribute configurations. The SPI module supports up to eight CTAR registers. This device supports two CTARs on all instances of the SPI. In master mode, the CTAR registers define combinations of transfer attributes, such as frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. In slave mode only CTAR0 is used, and a subset of its bitfields sets the slave transfer attributes. 3.9.4.4 TX FIFO size Table 3-68. SPI transmit FIFO size SPI Module Transmit FIFO size SPI0 4 SPI1 4 SPI2 4 3.9.4.5 RX FIFO Size SPI supports up to 16-bit frame size during reception. Table 3-69. SPI receive FIFO size SPI Module Receive FIFO size SPI0 4 Table continues on the next page... Communication interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 154 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 155

Table 3-69. SPI receive FIFO size (continued) SPI Module Receive FIFO size SPI1 4 SPI2 4 3.9.4.6 Number of PCS signals The following table shows the number of peripheral chip select signals available per SPI module. Table 3-70. SPI PCS signals SPI Module PCS Signals SPI0 SPI_PCS[5:0] SPI1 SPI_PCS[3:0] SPI2 SPI_PCS[1:0] 3.9.4.7 SPI Operation in Low Power Modes In VLPR and VLPW modes the SPI is functional; however, the reduced system frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW modes the max SPI_CLK frequency is 2MHz. In stop and VLPS modes, the clocks to the SPI module are disabled. The module is not functional, but it is powered so that it retains state. There is one way to wake from stop mode via the SPI, which is explained in the following section. 3.9.4.7.1 Using GPIO Interrupt to Wake from stop mode Here are the steps to use a GPIO to create a wakeup upon reception of SPI data in slave mode:

Point the GPIO interrupt vector to the desired interrupt handler.
Enable the GPIO input to generate an interrupt on either the rising or falling edge (depending on the polarity of the chip select signal).
Enter Stop or VLPS mode and Wait for the GPIO interrupt. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 155 General Business Information

Page 156

NOTE It is likely that in using this approach the first word of data from the SPI host might not be received correctly. This is dependent on the transfer rate used for the SPI, the delay between chip select assertion and presentation of data, and the system interrupt latency. 3.9.4.8 SPI Doze Mode The Doze mode for the SPI module is the same as the Wait and VLPW modes for the chip. 3.9.4.9 SPI Interrupts The SPI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request per SPI module to the interrupt controller. When an SPI interrupt occurs, read the SPI_SR to determine the exact interrupt source. 3.9.4.10 SPI clocks This table shows the SPI module clocks and the corresponding chip clocks. Table 3-71. SPI clock connections Module clock Chip clock System Clock Bus Clock 3.9.5 I2C Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Communication interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 156 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 157

Signal multiplexing Register access Peripheral bridge Module signals 2I C Figure 3-62. I2C configuration Table 3-72. Reference links to related information Topic Related module Reference Full description I2C I2C System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.5.1 Number of I2C modules This device has two I2C modules. 3.9.6 UART Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 157 General Business Information

Page 158

Signal multiplexing Register access Peripheral bridge Module signals UART Figure 3-63. UART configuration Table 3-73. Reference links to related information Topic Related module Reference Full description UART UART System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.6.1 UART configuration information This device contains six UART modules. This section describes how each module is configured on this device.

Standard features of all UARTs: • RS-485 support • Hardware flow control (RTS/CTS) • 9-bit UART to support address mark with parity • MSB/LSB configuration on data
UART0 and UART1 are clocked from the core clock, the remaining UARTs are clocked on the bus clock. The maximum baud rate is 1/16 of related source clock frequency.
IrDA is available on all UARTs
UART0 contains the standard features plus ISO7816
AMR support on all UARTs. The pin control and interrupts (PORT) module supports open-drain for all I/O.
UART0 and UART1 contains 8-entry transmit and 8-entry receive FIFOs
All other UARTs contain a 1-entry transmit and receive FIFOs
CEA709.1-B (LON) is available in UART0 Communication interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 158 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 159

3.9.6.2 UART wakeup The UART can be configured to generate an interrupt/wakeup on the first active edge that it receives. 3.9.6.3 UART interrupts The UART has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate a single interrupt request. See below for the mapping of the individual interrupt sources to the interrupt request: The status interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 UART 3 UART 4 UART 5 Transmit data empty x x x x x x Transmit complete x x x x x x Idle line x x x x x x Receive data full x x x x x x LIN break detect x x x x x x RxD pin active edge x x x x x x Initial character detect x — — — — — The error interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 UART 3 UART 4 UART 5 Receiver overrun x x x x x x Noise flag x x x x x x Framing error x x x x x x Parity error x x x x x x Transmitter buffer overflow x x x x x x Receiver buffer overflow x x x x x x Receiver buffer underflow x x x x x x Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 159 General Business Information

Page 160

Source UART 0 UART 1 UART 2 UART 3 UART 4 UART 5 Transmit threshold (ISO7816) x — — — — — Receiver threshold (ISO7816) x — — — — — Wait timer (ISO7816) x — — — — — Character wait timer (ISO7816) x — — — — — Block wait timer (ISO7816) x — — — — — Guard time violation (ISO7816) x — — — — — The LON status interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 UART 3 UART 4 UART 5 Wbase expire after beta1 time slots (LON) x — — — — — Package received (LON) x — — — — — Package transmitted (LON) x — — — — — Package cycle time expired (LON) x — — — — — Preamble start (LON) x — — — — — Transmission fail (LON) x — — — — — Initial sync detection (LON) x — — — — — 3.9.7 SDHC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Communication interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 160 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 161

Crossbar switch Register access Peripheral bridge Module signals SDHC Transfers Signal multiplexing Figure 3-64. SDHC configuration Table 3-74. Reference links to related information Topic Related module Reference Full description SDHC SDHC System memory map System memory map Clocking Clock Distribution Power management Power management Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.9.7.1 SDHC clocking In addition to the system clock, the SDHC needs a clock for the base for the external card clock. There are four possible clock sources for this clock, selected by the SIM’s SOPT2 register: • Core/system clock • MCGPLLCLK or MCGFLLCLK • EXTAL • Bypass clock from off-chip (SDHC0_CLKIN) 3.9.7.2 SD bus pullup/pulldown constraints The SD standard requires the SD bus signals (except the SD clock) to be pulled up during data transfers. The SDHC also provides a feature of detecting card insertion/removal, by detecting voltage level changes on DAT[3] of the SD bus. To support this DAT[3] must be pulled down. To avoid a situation where the SDHC detects voltage changes due to normal data transfers on the SD bus as card insertion/removal, the interrupt relating to this event must be disabled after the card has been inserted and detected. It can be re- enabled after the card is removed. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 161 General Business Information

Page 162

3.9.8 I2S configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access Peripheral bridge Module signals 2I S Figure 3-65. I2S configuration Table 3-75. Reference links to related information Topic Related module Reference Full description I2S I2S System memory map System memory map Clocking Clock Distribution Power management Power management Signal multiplexing Port control Signal Multiplexing 3.9.8.1 Instantiation information This device contains one I2S module. As configured on the device, module features include: • TX data lines: 2 • RX data lines: 2 • FIFO size (words): 8 • Maximum words per frame: 32 • Maximum bit clock divider: 512 3.9.8.2 I2S/SAI clocking Communication interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 162 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 163

3.9.8.2.1 Audio Master Clock The audio master clock (MCLK) is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The audio master clock can also be output to or input from a pin. The transmitter and receiver have the same audio master clock inputs. 3.9.8.2.2 Bit Clock The I2S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. The module also supports the option for synchronous operation between the receiver and transmitterproduct. 3.9.8.2.3 Bus Clock The bus clock is used by the control registers and to generate synchronous interrupts and DMA requests. 3.9.8.2.4 I2S/SAI clock generation Each SAI peripheral can control the input clock selection, pin direction and divide ratio of one audio master clock. The MCLK Input Clock Select bit of the MCLK Control Register (MCR[MICS]) selects the clock input to the I2S/SAI module’s MCLK divider. The module's MCLK Divide Register (MDR) configures the MCLK divide ratio. The module's MCLK Output Enable bit of the MCLK Control Register (MCR[MOE]) controls the direction of the MCLK pin. The pin is the input from the pin when MOE is 0, and the pin is the output from the clock divider when MOE is 1. The transmitter and receiver can independently select between the bus clock and the audio master clock to generate the bit clock. Each module's Clocking Mode field of the Transmit Configuration 2 Register and Receive Configuration 2 Register (TCR2[MSEL] and RCR2[MSEL]) selects the master clock. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 163 General Business Information

Page 164

3.9.8.2.5 Clock gating and I2S/SAI initialization The clock to the I2S/SAI module can be gated using a bit in the SIM. To minimize power consumption, these bits are cleared after any reset, which disables the clock to the corresponding module. The clock enable bit should be set by software at the beginning of the module initialization routine to enable the module clock before initialization of any of the I2S/SAI registers. 3.9.8.3 I2S/SAI operation in low power modes 3.9.8.3.1 Stop and very low power modes In VLPS mode, the module behaves as it does in stop mode if VLPS mode is entered from run mode. However, if VLPS mode is entered from VLPR mode, the FIFO might underflow or overflow before wakeup from stop mode due to the limits in bus bandwidth. In VLPW and VLPR modes, the module is limited by the maximum bus clock frequencies. When operating from an internally generated bit clock or Audio Master Clock that is disabled in stop modes: In Stop mode, the transmitter is disabled after completing the current transmit frame, and, the receiver is disabled after completing the current receive frame. Entry into Stop mode is prevented–not acknowledged–while waiting for the transmitter and receiver to be disabled at the end of the current frame. 3.10 Human-machine interfaces 3.10.1 GPIO configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Human-machine interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 164 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 165

Signal multiplexing Register access Peripheral bridge Module signals GPIO controller Crossbar switch Transfers Figure 3-66. GPIO configuration Table 3-76. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock Distribution Power management Power management Transfers Crossbar switch Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.10.1.1 GPIO access protection The GPIO module does not have access protection because it is not connected to a peripheral bridge slot and is not protected by the MPU. 3.10.1.2 Number of GPIO signals The number of GPIO signals available on the devices covered by this document are detailed in Orderable part numbers. 3.10.2 TSI Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 165 General Business Information

Page 166

Signal multiplexing Register access Peripheral bridge Module signals Touch sense input module Figure 3-67. TSI configuration Table 3-77. Reference links to related information Topic Related module Reference Full description TSI TSI System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.10.2.1 Number of inputs This device includes one TSI module containing 16 inputs. In low-power modes, one selectable pin is active. 3.10.2.2 TSI module functionality in MCU operation modes Table 3-78. TSI module functionality in MCU operation modes MCU operation mode TSI clock sources TSI operation mode when GENCS[TSIEN] is 1 Functional electrode pins Required GENCS[STPE] state Run BUSCLK, MCGIRCLK, OSCERCLK Active mode All Don’t care Wait BUSCLK, MCGIRCLK, OSCERCLK Active mode All Don’t care Stop MCGIRCLK, OSCERCLK Active mode All 1 VLPR BUSCLK, MCGIRCLK, OSCERCLK Active mode All Don’t care VLPW BUSCLK, MCGIRCLK, OSCERCLK Active mode All Don’t care VLPS OSCERCLK Active mode All 1 Table continues on the next page... Human-machine interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 166 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 167

Table 3-78. TSI module functionality in MCU operation modes (continued) MCU operation mode TSI clock sources TSI operation mode when GENCS[TSIEN] is 1 Functional electrode pins Required GENCS[STPE] state LLS LPOCLK, VLPOSCCLK Low power mode Determined by PEN[LPSP] 1 VLLS3 LPOCLK, VLPOSCCLK Low power mode Determined by PEN[LPSP] 1 VLLS2 LPOCLK, VLPOSCCLK Low power mode Determined by PEN[LPSP] 1 VLLS1 LPOCLK, VLPOSCCLK Low power mode Determined by PEN[LPSP] 1 3.10.2.3 TSI clocks This table shows the TSI clocks and the corresponding chip clocks. Table 3-79. TSI clock connections Module clock Chip clock BUSCLK Bus clock MCGIRCLK MCGIRCLK OSCERCLK OSCERCLK LPOCLK 1 kHz LPO clock VLPOSCCLK ERCLK32K 3.10.2.4 TSI Interrupts The TSI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request. When a TSI interrupt occurs, read the TSI status register to determine the exact interrupt source. 3.10.2.5 Shield drive signal The shield drive signal is not supported on this device. Ignore this feature in the TSI chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 167 General Business Information

Page 168

Human-machine interfaces K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 168 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 169

Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. Table 4-1. System memory map System 32-bit Address Range Destination Slave Access 0x0000_0000–0x07FF_FFFF Program flash and read-only data (Includes exception vectors in first 1024 bytes) All masters 0x0800_0000–0x0FFF_FFFF FlexBus (Aliased area) Cortex-M4 core (M0) only 0x1000_0000–0x13FF_FFFF • For MK60DN256VLQ10: Reserved • For MK60DX256VLQ10: FlexNVM • For MK60DN512VLQ10: Reserved • For MK60DN256VMD10: Reserved • For MK60DX256VMD10: FlexNVM • For MK60DN512VMD10: Reserved All masters 0x1400_0000–0x17FF_FFFF For devices with FlexNVM: FlexRAM For devices with program flash only: Programming acceleration RAM All masters 0x1800_0000–0x1BFF_FFFF FlexBus (Aliased area) Cortex-M4 core (M0) only 0x1C00_0000–0x1FFF_FFFF SRAM_L: Lower SRAM (ICODE/DCODE) All masters 0x2000_0000–0x200F_FFFF SRAM_U: Upper SRAM bitband region All masters 0x2010_0000–0x21FF_FFFF Reserved – Table continues on the next page... K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 169 General Business Information

Page 170

Table 4-1. System memory map (continued) System 32-bit Address Range Destination Slave Access 0x2200_0000–0x23FF_FFFF Aliased to SRAM_U bitband Cortex-M4 core only 0x2400_0000–0x3FFF_FFFF Reserved – 0x4000_0000–0x4007_FFFF Bitband region for peripheral bridge 0 (AIPS-Lite0) Cortex-M4 core & DMA/EzPort 0x4008_0000–0x400F_EFFF Bitband region for peripheral bridge 1 (AIPS-Lite1) Cortex-M4 core & DMA/EzPort 0x400F_F000–0x400F_FFFF Bitband region for general purpose input/output (GPIO) Cortex-M4 core & DMA/EzPort 0x4010_0000–0x41FF_FFFF Reserved – 0x4200_0000–0x43FF_FFFF Aliased to peripheral bridge (AIPS-Lite) and general purpose input/output (GPIO) bitband Cortex-M4 core only 0x4400_0000–0x5FFF_FFFF Reserved – 0x6000_0000–0x7FFF_FFFF FlexBus (External Memory - Write-back) All masters 0x8000_0000–0x9FFF_FFFF FlexBus (External Memory - Write-through) All masters 0xA000_0000–0xDFFF_FFFF FlexBus (External Peripheral - Not executable) All masters 0xE000_0000–0xE00F_FFFF Private peripherals Cortex-M4 core only 0xE010_0000–0xFFFF_FFFF Reserved – NOTE

EzPort master port is statically muxed with DMA master port. Access rights to AIPS-Lite peripheral bridges and general purpose input/output (GPIO) module address space is limited to the core, DMA, and EzPort.
ARM Cortex-M4 core access privileges also includes accesses via the debug interface. 4.2.1 Aliased bit-band regions The SRAM_U, AIPS-Lite, and general purpose input/output (GPIO) module resources reside in the Cortex-M4 processor bit-band regions. The processor also includes two 32 MB aliased bit-band regions associated with the two 1 MB bit-band spaces. Each 32-bit location in the 32 MB space maps to an individual bit in the bit-band region. A 32-bit write in the alias region has the same effect as a read- modify-write operation on the targeted bit in the bit-band region. Bit 0 of the value written to the alias region determines what value is written to the target bit: System memory map K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 170 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 171

• Writing a value with bit 0 set writes a 1 to the target bit. • Writing a value with bit 0 clear writes a 0 to the target bit. A 32-bit read in the alias region returns either: • a value of 0x0000_0000 to indicate the target bit is clear • a value of 0x0000_0001 to indicate the target bit is set 31 0 0 31 Bit-band region Alias bit-band region 1 MByte 32 MByte Figure 4-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. 4.3 Flash Memory Map The various flash memories and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 171 General Business Information

Page 172

Program flash Flash configuration field Program flash base address Flash memory base address Registers RAM Programming acceleration RAM base address Figure 4-2. Flash memory map for devices containing only program flash Program flash Flash configuration field FlexNVM base address Program flash base address Flash memory base address Registers FlexNVM FlexRAM FlexRAM base address Figure 4-3. Flash memory map for devices containing FlexNVM 4.3.1 Alternate Non-Volatile IRC User Trim Description The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location. To override the factory trim, user software must load new values into the MCG trim registers. Non-Volatile Byte Address Alternate IRC Trim Value 0x0000_03FC Reserved 0x0000_03FD Reserved 0x0000_03FE (bit 0) SCFTRIM 0x0000_03FE (bit 4:1) FCTRIM 0x0000_03FF SCTRIM Flash Memory Map K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 172 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 173

4.4 SRAM memory map The on-chip RAM is split evenly among SRAM_L and SRAM_U. The RAM is also implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. See SRAM Arrays for details. Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. 4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps The peripheral memory map is accessible via two slave ports on the crossbar switch in the 0x4000_0000–0x400F_FFFF region. The device implements two peripheral bridges (AIPS-Lite 0 and 1): • AIPS-Lite0 covers 512 KB • AIPS-Lite1 covers 508 KB with 4 KB assigned to the general purpose input/output module (GPIO) AIPS-Lite0 is connected to crossbar switch slave port 2, and is accessible at locations 0x4000_0000–0x4007_FFFF. AIPS-Lite1 and the general purpose input/output module share the connection to crossbar switch slave port 3. The AIPS-Lite1 is accessible at locations 0x4008_0000– 0x400F_EFFF. The general purpose input/output module is accessible in a 4-kbyte region at 0x400F_F000–0x400F_FFFF. Its direct connection to the crossbar switch provides master access without incurring wait states associated with accesses via the AIPS-Lite controllers. Modules that are disabled via their clock gate control bits in the SIM registers disable the associated AIPS slots. Access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error termination. For programming model accesses via the peripheral bridges, there is generally only a small range within the 4 KB slots that is implemented. Accessing an address that is not implemented in the peripheral results in a transfer error termination. Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 173 General Business Information

Page 174

4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot number Module 0x4000_0000 0 Peripheral bridge 0 (AIPS-Lite 0) 0x4000_1000 1 — 0x4000_2000 2 — 0x4000_3000 3 — 0x4000_4000 4 Crossbar switch 0x4000_5000 5 — 0x4000_6000 6 — 0x4000_7000 7 — 0x4000_8000 8 DMA controller 0x4000_9000 9 DMA controller transfer control descriptors 0x4000_A000 10 — 0x4000_B000 11 — 0x4000_C000 12 FlexBus 0x4000_D000 13 MPU 0x4000_E000 14 — 0x4000_F000 15 — 0x4001_0000 16 — 0x4001_1000 17 — 0x4001_2000 18 — 0x4001_3000 19 — 0x4001_4000 20 — 0x4001_5000 21 — 0x4001_6000 22 — 0x4001_7000 23 — 0x4001_8000 24 — 0x4001_9000 25 — 0x4001_A000 26 — 0x4001_B000 27 — 0x4001_C000 28 — 0x4001_D000 29 — 0x4001_E000 30 — 0x4001_F000 31 Flash memory controller 0x4002_0000 32 Flash memory 0x4002_1000 33 DMA channel mutiplexer 0 0x4002_2000 34 — 0x4002_3000 35 — 0x4002_4000 36 FlexCAN 0 Table continues on the next page... Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 174 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 175

Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4002_5000 37 — 0x4002_6000 38 — 0x4002_7000 39 — 0x4002_8000 40 — 0x4002_9000 41 — 0x4002_A000 42 — 0x4002_B000 43 — 0x4002_C000 44 SPI 0 0x4002_D000 45 SPI 1 0x4002_E000 46 — 0x4002_F000 47 I2S 0 0x4003_0000 48 — 0x4003_1000 49 — 0x4003_2000 50 CRC 0x4003_3000 51 — 0x4003_4000 52 — 0x4003_5000 53 USB DCD 0x4003_6000 54 Programmable delay block (PDB) 0x4003_7000 55 Periodic interrupt timers (PIT) 0x4003_8000 56 FlexTimer (FTM) 0 0x4003_9000 57 FlexTimer (FTM) 1 0x4003_A000 58 — 0x4003_B000 59 Analog-to-digital converter (ADC) 0 0x4003_C000 60 — 0x4003_D000 61 Real-time clock (RTC) 0x4003_E000 62 VBAT register file 0x4003_F000 63 — 0x4004_0000 64 Low-power timer (LPTMR) 0x4004_1000 65 System register file 0x4004_2000 66 — 0x4004_3000 67 — 0x4004_4000 68 — 0x4004_5000 69 Touch sense interface (TSI) 0x4004_6000 70 — 0x4004_7000 71 SIM low-power logic 0x4004_8000 72 System integration module (SIM) 0x4004_9000 73 Port A multiplexing control 0x4004_A000 74 Port B multiplexing control 0x4004_B000 75 Port C multiplexing control Table continues on the next page... Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 175 General Business Information

Page 176

Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4004_C000 76 Port D multiplexing control 0x4004_D000 77 Port E multiplexing control 0x4004_E000 78 — 0x4004_F000 79 — 0x4005_0000 80 — 0x4005_1000 81 — 0x4005_2000 82 Software watchdog 0x4005_3000 83 — 0x4005_4000 84 — 0x4005_5000 85 — 0x4005_6000 86 — 0x4005_7000 87 — 0x4005_8000 88 — 0x4005_9000 89 — 0x4005_A000 90 — 0x4005_B000 91 — 0x4005_C000 92 — 0x4005_D000 93 — 0x4005_E000 94 — 0x4005_F000 95 — 0x4006_0000 96 — 0x4006_1000 97 External watchdog 0x4006_2000 98 Carrier modulator timer (CMT) 0x4006_3000 99 — 0x4006_4000 100 Multi-purpose Clock Generator (MCG) 0x4006_5000 101 System oscillator (OSC) 0x4006_6000 102 I2C 0 0x4006_7000 103 I2C 1 0x4006_8000 104 — 0x4006_9000 105 — 0x4006_A000 106 UART 0 0x4006_B000 107 UART 1 0x4006_C000 108 UART 2 0x4006_D000 109 UART 3 0x4006_E000 110 — 0x4006_F000 111 — 0x4007_0000 112 — 0x4007_1000 113 — 0x4007_2000 114 USB OTG FS/LS Table continues on the next page... Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 176 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 177

Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4007_3000 115 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 116 Voltage reference (VREF) 0x4007_5000 117 — 0x4007_6000 118 — 0x4007_7000 119 — 0x4007_8000 120 — 0x4007_9000 121 — 0x4007_A000 122 — 0x4007_B000 123 — 0x4007_C000 124 Low-leakage wakeup unit (LLWU) 0x4007_D000 125 Power management controller (PMC) 0x4007_E000 126 System Mode controller (SMC) 0x4007_F000 127 Reset Control Module (RCM) 4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map Table 4-3. Peripheral bridge 1 slot assignments System 32-bit base address Slot number Module 0x4008_0000 0 Peripheral bridge 1 (AIPS-Lite 1) 0x4008_1000 1 — 0x4008_2000 2 — 0x4008_3000 3 — 0x4008_4000 4 — 0x4008_5000 5 — 0x4008_6000 6 — 0x4008_7000 7 — 0x4008_8000 8 — 0x4008_9000 9 — 0x4008_A000 10 — 0x4008_B000 11 — 0x4008_C000 12 — 0x4008_D000 13 — 0x4008_E000 14 — 0x4008_F000 15 — 0x4009_0000 16 — 0x4009_1000 17 — Table continues on the next page... Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 177 General Business Information

Page 178

Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot number Module 0x4009_2000 18 — 0x4009_3000 19 — 0x4009_4000 20 — 0x4009_5000 21 — 0x4009_6000 22 — 0x4009_7000 23 — 0x4009_8000 24 — 0x4009_9000 25 — 0x4009_A000 26 — 0x4009_B000 27 — 0x4009_C000 28 — 0x4009_D000 29 — 0x4009_E000 30 — 0x4009_F000 31 — 0x400A_0000 32 Random number generator (RNGA) 0x400A_1000 33 — 0x400A_2000 34 — 0x400A_3000 35 — 0x400A_4000 36 FlexCAN 1 0x400A_5000 37 — 0x400A_6000 38 — 0x400A_7000 39 — 0x400A_8000 40 — 0x400A_9000 41 — 0x400A_A000 42 — 0x400A_B000 43 — 0x400A_C000 44 SPI 2 0x400A_D000 45 — 0x400A_E000 46 — 0x400A_F000 47 — 0x400B_0000 48 — 0x400B_1000 49 SDHC 0x400B_2000 50 — 0x400B_3000 51 — 0x400B_4000 52 — 0x400B_5000 53 — 0x400B_6000 54 — 0x400B_7000 55 — 0x400B_8000 56 FlexTimer (FTM) 2 Table continues on the next page... Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 178 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 179

Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot number Module 0x400B_9000 57 — 0x400B_A000 58 — 0x400B_B000 59 Analog-to-digital converter (ADC) 1 0x400B_C000 60 — 0x400B_D000 61 — 0x400B_E000 62 — 0x400B_F000 63 — 0x400C_0000 64 Ethernet MAC and IEEE 1588 timers 0x400C_1000 65 — 0x400C_2000 66 — 0x400C_3000 67 — 0x400C_4000 68 — 0x400C_5000 69 — 0x400C_6000 70 — 0x400C_7000 71 — 0x400C_8000 72 — 0x400C_9000 73 — 0x400C_A000 74 — 0x400C_B000 75 — 0x400C_C000 76 12-bit digital-to-analog converter (DAC) 0 0x400C_D000 77 12-bit digital-to-analog converter (DAC) 1 0x400C_E000 78 — 0x400C_F000 79 — 0x400D_0000 80 — 0x400D_1000 81 — 0x400D_2000 82 — 0x400D_3000 83 — 0x400D_4000 84 — 0x400D_5000 85 — 0x400D_6000 86 — 0x400D_7000 87 — 0x400D_8000 88 — 0x400D_9000 89 — 0x400D_A000 90 — 0x400D_B000 91 — 0x400D_C000 92 — 0x400D_D000 93 — 0x400D_E000 94 — 0x400D_F000 95 — Table continues on the next page... Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 179 General Business Information

Page 180

Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot number Module 0x400E_0000 96 — 0x400E_1000 97 — 0x400E_2000 98 — 0x400E_3000 99 — 0x400E_4000 100 — 0x400E_5000 101 — 0x400E_6000 102 — 0x400E_7000 103 — 0x400E_8000 104 — 0x400E_9000 105 — 0x400E_A000 106 UART 4 0x400E_B000 107 UART 5 0x400E_C000 108 — 0x400E_D000 109 — 0x400E_E000 110 — 0x400E_F000 111 — 0x400F_0000 112 — 0x400F_1000 113 — 0x400F_2000 114 — 0x400F_3000 115 — 0x400F_4000 116 — 0x400F_5000 117 — 0x400F_6000 118 — 0x400F_7000 119 — 0x400F_8000 120 — 0x400F_9000 121 — 0x400F_A000 122 — 0x400F_B000 123 — 0x400F_C000 124 — 0x400F_D000 125 — 0x400F_E000 126 — 0x400F_F000 Not an AIPS-Lite slot. The 32-bit general purpose input/output module that shares the crossbar switch slave port with the AIPS-Lite is accessed at this address. Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 180 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 181

4.6 Private Peripheral Bus (PPB) memory map The PPB is part of the defined ARM bus architecture and provides access to select processor-local modules. These resources are only accessible from the core; other system masters do not have access to them. Table 4-4. PPB memory map System 32-bit Address Range Resource 0xE000_0000–0xE000_0FFF Instrumentation Trace Macrocell (ITM) 0xE000_1000–0xE000_1FFF Data Watchpoint and Trace (DWT) 0xE000_2000–0xE000_2FFF Flash Patch and Breakpoint (FPB) 0xE000_3000–0xE000_DFFF Reserved 0xE000_E000–0xE000_EFFF System Control Space (SCS) (for NVIC) 0xE000_F000–0xE003_FFFF Reserved 0xE004_0000–0xE004_0FFF Trace Port Interface Unit (TPIU) 0xE004_1000–0xE004_1FFF Embedded Trace Macrocell (ETM) 0xE004_2000–0xE004_2FFF Embedded Trace Buffer (ETB) 0xE004_3000–0xE004_3FFF Embedded Trace Funnel 0xE004_4000–0xE007_FFFF Reserved 0xE008_0000–0xE008_0FFF Miscellaneous Control Module (MCM)(including ETB Almost Full) 0xE008_1000–0xE008_1FFF Memory Mapped Cryptographic Acceleration Unit (MMCAU) 0xE008_2000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF ROM Table - allows auto-detection of debug components Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 181 General Business Information

Page 182

Private Peripheral Bus (PPB) memory map K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 182 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 183

Chapter 5 Clock Distribution 5.1 Introduction The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory. The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. The primary clocks for the system are generated from the MCGOUTCLK clock. The clock generation circuitry provides several clock dividers that allow different portions of the device to be clocked at different frequencies. This allows for trade-offs between performance and power dissipation. Various modules, such as the USB OTG Controller, have module-specific clocks that can be generated from the MCGPLLCLK or MCGFLLCLK clock. In addition, there are various other module-specific clocks that have other alternate sources. Clock selection for most modules is controlled by the SOPT registers in the SIM module. 5.2 Programming model The selection and multiplexing of system clock sources is controlled and programmed via the MCG module. The setting of clock dividers and module clock gating for the system are programmed via the SIM module. Reference those sections for detailed register and bit descriptions. 5.3 High-Level device clocking diagram The following system oscillator, MCG, and SIM module registers control the multiplexers, dividers, and clock gates shown in the below figure: K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 183 General Business Information

Page 184

OSC MCG SIM Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers — MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx 32 kHz IRC PLL FLL MCGOUTCLK MCGPLLCLK MCG MCGFLLCLK OUTDIV1 Core / system clocks 4 MHz IRC OUTDIV4 Flash clock OUTDIV2 Bus clock RTC oscillator EXTAL32 XTAL32 EXTAL0 XTAL0 System oscillator SIM FRDIV MCGIRCLK ERCLK32K OSC32KCLK XTAL_CLK MCGFFCLK OSCERCLK OSC logic OSC logic Clock options for some peripherals (see note) MCGFLLCLK MCGPLLCLK/ Note: See subsequent sections for details on where these clocks are used. PMC logic PMC LPO OSCCLK CG CG CG CG CG CG — Clock gate RTC clock Clock options for some peripherals (see note) FCRDIV OUTDIV3 FlexBus clock CG Figure 5-1. Clocking diagram 5.4 Clock definitions The following table describes the clocks in the previous block diagram. Clock name Description Core clock MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex- M4 core Table continues on the next page... Clock definitions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 184 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 185

Clock name Description System clock MCGOUTCLK divided by OUTDIV1 clocks the crossbar switch and bus masters directly connected to the crossbar. In addition, this clock is used for UART0 and UART1. Bus clock MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding memories) FlexBus clock MCGOUTCLK divided by OUTDIV3 clocks the external FlexBus interface Flash clock MCGOUTCLK divided by OUTDIV4 clocks the flash memory MCGIRCLK MCG output of the slow or fast internal reference clock MCGFFCLK MCG output of the slow internal reference clock or a divided MCG external reference clock. MCGOUTCLK MCG output of either IRC, MCGFLLCLK, MCGPLLCLK, or MCG's external reference clock that sources the core, system, bus, FlexBus, and flash clock. It is also an option for the debug trace clock. MCGFLLCLK MCG output of the FLL. MCGFLLCLK or MCGPLLCLK may clock some modules. MCGPLLCLK MCG output of the PLL. MCGFLLCLK or MCGPLLCLK may clock some modules. MCG external reference clock Input clock to the MCG sourced by the system oscillator (OSCCLK) or RTC oscillator OSCCLK System oscillator output of the internal oscillator or sourced directly from EXTAL OSCERCLK System oscillator output sourced from OSCCLKthat may clock some on-chip modules OSC32KCLK System oscillator 32kHz output ERCLK32K Clock source for some modules that is chosen as OSC32KCLK or the RTC clock. It is VLPOSCCLK for TSI. RTC clock RTC oscillator output for the RTC module LPO PMC 1kHz output 5.4.1 Device clock summary The following table provides more information regarding the on-chip clocks. Table 5-1. Clock Summary Clock name Run mode clock frequency VLPR mode clock frequency Clock source Clock is disabled when… MCGOUTCLK Up to 100 MHz Up to 4 MHz MCG In all stop modes Core clock Up to 100 MHz Up to 4 MHz MCGOUTCLK clock divider In all wait and stop modes System clock Up to 100 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes Table continues on the next page... Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 185 General Business Information

Page 186

Table 5-1. Clock Summary (continued) Clock name Run mode clock frequency VLPR mode clock frequency Clock source Clock is disabled when… Bus clock Up to 50 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes FlexBus clock (FB_CLK) Up to 50 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes or FlexBus disabled Flash clock Up to 25 MHz Up to 1 MHz in BLPE, Up to 800 kHz in BLPI MCGOUTCLK clock divider In all stop modes Internal reference (MCGIRCLK) 30-40 kHz or 4 MHz 4 MHz only MCG MCG_C1[IRCLKEN] cleared, Stop mode and MCG_C1[IREFSTEN] cleared, or VLPS/LLS/VLLS mode External reference (OSCERCLK) Up to 50 MHz (bypass), 30-40 kHz, or 3-32 MHz (crystal) Up to 16 MHz (bypass), 30-40 kHz (low-range crystal) or Up to 4 MHz (high- range crystal) System OSC System OSC's OSC_CR[ERCLKEN] cleared, or Stop mode and OSC_CR[EREFSTEN] cleared External reference 32kHz (ERCLK32K) 30-40 kHz 30-40 kHz System OSC or RTC OSC depending on SIM_SOPT1[OSC32KS EL] System OSC's OSC_CR[ERCLKEN] cleared or RTC's RTC_CR[OSCE] cleared RTC_CLKOUT 1 Hz or 32 kHz 1 Hz or 32 kHz RTC clock Clock is disabled in LLS and VLLSx modes LPO 1 kHz 1 kHz PMC Available in all power modes USB FS clock 48 MHz N/A MCGPLLCLK or MCGFLLCLK with fractional clock divider, or USB_CLKIN USB FS OTG is disabled I2S master clock Up to 25 MHz Up to 12.5 MHz System clock, MCGPLLCLK, OSCERCLK with fractional clock divider, or I2S_CLKIN I2S is disabled SDHC clock Up to 50 MHz N/A System clock, MCGPLLCLK/ MCGFLLCLK, or OSCERCLK SDHC is disabled Ethernet RMII clock 50 MHz N/A OSCERCLK Ethernet is disabled Table continues on the next page... Clock definitions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 186 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 187

Table 5-1. Clock Summary (continued) Clock name Run mode clock frequency VLPR mode clock frequency Clock source Clock is disabled when… Ethernet IEEE 1588 clock Up to 100 MHz N/A System clock, OSCERCLK, MCGPLLCLK/ MCGFLLCLK, or ENET_1588_CLKIN Ethernet is disabled TRACE clock Up to 100 MHz Up to 4 MHz System clock or MCGOUTCLK Trace is disabled 5.5 Internal clocking requirements The clock dividers are programmed via the SIM module’s CLKDIV registers. Each divider is programmable from a divide-by-1 through divide-by-16 setting. The following requirements must be met when configuring the clocks for this device:

The core and system clock frequencies must be 100 MHz or slower.
The bus clock frequency must be programmed to 50 MHz or less and an integer divide of the core clock.
The flash clock frequency must be programmed to 25 MHz or less, less than or equal to the bus clock, and an integer divide of the core clock.
The FlexBus clock frequency must be programmed to be less than or equal to the bus clock frequency. The following are a few of the more common clock configurations for this device: Option 1: Clock Frequency Core clock 50 MHz System clock 50 MHz Bus clock 50 MHz FlexBus clock 50 MHz Flash clock 25 MHz Option 2: Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 187 General Business Information

Page 188

Clock Frequency Core clock 100 MHz System clock 100 MHz Bus clock 50 MHz FlexBus clock 25 MHz Flash clock 25 MHz Option 3: Clock Frequency Core clock 96 MHz System clock 96 MHz Bus clock 48 MHz FlexBus clock 48 MHz Flash clock 24 MHz 5.5.1 Clock divider values after reset Each clock divider is programmed via the SIM module’s CLKDIVn registers. The flash memory's FTFL_FOPT[LPBOOT] bit controls the reset value of the core clock, system clock, bus clock, and flash clock dividers as shown below: FTFL_FOPT [LPBOOT] Core/system clock Bus clock FlexBus clock Flash clock Description 0 0x7 (divide by 8) 0x7 (divide by 8) 0xF (divide by 16) 0xF (divide by 16) Low power boot 1 0x0 (divide by 1) 0x0 (divide by 1) 0x1 (divide by 2) 0x1 (divide by 2) Fast clock boot This gives the user flexibility for a lower frequency, low-power boot option. The flash erased state defaults to fast clocking mode, since where the low power boot (FTFL_FOPT[LPBOOT]) bit resides in flash is logic 1 in the flash erased state. To enable the low power boot option program FTFL_FOPT[LPBOOT] to zero. During the reset sequence, if LPBOOT is cleared, the system is in a slow clock configuration. Upon any system reset, the clock dividers return to this configurable reset state. 5.5.2 VLPR mode clocking The clock dividers cannot be changed while in VLPR mode. They must be programmed prior to entering VLPR mode to guarantee: Internal clocking requirements K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 188 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 189

• the core/system, FlexBus, and bus clocks are less than or equal to 4 MHz, and • the flash memory clock is less than or equal to 1 MHz NOTE When the MCG is in BLPI and clocking is derived from the Fast IRC, the clock divider controls, MCG_SC[FCRDIV] and SIM_CLKDIV1[OUTDIV4], must be programmed such that the resulting flash clock nominal frequency is 800 kHz or less. In this case, one example of correct configuration is MCG_SC[FCRDIV]=000b and SIM_CLKDIV1[OUTDIV4]=0100b, resulting in a divide by 5 setting. 5.6 Clock Gating The clock to each module can be individually gated on and off using the SIM module's SCGCx registers. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing a module, set the corresponding bit in SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. Any bus access to a peripheral that has its clock disabled generates an error termination. 5.7 Module clocks The following table summarizes the clocks associated with each module. Table 5-2. Module clocks Module Bus interface clock Internal clocks I/O interface clocks Core modules ARM Cortex-M4 core System clock Core clock — NVIC System clock — — DAP System clock — — ITM System clock — — ETM System clock TRACE clock TRACE_CLKOUT ETB System clock — — cJTAG, JTAGC — — JTAG_CLK System modules DMA System clock — — Table continues on the next page... Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 189 General Business Information

Page 190

Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks DMA Mux Bus clock — — Port control Bus clock LPO — Crossbar Switch System clock — — Peripheral bridges System clock Bus clock, Flash clock — MPU System clock — — LLWU, PMC, SIM, RCM Flash clock LPO — Mode controller Flash clock — — MCM System clock — — EWM Bus clock LPO — Watchdog timer Bus clock LPO — Clocks MCG Bus clock MCGOUTCLK, MCGPLLCLK, MCGFLLCLK, MCGIRCLK, OSCERCLK, EXTAL32K — OSC Bus clock OSCERCLK — Memory and memory interfaces Flash Controller System clock Flash clock — Flash memory Flash clock — — FlexBus System clock — CLKOUT EzPort System clock — EZP_CLK Security CRC Bus clock — — MMCAU System clock — — RNGA Bus clock — — Analog ADC Bus clock OSCERCLK — CMP Bus clock — — DAC Bus clock — — VREF Bus clock — — Timers PDB Bus clock — — FlexTimers Bus clock MCGFFCLK FTM_CLKINx PIT Bus clock — — LPTMR Flash clock LPO, OSCERCLK, MCGIRCLK, ERCLK32K — CMT Bus clock — — RTC Flash clock EXTAL32 — Communication interfaces Ethernet System clock, Bus clock RMII clock, IEEE 1588 clock MII_RXCLK, MII_TXCLK USB FS OTG System clock USB FS clock — Table continues on the next page... Module clocks K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 190 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 191

Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks USB DCD Bus clock — — FlexCAN Bus clock OSCERCLK — DSPI Bus clock — DSPI_SCK I2C Bus clock — I2C_SCL UART0, UART1 System clock — — UART2-5 Bus clock — — SDHC System clock SDHC clock SDHC_DCLK I2S Bus clock I2S master clock I2S_TX_BCLK, I2S_RX_BCLK Human-machine interfaces GPIO System clock — — TSI Flash clock LPO, ERCLK32K, MCGIRCLK — 5.7.1 PMC 1-kHz LPO clock The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low power modes. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock. 5.7.2 WDOG clocking The WDOG may be clocked from two clock sources as shown in the following figure. WDOG_STCTRLH[CLKSRC] WDOG clock Bus clock LPO Figure 5-2. WDOG clock generation Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 191 General Business Information

Page 192

5.7.3 Debug trace clock The debug trace clock source can be clocked as shown in the following figure. SIM_SOPT2[TRACECLKSEL] TRACECLKIN Core / system clock MCGOUTCLK TPIU ÷2 TRACE_CLKOUT Figure 5-3. Trace clock generation NOTE The trace clock frequency observed at the TRACE_CLKOUT pin will be half that of the selected clock source. 5.7.4 PORT digital filter clocking The digital filters in each of the PORTx modules can be clocked as shown in the following figure. NOTE In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source. PORTx_DFCR[CS] PORTx digital input filter clock Bus clock LPO Figure 5-4. PORTx digital input filter clock generation Module clocks K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 192 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 193

5.7.5 LPTMR clocking The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. LPTMRx_PSR[PCS] LPTMRx prescaler/glitch filter clock MCGIRCLK OSCERCLK ERCLK32K LPO Figure 5-5. LPTMRx prescaler/glitch filter clock generation 5.7.6 Ethernet Clocking • The RMII clock source is fixed to OSCERCLK and must be 50 MHz • The MII clocks are supplied from pins and must be 25 MHz • The IEEE 1588 timestamp clock can run up to 100 MHz, if generated from internal clock sources. Its period must be an integer number of nanoseconds (eg: 10ns = 100 MHz, 15ns = 66.67 MHz, 20ns = 50 MHz). Its clock source is chosen as shown in the following figure. Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 193 General Business Information

Page 194

Core / System clock OSCERCLK MCGPLLCLK or MCGFLLCLK ENET_1588_CLKIN SIM_SOPT2[TIMESRC] Ethernet IEEE 1588 timestamp clock Figure 5-6. Ethernet IEEE1588 timestamp clock generation 5.7.7 USB FS OTG Controller clocking The USB FS OTG controller is a bus master attached to the crossbar switch. As such, its clock is connected to the system clock. NOTE For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz. The USB OTG controller also requires a 48 MHz clock. The clock source options are shown below. USB 48MHz USB_CLKIN MCGPLLCLK or MCGFLLCLK SIM_CLKDIV2 [USBFRAC, USBDIV] SIM_SOPT2[USBSRC] Figure 5-7. USB 48 MHz clock source NOTE The MCGFLLCLK does not meet the USB jitter specifications for certification. Module clocks K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 194 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 195

5.7.8 FlexCAN clocking The clock for the FlexCAN's protocol engine can be selected as shown in the following figure. CANx_CTRL1[CLKSRC] FlexCAN clock Bus clock OSCERCLK Figure 5-8. FlexCAN clock generation 5.7.9 UART clocking UART0 and UART1 modules operate from the core/system clock, which provides higher performance level for these modules. All other UART modules operate from the bus clock. 5.7.10 SDHC clocking The SDHC module has four possible clock sources for the external clock source, as shown in the following figure. SIM_SOPT2[SDHCSRC] SDHC clock MCGPLLCLK or MCGFLLCLK Core / system clock OSCERCLK SDHC0_CLKIN Figure 5-9. SDHC clock generation Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 195 General Business Information

Page 196

5.7.11 I2S/SAI clocking The audio master clock (MCLK) is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The audio master clock can also be output to or input from a pin. The transmitter and receiver have the same audio master clock inputs. Each SAI peripheral can control the input clock selection, pin direction and divide ratio of one audio master clock. The I2S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. The module also supports the option for synchronous operation between the receiver and transmitterproduct. The transmitter and receiver can independently select between the bus clock and the audio master clock to generate the bit clock. The MCLK and BCLK source options appear in the following figure. Fractional Clock Divider 1 0 11 01 10 00 OSC0ERCLK MCGPLLCLK SYSCLK I2Sx_MCR[MOE] MCLK MCLK_OUT MCLK_IN 11 01 10 00 BUSCLK [MSEL] Bit Clock Divider 1 0 BCLK_IN I2S/SAI BCLK_OUT [BCD] BCLK I2Sx_MDR[FRACT,DIVIDE] I2Sx_MCR[MICS] Clock Generation [DIV] I2Sx_TCR2/RCR2 Figure 5-10. I2S/SAI clock generation 5.7.12 TSI clocking In active mode, the TSI can be clocked as shown in the following figure. Module clocks K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 196 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 197

TSI_SCANC[AMCLKS] TSI clock in active mode Bus clock MCGIRCLK OSCERCLK Figure 5-11. TSI clock generation In low-power mode, the TSI can be clocked as shown in the following figure. NOTE In the TSI chapter, these two clocks are referred to as LPOCLK and VLPOSCCLK. TSI_GENCS[LPCLKS] TSI clock in low-power mode LPO ERCLK32K Figure 5-12. TSI low-power clock generation Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 197 General Business Information

Page 198

Module clocks K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 198 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 199

Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1. Reset sources Reset sources Description POR reset • Power-on reset (POR) System resets • External pin reset (PIN) • Low-voltage detect (LVD) • Computer operating properly (COP) watchdog reset • Low leakage wakeup (LLWU) reset • Multipurpose clock generator loss of clock (LOC) reset • Multipurpose clock generator loss of lock (LOL) reset • Stop mode acknowledge error (SACKERR) • Software reset (SW) • Lockup reset (LOCKUP) • EzPort reset • MDM DAP system reset Debug reset • JTAG reset • nTRST reset Each of the system reset sources has an associated bit in the system reset status (SRS) registers. See the Reset Control Module for register details. The MCU exits reset in functional mode that is controlled by EZP_CS pin to select between the single chip (default) or serial flash programming (EzPort) modes. See Boot options for more details. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 199 General Business Information

Page 200

6.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (VPOR), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (VLVDL). The POR and LVD bits in SRS0 register are set following a POR. 6.2.2 System reset sources Resetting the MCU provides a way to start processing from a known set of initial conditions. System reset begins with the on-chip regulator in full regulation and system clocking generation from an internal reference. When the processor exits reset, it performs the following: • Reads the start SP (SP_main) from vector-table offset 0 • Reads the start PC from vector-table offset 4 • LR is set to 0xFFFF_FFFF The on-chip peripheral modules are disabled and the non-analog I/O pins are initially configured as disabled. The pins with analog functions assigned to them default to their analog function after reset. During and following a reset, the JTAG pins have their associated input pins configured as: • TDI in pull-up (PU) • TCK in pull-down (PD) • TMS in PU and associated output pin configured as: • TDO with no pull-down or pull-up Reset K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 200 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 201

Note that the nTRST signal is initially configured as disabled, however once configured to its JTAG functionality its associated input pin is configured as: • nTRST in PU 6.2.2.1 External pin reset (PIN) On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the RCM's SRS0[PIN] bit is set. 6.2.2.1.1 Reset pin filter The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus clock. A separate filter is implemented for each clock source. In stop and VLPS mode operation, this logic either switches to bypass operation or has continued filtering operation depending on the filtering mode selected. In low leakage stop modes, a separate LPO filter in the LLWU can continue filtering the RESET pin. The RPFC[RSTFLTSS], RPFC[RSTFLTSRW], and RPFW[RSTFLTSEL] fields in the reset control (RCM) register set control this functionality; see the RCM chapter. The filters are asynchronously reset by Chip POR. The reset value for each filter assumes the RESET pin is negated. The two clock options for the RESET pin filter when the chip is not in low leakage modes are the LPO (1 kHz) and bus clock. For low leakage modes VLLS3, VLLS2, VLLS1, the LLWU provides control (in the LLWU_RST register) of an optional fixed digital filter running the LPO. The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a transition from low to high or high to low. The bus filter initializes to off (logic 1) when the bus filter is not enabled. The bus clock is used when the filter selects bus clock, and the number of counts is controlled by the RCM's RPFW[RSTFLTSEL] field. Chapter 6 Reset and Boot K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 201 General Business Information

Page 202

6.2.2.2 Low-voltage detect (LVD) The chip includes a system for managing low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip voltage. The LVD system is always enabled in normal run, wait, or stop mode. The LVD system is disabled when entering VLPx, LLS, or VLLSx modes. The LVD can be configured to generate a reset upon detection of a low voltage condition by setting the PMC's LVDSC1[LVDRE] bit to 1. The low voltage detection threshold is determined by the PMC's LVDSC1[LVDV] field. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage has risen above the low voltage detection threshold. The RCM's SRS0[LVD] bit is set following either an LVD reset or POR. 6.2.2.3 Computer operating properly (COP) watchdog timer The computer operating properly (COP) watchdog timer (WDOG) monitors the operation of the system by expecting periodic communication from the software. This communication is generally known as servicing (or refreshing) the COP watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset. The COP reset causes the RCM's SRS0[WDOG] bit to set. 6.2.2.4 Low leakage wakeup (LLWU) The LLWU module provides the means for a number of external pins, the RESET pin, and a number of internal peripherals to wake the MCU from low leakage power modes. The LLWU module is functional only in low leakage power modes. • In LLS mode, only the RESET pin via the LLWU can generate a system reset. • In VLLSx modes, all enabled inputs to the LLWU can generate a system reset. After a system reset, the LLWU retains the flags indicating the input source of the last wakeup until the user clears them. NOTE Some flags are cleared in the LLWU and some flags are required to be cleared in the peripheral module. Refer to the individual peripheral chapters for more information. Reset K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 202 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 203

6.2.2.5 Multipurpose clock generator loss-of-clock (LOC) The MCG module supports an external reference clock. If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If the external reference falls below floc_low or floc_high, as controlled by the C2[RANGE] field in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source. NOTE To prevent unexpected loss of clock reset events, all clock monitors should be disabled before entering any low power modes, including VLPR and VLPW. 6.2.2.6 MCG loss-of-lock (LOL) reset The MCG includes a PLL loss-of-lock detector. The detector is enabled when configured for PEE and lock has been achieved. If the MCG_C8[LOLRE] bit in the MCG module is set and the PLL lock status bit (MCG_S[LOLS0]) becomes set, the MCU resets. The RCM_SRS0[LOL] bit is set to indicate this reset source. NOTE This reset source does not cause a reset if the chip is in any stop mode. 6.2.2.7 Stop mode acknowledge error (SACKERR) This reset is generated if the core attempts to enter stop mode, but not all modules acknowledge stop mode within 1025 cycles of the 1 kHz LPO clock. A module might not acknowledge the entry to stop mode if an error condition occurs. The error can be caused by a failure of an external clock input to a module. 6.2.2.8 Software reset (SW) The SYSRESETREQ bit in the NVIC application interrupt and reset control register can be set to force a software reset on the device. (See ARM's NVIC documentation for the full description of the register fields, especially the VECTKEY field requirements.) Setting SYSRESETREQ generates a software reset request. This reset forces a system reset of all major components except for the debug module. A software reset causes the RCM's SRS1[SW] bit to set. Chapter 6 Reset and Boot K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 203 General Business Information

Page 204

6.2.2.9 Lockup reset (LOCKUP) The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. The LOCKUP condition causes a system reset and also causes the RCM's SRS1[LOCKUP] bit to set. 6.2.2.10 EzPort reset The EzPort supports a system reset request via EzPort signaling. The EzPort generates a system reset request following execution of a Reset Chip (RESET) command via the EzPort interface. This method of reset allows the chip to boot from flash memory after it has been programmed by an external source. The EzPort is enabled or disabled by the EZP_CS pin. An EzPort reset causes the RCM's SRS1[EZPT] bit to set. 6.2.2.11 MDM-AP system reset request Set the system reset request bit in the MDM-AP control register to initiate a system reset. This is the primary method for resets via the JTAG/SWD interface. The system reset is held until this bit is cleared. Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset. 6.2.3 MCU Resets A variety of resets are generated by the MCU to reset different modules. 6.2.3.1 VBAT POR The VBAT POR asserts on a VBAT POR reset source. It affects only the modules within the VBAT power domain: RTC and VBAT Register File. These modules are not affected by the other reset types. Reset K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 204 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 205

6.2.3.2 POR Only The POR Only reset asserts on the POR reset source only. It resets the PMC and System Register File. The POR Only reset also causes all other reset types (except VBAT POR) to occur. 6.2.3.3 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of the SMC and SIM. It also resets the LPTMR. The Chip POR not VLLS reset also causes these resets to occur: Chip POR, Chip Reset not VLLS, and Chip Reset (including Early Chip Reset). 6.2.3.4 Chip POR The Chip POR asserts on POR, LVD, and VLLS Wakeup reset sources. It resets the Reset Pin Filter registers and parts of the SIM and MCG. The Chip POR also causes the Chip Reset (including Early Chip Reset) to occur. 6.2.3.5 Chip Reset not VLLS The Chip Reset not VLLS reset asserts on all reset sources except a VLLS Wakeup that does not occur via the RESET pin. It resets parts of the SMC, LLWU, and other modules that remain powered during VLLS mode. The Chip Reset not VLLS reset also causes the Chip Reset (including Early Chip Reset) to occur. 6.2.3.6 Early Chip Reset The Early Chip Reset asserts on all reset sources. It resets only the flash memory module. It negates before flash memory initialization begins ("earlier" than when the Chip Reset negates). Chapter 6 Reset and Boot K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 205 General Business Information

Page 206

6.2.3.7 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET pin has also negated. It resets the remaining modules (the modules not reset by other reset types). 6.2.4 Reset Pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed. After flash initialization has completed, the RESET pin is released, and the internal Chip Reset negates after the RESET pin is pulled high. Keeping the RESET pin asserted externally delays the negation of the internal Chip Reset. 6.2.5 Debug resets The following sections detail the debug resets available on the device. 6.2.5.1 JTAG reset The JTAG module generate a system reset when certain IR codes are selected. This functional reset is asserted when EzPort, EXTEST, HIGHZ and CLAMP instructions are active. The reset source from the JTAG module is released when any other IR code is selected. A JTAG reset causes the RCM's SRS1[JTAG] bit to set. 6.2.5.2 nTRST reset The nTRST pin causes a reset of the JTAG logic when asserted. Asserting the nTRST pin allows the debugger to gain control of the TAP controller state machine (after exiting LLS or VLLSx) without resetting the state of the debug modules. The nTRST pin does not cause a system reset. Reset K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 206 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 207

6.2.5.3 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers. CDBGRSTREQ resets the debug-related registers within the following modules: • SWJ-DP • AHB-AP • ETM • ATB replicators • ATB upsizers • ATB funnels • ETB • TPIU • MDM-AP (MDM control and status registers) • MCM (ETB “Almost Full” logic) CDBGRSTREQ does not reset the debug-related registers within the following modules: • CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR) • FPB • DWT • ITM • NVIC • Crossbar bus switch1 • AHB-AP1 • Private peripheral bus1 6.3 Boot This section describes the boot sequence, including sources and options. 6.3.1 Boot sources This device only supports booting from internal flash. Any secondary boot must go through an initialization sequence in flash. 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. Chapter 6 Reset and Boot K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 207 General Business Information

Page 208

6.3.2 Boot options The device's functional mode is controlled by the state of the EzPort chip select (EZP_CS) pin during reset. The device can be in single chip (default) or serial flash programming mode (EzPort). While in single chip mode the device can be in run or various low power modes mentioned in Power mode transitions. Table 6-2. Mode select decoding EzPort chip select (EZP_CS) Description 0 Serial flash programming mode (EzPort) 1 Single chip (default) 6.3.3 FOPT boot options The flash option register (FOPT) in flash memory module (FTFL) allows the user to customize the operation of the MCU at boot time. The register contains read-only bits that are loaded from the NVM's option byte in the flash configuration field. The user can reprogram the option byte in flash to change the FOPT values that are used for subsequent resets. For more details on programming the option byte, refer to the flash memory chapter. The MCU uses the FTFL_FOPT register bits to configure the device at reset as shown in the following table. Table 6-3. Flash Option Register (FTFL_FOPT) Bit Definitions Bit Num Field Value Definition 7-3 Reserved Reserved for future expansion. 2 NMI_DIS 0 NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. 1 NMI pin/interrupts reset default to enabled. 1 EZPORT_DIS 0 EzPort operation is disabled. The device always boots to normal CPU execution and the state of EZP_CS signal during reset is ignored. This option avoids inadvertent resets into EzPort mode if the EZP_CS/NMI pin is used for its NMI function. 1 EzPort operation is enabled. The state of EZP_CS pin during reset determines if device enters EzPort mode. Table continues on the next page... Boot K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 208 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 209

Table 6-3. Flash Option Register (FTFL_FOPT) Bit Definitions (continued) Bit Num Field Value Definition 0 LPBOOT 0 Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at reset exit for higher divide values that produce lower power consumption at reset exit. • Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2) are 0x7 (divide by 8) • Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are 0xF (divide by 16) 1 Normal boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at reset exit for higher frequency values that produce faster operating frequencies at reset exit. • Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2) are 0x0 (divide by 1) • Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are 0x1 (divide by 2) 6.3.4 Boot sequence At power up, the on-chip regulator holds the system in a POR state until the input supply is above the POR threshold. The system continues to be held in this static state until the internally regulated supplies have reached a safe operating voltage as determined by the LVD. The Mode Controller reset logic then controls a sequence to exit reset.

A system reset is held on internal logic, the RESET pin is driven out low, and the MCG is enabled in its default clocking mode.
Required clocks are enabled (Core Clock, System Clock, Flash Clock, and any Bus Clocks that do not have clock gate control).
The system reset on internal logic continues to be held, but the Flash Controller is released from reset and begins initialization operation while the Mode Control logic continues to drive the RESET pin out low for a count of ~128 Bus Clock cycles.
The RESET pin is released, but the system reset of internal logic continues to be held until the Flash Controller finishes initialization. EzPort mode is selected instead of the normal CPU execution if EZP_CS is low when the internal reset is deasserted. EzPort mode can be disabled by programming the FOPT[EZPORT_DIS] field in the Flash Memory module.
When Flash Initialization completes, the RESET pin is observed. If RESET continues to be asserted (an indication of a slow rise time on the RESET pin or external drive in low), the system continues to be held in reset. Once the RESET pin is detected high, the system is released from reset. Chapter 6 Reset and Boot K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 209 General Business Information

Page 210

At release of system reset, clocking is switched to a slow clock if the FOPT[LPBOOT] field in the Flash Memory module is configured for Low Power Boot
When the system exits reset, the processor sets up the stack, program counter (PC), and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to 0xFFFF_FFFF. The CPU begins execution at the PC location. EzPort mode is entered instead of the normal CPU execution if Ezport mode was latched during the sequence.
If FlexNVM is enabled, the flash controller continues to restore the FlexNVM data. This data is not available immediately out of reset and the system should not access this data until the flash controller completes this initialization step as indicated by the EEERDY flag. Subsequent system resets follow this reset flow beginning with the step where system clocks are enabled. Boot K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 210 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 211

Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Power modes The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The following table compares the various power modes available. For each run mode there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode. The very low power run (VLPR) operating mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs. The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the chip. The primary modes are augmented in a number of ways to provide lower power based on application needs. Table 7-1. Chip power modes Chip mode Description Core mode Normal recovery method Normal run Allows maximum performance of chip. Default mode out of reset; on- chip voltage regulator is on. Run

Table continues on the next page... K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 211 General Business Information

Page 212

Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method Normal Wait - via WFI Allows peripherals to function while the core is in sleep mode, reducing power. NVIC remains sensitive to interrupts; peripherals continue to be clocked. Sleep Interrupt Normal Stop - via WFI Places chip in static state. Lowest power mode that retains all registers while maintaining LVD protection. NVIC is disabled; AWIC is used to wake up from interrupt; peripheral clocks are stopped. Sleep Deep Interrupt VLPR (Very Low Power Run) On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. Reduced frequency Flash access mode (1 MHz); LVD off; internal oscillator provides a low power 4 MHz source for the core, the bus and the peripheral clocks. Run Interrupt VLPW (Very Low Power Wait) -via WFI Same as VLPR but with the core in sleep mode to further reduce power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. Sleep Interrupt VLPS (Very Low Power Stop)-via WFI Places chip in static state with LVD operation off. Lowest power mode with ADC and pin interrupts functional. Peripheral clocks are stopped, but LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled (FCLK = OFF); AWIC is used to wake up from interrupt. On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. All SRAM is operating (content retained and I/O states held). Sleep Deep Interrupt LLS (Low Leakage Stop) State retention power mode. Most peripherals are in state retention mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU is used to wake up. NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. All SRAM is operating (content retained and I/O states held). Sleep Deep Wakeup Interrupt1 VLLS3 (Very Low Leakage Stop3) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU is used to wake up. SRAM_U and SRAM_L remain powered on (content retained and I/O states held). Sleep Deep Wakeup Reset2 VLLS2 (Very Low Leakage Stop2) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU is used to wake up. SRAM_L is powered off. A portion of SRAM_U remains powered on (content retained and I/O states held). Sleep Deep Wakeup Reset2 VLLS1 (Very Low Leakage Stop1) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU is used to wake up. All of SRAM_U and SRAM_L are powered off. The 32-byte system register file and the 32-byte VBAT register file remain powered for customer-critical data. Sleep Deep Wakeup Reset2 Table continues on the next page... Power modes K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 212 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 213

Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method BAT (backup battery only) The chip is powered down except for the VBAT supply. The RTC and the 32-byte VBAT register file for customer-critical data remain powered. Off Power-up Sequence 1. Resumes normal run mode operation by executing the LLWU interrupt service routine. 2. Follows the reset flow with the LLWU interrupt flag set for the NVIC. 7.3 Entering and exiting power modes The WFI instruction invokes wait and stop modes for the chip. The processor exits the low-power mode via an interrupt. The Nested Vectored Interrupt Controller (NVIC) describes interrupt operation and what peripherals can cause interrupts. NOTE The WFE instruction can have the side effect of entering a low- power mode, but that is not its intended usage. See ARM documentation for more on the WFE instruction. Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU inputs" in the LLWU configuration section for a list of the sources. The wake-up flow from VLLSx is through reset. The wakeup bit in the SRS registers in the RCM is set indicating that the chip is recovering from a low power mode. Code execution begins; however, the I/O pins are held in their pre low power mode entry states, and the system oscillator and MCG registers are reset (even if EREFSTEN had been set before entering VLLSx). Software must clear this hold by writing a 1 to the ACKISO bit in the Regulator Status and Control Register in the PMC module. NOTE To avoid unwanted transitions on the pins, software must re- initialize the I/O pins to their pre-low-power mode entry states before releasing the hold. If the oscillator was configured to continue running during VLLSx modes, it must be re- configured before the ACKISO bit is cleared. The oscillator configuration within the MCG is cleared after VLLSx recovery and the oscillator will stop when ACKISO is cleared unless the register is re-configured. Chapter 7 Power Management K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 213 General Business Information

Page 214

7.4 Power mode transitions The following figure shows the power mode transitions. Any reset always brings the chip back to the normal run state. In run, wait, and stop modes active power regulation is enabled. The VLPx modes are limited in frequency, but offer a lower power operating mode than normal modes. The LLS and VLLSx modes are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application. Wait Stop Run LLS VLLS 3, 2, 1 VLPS VLPR VLPW Any reset 4 6 7 3 1 2 8 10 11 9 5 Figure 7-1. Power mode state transition diagram Power mode transitions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 214 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 215

7.5 Power modes shutdown sequencing When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. All low-power entry sequences are initiated by the core executing an WFI instruction. The ARM core's outputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes: • System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP • All other low power modes equate to: SLEEPING & SLEEPDEEP When entering the non-wait modes, the chip performs the following sequence: • Shuts off Core Clock and System Clock to the ARM Cortex-M4 core immediately. • Polls stop acknowledge indications from the non-core crossbar masters (DMA, Ethernet), supporting peripherals (SPI, PIT, RNG) and the Flash Controller for indications that System Clocks, Bus Clock and/or Flash Clock need to be left enabled to complete a previously initiated operation, effectively stalling entry to the targeted low power mode. When all acknowledges are detected, System Clock, Bus Clock and Flash Clock are turned off at the same time. • MCG and Mode Controller shut off clock sources and/or the internal supplies driven from the on-chip regulator as defined for the targeted low power mode. In wait modes, most of the system clocks are not affected by the low power mode entry. The Core Clock to the ARM Cortex-M4 core is shut off. Some modules support stop-in- wait functionality and have their clocks disabled under these configurations. The debugger modules support a transition from stop, wait, VLPS, and VLPW back to a halted state when the debugger is enabled. This transition is initiated by setting the Debug Request bit in MDM-AP control register. As part of this transition, system clocking is re- established and is equivalent to normal run/VLPR mode clocking configuration. 7.6 Module Operation in Low Power Modes The following table illustrates the functionality of each module while the chip is in each of the low power modes. (Debug modules are discussed separately; see Debug in Low Power Modes.) Number ratings (such as 2 MHz and 1 Mbps) represent the maximum frequencies or maximum data rates per mode. Also, these terms are used: • FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF. • static = Module register states and associated memories are retained. Chapter 7 Power Management K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 215 General Business Information

Page 216

• powered = Memory is powered to retain contents. • low power = Flash has a low power state that retains configuration registers to support faster wakeup. • OFF = Modules are powered off; module is in reset state upon wakeup. • wakeup = Modules can serve as a wakeup source for the chip. Table 7-2. Module operation in low power modes Modules Stop VLPR VLPW VLPS LLS VLLSx Core modules NVIC static FF FF static static OFF System modules Mode Controller FF FF FF FF FF FF LLWU1 static static static static FF FF Regulator ON low power low power low power low power low power LVD ON disabled disabled disabled disabled disabled Brown-out Detection ON ON ON ON ON ON DMA static FF FF static static OFF Watchdog FF FF FF FF static OFF EWM static FF static static static OFF Clocks 1kHz LPO ON ON ON ON ON ON System oscillator (OSC) OSCERCLK optional OSCERCLK max of 4MHz crystal OSCERCLK max of 4MHz crystal OSCERCLK max of 4MHz crystal limited to low range/low power limited to low range/low power MCG static - MCGIRCLK optional; PLL optionally on but gated 4 MHz IRC 4 MHz IRC static - no clock output static - no clock output OFF Core clock OFF 4 MHz max OFF OFF OFF OFF System clock OFF 4 MHz max 4 MHz max OFF OFF OFF Bus clock OFF 4 MHz max 4 MHz max OFF OFF OFF Memory and memory interfaces Flash powered 1 MHz max access - no pgm low power low power OFF OFF Portion of SRAM_U2 low power low power low power low power low power low power in VLLS3,2; otherwise OFF Remaining SRAM_U and all of SRAM_L low power low power low power low power low power low power in VLLS3; otherwise OFF FlexMemory low power low power3 low power low power low power OFF Register files4 powered powered powered powered powered powered FlexBus static FF FF static static OFF Table continues on the next page... Module Operation in Low Power Modes K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 216 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 217

Table 7-2. Module operation in low power modes (continued) Modules Stop VLPR VLPW VLPS LLS VLLSx EzPort disabled disabled disabled disabled disabled disabled Communication interfaces USB FS/LS static static static static static OFF USB DCD static FF FF static static OFF USB Voltage Regulator optional optional optional optional optional optional Ethernet wakeup static static static static OFF UART static, wakeup on edge 125 kbps 125 kbps static, wakeup on edge static OFF SPI static 1 Mbps 1 Mbps static static OFF I2C static, address match wakeup 100 kbps 100 kbps static, address match wakeup static OFF CAN wakeup 256 kbps 256 kbps wakeup static OFF I2S FF with external clock5 FF FF FF with external clock5 static OFF SDHC wakeup FF FF wakeup static OFF Security CRC static FF FF static static OFF RNG static FF static static static OFF Timers FTM static FF FF static static OFF PIT static FF FF static static OFF PDB static FF FF static static OFF LPTMR FF FF FF FF FF FF RTC - 32kHz OSC4 FF FF FF FF FF6 FF6 CMT static FF FF static static OFF Analog 16-bit ADC ADC internal clock only FF FF ADC internal clock only static OFF CMP7 HS or LS level compare FF FF HS or LS level compare LS level compare LS level compare 6-bit DAC static FF FF static static static VREF FF FF FF FF static OFF 12-bit DAC static FF FF static static static Human-machine interfaces GPIO wakeup FF FF wakeup static, pins latched OFF, pins latched TSI wakeup FF FF wakeup wakeup8 wakeup8 1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a transition to occur to the LLWU. 2. A 4 or 16KB portion of SRAM_U block is left powered on in low power mode VLLS2. Chapter 7 Power Management K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 217 General Business Information

Page 218

FlexRAM enabled as EEPROM is not writable in VLPR and writes are ignored. Read accesses to FlexRAM as EEPROM while in VLPR are allowed. There are no access restrictions for FlexRAM configured as traditional RAM. 4. These components remain powered in BAT power mode. 5. Use an externally generated bit clock or an externally generated audio master clock (including EXTAL). 6. RTC_CLKOUT is not available. 7. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS or VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLS, or VLLSx modes. 8. TSI wakeup from LLS and VLLSx modes is limited to a single selectable pin. 7.7 Clock Gating To conserve power, the clocks to most modules can be turned off using the SCGCx registers in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module. Prior to initializing a module, set the corresponding bit in the SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution and SIM chapters. Clock Gating K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 218 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 219

Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits. The MCU, in turn, confirms the security request and limits access to flash resources. During reset, the flash module initializes the FSEC register using data read from the security byte of the flash configuration field. NOTE The security features apply only to external accesses: debug and EzPort. CPU accesses to the flash are not affected by the status of FSEC. In the unsecured state all flash commands are available to the programming interfaces (JTAG and EzPort), as well as user code execution of Flash Controller commands. When the flash is secured (FSEC[SEC] = 00, 01, or 11), programmer interfaces are only allowed to launch mass erase operations and have no access to memory locations. Further information regarding the flash security options and enabling/disabling flash security is available in the Flash Memory Module. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 219 General Business Information

Page 220

8.3 Security Interactions with other Modules The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 Security interactions with FlexBus When flash security is enabled, SIM_SOPT2[FBSL] enables/disables off-chip accesses through the FlexBus interface. The FBSL bitfield also has an option to allow opcode and operand accesses or only operand accesses. 8.3.2 Security Interactions with EzPort When flash security is active the MCU can still boot in EzPort mode. The EzPort holds the flash logic in NVM special mode and thus limits flash operation when flash security is active. While in EzPort mode and security is active, flash bulk erase (BE) can still be executed. The write FCCOB registers (WRFCCOB) command is limited to the mass erase (Erase All Blocks) and verify all 1s (Read 1s All Blocks) commands. Read accesses to internal memories via the EzPort are blocked when security is enabled. The mass erase can be used to disable flash security, but all of the flash contents are lost in the process. A mass erase via the EzPort is allowed even when some memory locations are protected. When mass erase has been disabled, mass erase via the EzPort is blocked and cannot be defeated. 8.3.3 Security Interactions with Debug When flash security is active the JTAG port cannot access the memory resources of the MCU. Boundary scan chain operations work, but debugging capabilities are disabled so that the debug port cannot read flash contents. Although most debug functions are disabled, the debugger can write to the Flash Mass Erase in Progress bit in the MDM-AP Control register to trigger a mass erase (Erase All Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. Security Interactions with other Modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 220 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 221

When mass erase is disabled, mass erase via the debugger is blocked. Chapter 8 Security K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 221 General Business Information

Page 222

Security Interactions with other Modules K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 222 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 223

Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported: • IEEE 1149.1 JTAG • IEEE 1149.7 JTAG (cJTAG) • Serial Wire Debug (SWD) • ARM Real-Time Trace Interface The basic Cortex-M4 debug architecture is very flexible. The following diagram shows the topology of the core debug architecture and its components. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 223 General Business Information

Page 224

Private Peripheral Bus (internal) Trigger ITM TPIU Core FPB AHB-AP NVIC SWJ-DP Bus Matrix APB i/f Trace port (serial wire or multi-pin) Cortex-M4 SW/ JTAG Debug Sleep Interrupts INTNMI SLEEPING SLEEPDEEP INTISR[239:0] AWIC DWT ROM Table ETB ETM Instr. Data MCM MMCAU I-code bus D-code bus System bus Code bus MDM-AP Figure 9-1. Cortex-M4 Debug Topology The following table presents a brief description of each one of the debug components. Table 9-1. Debug Components Description Module Description SWJ-DP+ cJTAG Modified Debug Port with support for SWD, JTAG, cJTAG AHB-AP AHB Master Interface from JTAG to debug module and SOC system memory maps MDM-AP Provides centralized control and status registers for an external debugger to control the device. ROM Table Identifies which debug IP is available. Core Debug Singlestep, Register Access, Run, Core Status CoreSight Trace Funnel (not shown in figure) The CSTF combines multiple trace streams onto a single ATB bus. CoreSight Trace Replicator (not shown in figure) The ATB replicator enables two trace sinks to be wired together and operate from the same incoming trace stream. ETM (Embedded Trace Macrocell) ETMv3.5 Architecture CoreSight ETB (Embedded Trace Buffer) Memory mapped buffer used to store trace data. ITM S/W Instrumentation Messaging + Simple Data Trace Messaging + Watchpoint Messaging Table continues on the next page... Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 224 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 225

Table 9-1. Debug Components Description (continued) Module Description DWT (Data and Address Watchpoints) 4 data and address watchpoints (configurable for less, but 4 seems to be accepted) FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches code and data from code space to system space. The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space. The FBP also contains six instruction comparators for matching against instruction fetches from Code space, and remapping to a corresponding area in System space. Alternatively, the six instruction comparators can individually configure the comparators to return a Breakpoint Instruction (BKPT) to the processor core on a match, so providing hardware breakpoint capability. TPIU (Trace Port Inteface Unit) Synchronous Mode (5-pin) = TRACE_D[3:0] + TRACE_CLKOUT Synchronous Mode (3-pin) = TRACE_D[1:0] + TRACE_CLKOUT Asynchronous Mode (1-pin) = TRACE_SWO (available on JTAG_TDO) MCM (Miscellaneous Control Module) The MCM provides miscellaneous control functions including control of the ETB and trace path switching. 9.1.1 References For more information on ARM debug components, see these documents: • ARMv7-M Architecture Reference Manual • ARM Debug Interface v5.1 • ARM CoreSight Architecture Specification • ARM ETM Architecture Specification v3.5 9.2 The Debug Port The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in the following figure: Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 225 General Business Information

Page 226

CJTAG DAP Bus TDO TRACESWO TDO TDI TCK TDI nSYS_TRST nSYS_TDO nSYS_TDI nSYS_TCK nSYS_TMS nTRST TCK TMS_OUT TMS_IN TMS_OUT_OE TMS TDO TDI SWCLKTCK SWDITMS SWDO SWDOEN SWD/JTAG SELECT SWCLKTCK SWDITMS JTAGSEL SWDSEL 4’b1111 or 4’b0000 TDI TDO PEN JTAGNSW JTAGC TDO TDI nTRST TCK TMS jtag_updateinstr[3:0] 4’b1111 or 4’b1110 JTAGir[3:0] IR==BYPASS or IDCODE IR==BYPASS or IDCODE A A (1’b0 = 2-pin cJTAG) (1’b1 = 4-pin JTAG) To Test Resources 1’b1 MDM-AP AHB-AP Figure 9-2. Modified Debug Port The debug port comes out of reset in standard JTAG mode and is switched into either cJTAG or SWD mode by the following sequences. Once the mode has been changed, unused debug pins can be reassigned to any of their alternative muxed functions. 9.2.1 JTAG-to-SWD change sequence

Send more than 50 TCK cycles with TMS (SWDIO) =1
Send the 16-bit sequence on TMS (SWDIO) = 0111_1001_1110_0111 (MSB transmitted first)
Send more than 50 TCK cycles with TMS (SWDIO) =1 NOTE See the ARM documentation for the CoreSight DAP Lite for restrictions. 9.2.2 JTAG-to-cJTAG change sequence
Reset the debug port The Debug Port K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 226 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 227

Set the control level to 2 via zero-bit scans
Execute the Store Format (STFMT) command (00011) to set the scan format register to 1149.7 scan format 9.3 Debug Port Pin Descriptions The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAG and SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIO functions. Table 9-2. Debug port pins Pin Name JTAG Debug Port cJTAG Debug Port SWD Debug Port Internal Pull- up\Down Type Description Type Description Type Description JTAG_TMS/ SWD_DIO I/O JTAG Test Mode Selection I/O cJTAG Data I/O Serial Wire Data Pull-up JTAG_TCLK/ SWD_CLK I JTAG Test Clock I cJTAG Clock I Serial Wire Clock Pull-down JTAG_TDI I JTAG Test Data Input

Pull-up JTAG_TDO/ TRACE_SWO O JTAG Test Data Output O Trace output over a single pin O Trace output over a single pin N/C JTAG_TRST_ b I JTAG Reset I cJTAG Reset

Pull-up 9.4 System TAP connection The system JTAG controller is connected in parallel to the ARM TAP controller. The system JTAG controller IR codes overlay the ARM JTAG controller IR codes without conflict. Refer to the IR codes table for a list of the available IR codes. The output of the TAPs (TDO) are muxed based on the IR code which is selected. This design is fully JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, ARM's IDCODE (IR=4'b1110) is selected. Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 227 General Business Information

Page 228

9.4.1 IR Codes Table 9-3. JTAG Instructions Instruction Code[3:0] Instruction Summary IDCODE 0000 Selects device identification register for shift SAMPLE/PRELOAD 0010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation SAMPLE 0011 Selects boundary scan register for shifting and sampling without disturbing functional operation EXTEST 0100 Selects boundary scan register while applying preloaded values to output pins and asserting functional reset HIGHZ 1001 Selects bypass register while three-stating all output pins and asserting functional reset CLAMP 1100 Selects bypass register while applying preloaded values to output pins and asserting functional reset EZPORT 1101 Enables the EZPORT function for the SoC and asserts functional reset. ARM_IDCODE 1110 ARM JTAG-DP Instruction BYPASS 1111 Selects bypass register for data operations Factory debug reserved 0101, 0110, 0111 Intended for factory debug only ARM JTAG-DP Reserved 1000, 1010, 1011, 1110 These instructions will go the ARM JTAG-DP controller. Please look at ARM JTAG-DP documentation for more information on these instructions. Reserved 1 All other opcodes Decoded to select bypass register 1. The manufacturer reserves the right to change the decoding of reserved instruction codes in the future 9.5 JTAG status and control registers Through the ARM Debug Access Port (DAP), the debugger has access to the status and control elements, implemented as registers on the DAP bus as shown in the following figure. These registers provide additional control and status for low power mode recovery and typical run-control scenarios. The status register bits also provide a means for the debugger to get updated status of the core without having to initiate a bus transaction across the crossbar switch, thus remaining less intrusive during a debug session. It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessible via the Debug Access Port (DAP) using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-4. MDM-AP Register Summary Address Register Description Table continues on the next page... JTAG status and control registers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 228 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 229

Table 9-4. MDM-AP Register Summary (continued) 0x0100_0000 Status See MDM-AP Status Register 0x0100_0004 Control See MDM-AP Control Register 0x0100_00FC ID Read-only identification register that always reads as 0x001C_0000 SWJ-DP SELECT[31:24] (APSEL) selects the AP SELECT[7:4] (APBANKSEL) selects the bank A[3:2] from the APACC selects the register within the bank AHB Access Port (AHB-AP) MDM-AP Status 0x00 Control 0x01 IDR 0x3F AHB-AP SELECT[31:24] = 0x00 selects the AHB-AP See ARM documentation for further details MDM-AP SELECT[31:24] = 0x01 selects the MDM-AP SELECT[7:4] = 0x0 selects the bank with Status and Ctrl A[3:2] = 2’b00 selects the Status Register A[3:2] = 2’b01 selects the Control Register SELECT[7:4] = 0xF selects the bank with IDR A[3:2] = 2’b11 selects the IDR Register (IDR register reads 0x001C_0000) Bus Matrix See Control and Status Register Descriptions Debug Port Internal Bus Access Port Data[31:0] A[7:4] A[3:2] RnW APSEL Decode Debug Port ID Register (DPIDR) Control/Status (CTRL/STAT) AP Select (SELECT) Read Buffer (REBUFF) DP Registers 0x00 0x04 0x08 0x0C Data[31:0] A[3:2] RnW DPACC Data[31:0] A[3:2] RnW APACC Debug Port (DP) Generic See the ARM Debug Interface v5p1 Supplement. Figure 9-3. MDM AP Addressing Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 229 General Business Information

Page 230

9.5.1 MDM-AP Control Register Table 9-5. MDM-AP Control register assignments Bit Name Secure1 Description 0 Flash Mass Erase in Progress Y Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset. 1 Debug Disable N Set to disable debug. Clear to allow debug operation. When set it overrides the C_DEBUGEN bit within the DHCSR and force disables Debug logic. 2 Debug Request N Set to force the Core to halt. If the Core is in a stop or wait mode, this bit can be used to wakeup the core and transition to a halted state. 3 System Reset Request N Set to force a system reset. The system remains held in reset until this bit is cleared. 4 Core Hold Reset N Configuration bit to control Core operation at the end of system reset sequencing. 0 Normal operation - release the Core from reset along with the rest of the system at the end of system reset sequencing. 1 Suspend operation - hold the Core in reset at the end of reset sequencing. Once the system enters this suspended state, clearing this control bit immediately releases the Core from reset and CPU operation begins. 5 VLLSx Debug Request (VLLDBGREQ) N Set to configure the system to be held in reset after the next recovery from a VLLSx mode. This bit is ignored on a VLLS wakeup via the Reset pin. During a VLLS wakeup via the Reset pin, the system can be held in reset by holding the reset pin asserted allowing the debugger to re-initialize the debug modules. This bit holds the system in reset when VLLSx modes are exited to allow the debugger time to re-initialize debug IP before the debug session continues. The Mode Controller captures this bit logic on entry to VLLSx modes. Upon exit from VLLSx modes, the Mode Controller will hold the system in reset until VLLDBGACK is asserted. The VLLDBGREQ bit clears automatically due to the POR reset generated as part of the VLLSx recovery. 6 VLLSx Debug Acknowledge (VLLDBGACK) N Set to release a system being held in reset following a VLLSx recovery This bit is used by the debugger to release the system reset when it is being held on VLLSx mode exit. The debugger re-initializes all debug IP and then assert this control bit to allow the Mode Controller to release the system from reset and allow CPU operation to begin. The VLLDBGACK bit is cleared by the debugger or can be left set because it clears automatically due to the POR reset generated as part of the next VLLSx recovery. Table continues on the next page... JTAG status and control registers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 230 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 231

Table 9-5. MDM-AP Control register assignments (continued) Bit Name Secure1 Description 7 LLS, VLLSx Status Acknowledge N Set this bit to acknowledge the DAP LLS and VLLS Status bits have been read. This acknowledge automatically clears the status bits. This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. 8 Timestamp Disable N Set this bit to disable the 48-bit global trace timestamp counter during debug halt mode when the core is halted. 0 The timestamp counter continues to count assuming trace is enabled and the ETM is enabled. (default) 1 The timestamp counter freezes when the core has halted (debug halt mode). 9 – 31 Reserved for future use N 1. Command available in secure mode 9.5.2 MDM-AP Status Register Table 9-6. MDM-AP Status register assignments Bit Name Description 0 Flash Mass Erase Acknowledge The Flash Mass Erase Acknowledge bit is cleared after any system reset. The bit is also cleared at launch of a mass erase command due to write of Flash Mass Erase in Progress bit in MDM AP Control Register. The Flash Mass Erase Acknowledge is set after Flash control logic has started the mass erase operation. When mass erase is disabled (via MEEN and SEC settings), an erase request due to seting of Flash Mass Erase in Progress bit is not acknowledged. 1 Flash Ready Indicate Flash has been initialized and debugger can be configured even if system is continuing to be held in reset via the debugger. 2 System Security Indicates the security state. When secure, the debugger does not have access to the system bus or any memory mapped peripherals. This bit indicates when the part is locked and no system bus access is possible. 3 System Reset Indicates the system reset state. 0 System is in reset 1 System is not in reset 4 Reserved 5 Mass Erase Enable Indicates if the MCU can be mass erased or not 0 Mass erase is disabled 1 Mass erase is enabled Table continues on the next page... Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 231 General Business Information

Page 232

Table 9-6. MDM-AP Status register assignments (continued) Bit Name Description 6 Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled. 0 Disabled 1 Enabled 7 LP Enabled Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are the selected power mode the next time the ARM Core enters Deep Sleep. 0 Low Power Stop Mode is not enabled 1 Low Power Stop Mode is enabled Usage intended for debug operation in which Run to VLPS is attempted. Per debug definition, the system actually enters the Stop state. A debugger should interpret deep sleep indication (with SLEEPDEEP and SLEEPING asserted), in conjuntion with this bit asserted as the debugger- VLPS status indication. 8 Very Low Power Mode Indicates current power mode is VLPx. This bit is not ‘sticky’ and should always represent whether VLPx is enabled or not. This bit is used to throttle JTAG TCK frequency up/down. 9 LLS Mode Exit This bit indicates an exit from LLS mode has occurred. The debugger will lose communication while the system is in LLS (including access to this register). Once communication is reestablished, this bit indicates that the system had been in LLS. Since the debug modules held their state during LLS, they do not need to be reconfigured. This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is held until the debugger has had a chance to recognize that LLS was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. 10 VLLSx Modes Exit This bit indicates an exit from VLLSx mode has occurred. The debugger will lose communication while the system is in VLLSx (including access to this register). Once communication is reestablished, this bit indicates that the system had been in VLLSx. Since the debug modules lose their state during VLLSx modes, they need to be reconfigured. This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit bit is held until the debugger has had a chance to recognize that a VLLS mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. 11 – 15 Reserved for future use Always read 0. 16 Core Halted Indicates the Core has entered debug halt mode 17 Core SLEEPDEEP Indicates the Core has entered a low power mode SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode. SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode. 18 Core SLEEPING 19 – 31 Reserved for future use Always read 0. 9.6 Debug Resets The debug system receives the following sources of reset: Debug Resets K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 232 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 233

• JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. • Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic. • TRST asserted via the cJTAG escape command. • System POR reset Conversely the debug system is capable of generating system reset using the following mechanism: • A system reset in the DAP control register which allows the debugger to hold the system in reset. • SYSRESETREQ bit in the NVIC application interrupt and reset control register • A system reset in the DAP control register which allows the debugger to hold the Core in reset. 9.7 AHB-AP AHB-AP provides the debugger access to all memory and registers in the system, including processor registers through the NVIC. System access is independent of the processor status. AHB-AP does not do back-to-back transactions on the bus, so all transactions are non-sequential. AHB-AP can perform unaligned and bit-band transactions. AHB-AP transactions bypass the FPB, so the FPB cannot remap AHB-AP transactions. SWJ/SW-DP-initiated transaction aborts drive an AHB-AP-supported sideband signal called HABORT. This signal is driven into the Bus Matrix, which resets the Bus Matrix state, so that AHB-AP can access the Private Peripheral Bus for last ditch debugging such as read/stop/reset the core. AHB-AP transactions are little endian. The MPU includes default settings and protections for the Region Descriptor 0 (RGD0) such that the Debugger always has access to the entire address space and those rights cannot be changed by the core or any other bus master. For a short period at the start of a system reset event the system security status is being determined and debugger access to all AHB-AP transactions is blocked. The MDM-AP Status register is accessible and can be monitored to determine when this initial period is completed. After this initial period, if system reset is held via assertion of the RESET pin, the debugger has access via the bus matrix to the private peripheral bus to configure the debug IP even while system reset is asserted. While in system reset, access to other memory and register resources, accessed over the Crossbar Switch, is blocked. Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 233 General Business Information

Page 234

9.8 ITM The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can generate packets. If multiple sources generate packets at the same time, the ITM arbitrates the order in which packets are output. The four sources in decreasing order of priority are:

Software trace -- Software can write directly to ITM stimulus registers. This emits packets.
Hardware trace -- The DWT generates these packets, and the ITM emits them.
Time stamping -- Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. The Cortex-M4 clock or the bitclock rate of the Serial Wire Viewer (SWV) output clocks the counter.
Global system timestamping. Timestamps can optionally be generated using a system-wide 48-bit count value. The same count value can be used to insert timestamps in the ETM trace stream, allowing coarse-grain correlation. 9.9 Core Trace Connectivity ETM Private Peripheral Bus ATB UPSIZER ATB (8-bit) ATB (8-bit) ATB (32-bit) ETM ETB TRACE PORT ( ) ATB (8-bit) ATB FUNNEL ATB REPLICATOR ATB (32-bit) ATB UPSIZER ATB (32-bit) ATB (8-bit) TRACE PORT TRACECLKIN TRACECLK TRACEDATA[3:0] TRACESWO TPIU ITM DWT ATB (8-bit) ATB REPLICATOR ATB (8-bit) TRACECLKIN CORE CLOCK NMI Interrupt MCM Alert Interrupt Debug Halt Request MCM Figure 9-4. Core Trace Connectivity ITM K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 234 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 235

The ETM and ITM can route its data to the ETB or the TPIU. (See the MCM (Miscellaneous Control Module) for controlling the routing to the TPIU.) This configuration enables the use of trace with low cost tools while maintaining the compatibility with trace probes. The arbitration between the ETM and ITM is performed inside the TPIU. The ETB can not be configured with an interface smaller than 32 bits, making it necessary to add an ATB upsizer to make it compatible with the ETM operating with an 8-bit interface. The speed of the ETB 32 bit interface and its associated RAM is expected to be one quarter of the ETB clock. The following combinations paths are supported:

ETM -> ETB
ETM -> TPIU(4 pin or 2 pin parallel)
ITM->ETB
ITM->TPIU(1 pin SWO, 2 pin or 4 pin parallel)
ETM & ITM -> ETB
ETM & ITM -> TPIU
ETM -> ETB & ITM -> TPIU The following combination paths are NOT supported
ETM -> TPIU & ETB
ITM -> TPIU & ETB 9.10 Embedded Trace Macrocell v3.5 (ETM) The Cortex-M4 Embedded Trace Macrocell (ETM-M4) is a debug component that enables a debugger to reconstruct program execution. The CoreSight ETM-M4 supports only instruction trace. You can use it either with the Cortex-M4 Trace Port Interface Unit (M4-TPIU), or with the CoreSight ETB. The main features of an ETM are: • tracing of 16-bit and 32-bit Thumb instructions • four EmbeddedICE watchpoint inputs • a Trace Start/Stop block with EmbeddedICE inputs • one reduced function counter • two external inputs • a 24-byte FIFO queue • global timestamping Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 235 General Business Information

Page 236

9.11 Coresight Embedded Trace Buffer (ETB) The ETB provides on-chip storage of trace data using 32-bit RAM. The ETB accepts trace data from any CoreSight-compliant component trace source with an ATB master port, such as a trace source or a trace funnel. It is included in this device to remove dependencies from the trace pin pad speed, and enable low cost trace solutions. The TraceRAM size is 2 KB. APB i/f ATB slave port ATB i/f TraceRAM Control Trace RAM interface TRIGIN Register Bank Formatter APB (from ETM Trigger out) Figure 9-5. ETB Block Diagram The ETB contains the following blocks: • Formatter -- Inserts source ID signals into the data packet stream so that trace data can be re-associated with its trace source after the data is read back out of the ETB. • Control -- Control registers for trace capture and flushing. • APB interface -- Read, write, and data pointers provide access to ETB registers. In addition, the APB interface supports wait states through the use of a PREADYDBG signal output by the ETB. The APB interface is synchronous to the ATB domain. • Register bank -- Contains the management, control, and status registers for triggers, flushing behavior, and external control. • Trace RAM interface -- Controls reads and writes to the Trace RAM. 9.11.1 Performance Profiling with the ETB To create a performance profile (e.g. gprof) for the target application, a means to collect trace over a long period of time is needed. The ETB buffer is too small to capture a meaningful profile in just one take. What is needed is to collect and concatenate data from the ETB buffer for multiple sequential runs. Using the ETB packet counter (described in Miscellaneous Control Module (MCM)), the trace analysis tool can capture Coresight Embedded Trace Buffer (ETB) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 236 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 237

multiple sequential runs by executing code until the ETB is almost full, and halting or executing an interrupt handler to allow the buffer to be emptied, and then continuing executing code. The target halts or executes an interrupt handler when the buffer is almost full to empty the data and then the debugger runs the target again. 9.11.2 ETB Counter Control The ETB packet counter is controlled by the ETB counter control register, ETB reload register, and ETB counter value register implemented in the Miscellaneous Control Module (MCM) accessible via the Private Peripheral Bus. Via the ETB counter control register the ETB control logic can be configured to cause an MCM Alert Interrupt, an NMI Interrupt, or cause a Debug halt when the down counter reaches 0. Other features of the ETB control logic include: • Down counter to count as many as 512 x 32-bit packets. • Reload request transfers reload value to counter. • ATB valid and ready signals used to form counter decrement. • The counter disarms itself when the count reaches 0. 9.12 TPIU The TPIU acts as a bridge between the on-chip trace data from the Embedded Trace Macrocell (ETM) and the Instrumentation Trace Macrocell (ITM), with separate IDs, to a data stream, encapsulating IDs where required, that is then captured by a Trace Port Analyzer (TPA). The TPIU is specially designed for low-cost debug. 9.13 DWT The DWT is a unit that performs the following debug functionality: • It contains four comparators that you can configure as a hardware watchpoint, an ETM trigger, a PC sampler event trigger, or a data address sampler event trigger. The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. The second comparator, DWT_COMP1, can also be used as a data comparator. • The DWT contains counters for: • Clock cycles (CYCCNT) • Folded instructions • Load store unit (LSU) operations Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 237 General Business Information

Page 238

• Sleep cycles • CPI (all instruction cycles except for the first cycle) • Interrupt overhead NOTE An event is emitted each time a counter overflows. • The DWT can be configured to emit PC samples at defined intervals, and to emit interrupt event information. 9.14 Debug in Low Power Modes In low power modes in which the debug modules are kept static or powered off, the debugger cannot gather any debug data for the duration of the low power mode. In the case that the debugger is held static, the debug port returns to full functionality as soon as the low power mode exits and the system returns to a state with active debug. In the case that the debugger logic is powered off, the debugger is reset on recovery and must be reconfigured once the low power mode is exited. Power mode entry logic monitors Debug Power Up and System Power Up signals from the debug port as indications that a debugger is active. These signals can be changed in RUN, VLPR, WAIT and VLPW. If the debug signal is active and the system attempts to enter stop or VLPS, FCLK continues to run to support core register access. In these modes in which FCLK is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar. With debug enabled, transitions from Run directly to VLPS are not allowed and result in the system entering Stop mode instead. Status bits within the MDM-AP Status register can be evaluated to determine this pseudo-VLPS state. Note with the debug enabled, transitions from Run--> VLPR --> VLPS are still possible but also result in the system entering Stop mode instead. In VLLS mode all debug modules are powered off and reset at wakeup. In LLS mode, the debug modules retain their state but no debug activity is possible. NOTE When using cJTAG and entering LLS mode, the cJTAG controller must be reset on exit from LLS mode. Going into a VLLSx mode causes all the debug controls and settings to be reset. To give time to the debugger to sync up with the HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. Debug in Low Power Modes K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 238 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 239

9.14.1 Debug Module State in Low Power Modes The following table shows the state of the debug modules in low power modes. These terms are used: • FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF. • static = Module register states and associated memories are retained. • OFF = Modules are powered off; module is in reset state upon wakeup. Table 9-7. Debug Module State in Low Power Modes Module STOP VLPR VLPW VLPS LLS VLLSx Debug Port FF FF FF OFF static OFF AHB-AP FF FF FF OFF static OFF ITM FF FF FF OFF static OFF ETM FF FF FF OFF static OFF ETB FF FF FF OFF static OFF TPIU FF FF FF OFF static OFF DWT FF FF FF OFF static OFF 9.15 Debug & Security When security is enabled (FSEC[SEC] != 10), the debug port capabilities are limited in order to prevent exploitation of secure data. In the secure state the debugger still has access to the MDM-AP Status Register and can determine the current security state of the device. In the case of a secure device, the debugger also has the capability of performing a mass erase operation via writes to the MDM-AP Control Register. In the case of a secure device that has mass erase disabled (FSEC[MEEN] = 10), attempts to mass erase via the debug interface are blocked. Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 239 General Business Information

Page 240

Debug & Security K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 240 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 241

Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. The Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin. 10.2 Signal Multiplexing Integration This section summarizes how the module is integrated into the device. For a comprehensive description of the module itself, see the module’s dedicated chapter. Register access Signal Multiplexing/ Port Control Transfers Module Peripheral bus controller 1 Module Module External Pins Transfers Figure 10-1. Signal multiplexing integration Table 10-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Table continues on the next page... K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 241 General Business Information

Page 242

Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus controller Peripheral bridge 10.2.1 Port control and interrupt module features • Five 32-pin ports NOTE Not all pins are available on the device. See the following section for details. • Each 32-pin port is assigned one interrupt. • The digital filter option has two clock source options: bus clock and 1-kHz LPO. The 1-kHz LPO option gives users this feature in low power modes. • The digital filter is configurable from 1 to 32 clock cycles when enabled. 10.2.2 PCRn reset values for port A PCRn bit reset values for port A are 1 for the following bits: • For PCR0: bits 1, 6, 8, 9, and 10. • For PCR1 to PCR4: bits 0, 1, 6, 8, 9, and 10. • For PCR5 : bits 0, 1, and 6. All other PCRn bit reset values for port A are 0. 10.2.3 Clock gating The clock to the port control module can be gated on and off using the SCGC5[PORTx] bits in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing the corresponding module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution chapter. Signal Multiplexing Integration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 242 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 243

10.2.4 Signal multiplexing constraints

A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin.
To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. 10.3 Pinout 10.3.1 K60 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 144 LQFP 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort — L5 RTC_ WAKEUP_B RTC_ WAKEUP_B RTC_ WAKEUP_B — M5 NC NC NC — A10 NC NC NC — B10 NC NC NC — C10 NC NC NC 1 D3 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA RTC_CLKOUT 2 D2 PTE1/ LLWU_P0 ADC1_SE5a ADC1_SE5a PTE1/ LLWU_P0 SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL SPI1_SIN 3 D1 PTE2/ LLWU_P1 ADC1_SE6a ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_CTS_ b SDHC0_DCLK 4 E4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_ b SDHC0_CMD SPI1_SOUT 5 E5 VDD VDD VDD 6 F6 VSS VSS VSS 7 E3 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0 UART3_TX SDHC0_D3 8 E2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 9 E1 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_ b I2S0_MCLK USB_SOF_ OUT 10 F4 PTE7 DISABLED PTE7 UART3_RTS_ b I2S0_RXD0 11 F3 PTE8 DISABLED PTE8 I2S0_RXD1 UART5_TX I2S0_RX_FS 12 F2 PTE9 DISABLED PTE9 I2S0_TXD1 UART5_RX I2S0_RX_ BCLK Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 243 General Business Information

Page 244

144 LQFP 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 13 F1 PTE10 DISABLED PTE10 UART5_CTS_ b I2S0_TXD0 14 G4 PTE11 DISABLED PTE11 UART5_RTS_ b I2S0_TX_FS 15 G3 PTE12 DISABLED PTE12 I2S0_TX_ BCLK 16 E6 VDD VDD VDD 17 F7 VSS VSS VSS 18 H3 VSS VSS VSS 19 H1 USB0_DP USB0_DP USB0_DP 20 H2 USB0_DM USB0_DM USB0_DM 21 G1 VOUT33 VOUT33 VOUT33 22 G2 VREGIN VREGIN VREGIN 23 J1 ADC0_DP1 ADC0_DP1 ADC0_DP1 24 J2 ADC0_DM1 ADC0_DM1 ADC0_DM1 25 K1 ADC1_DP1 ADC1_DP1 ADC1_DP1 26 K2 ADC1_DM1 ADC1_DM1 ADC1_DM1 27 L1 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 28 L2 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 29 M1 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 30 M2 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 31 H5 VDDA VDDA VDDA 32 G5 VREFH VREFH VREFH 33 G6 VREFL VREFL VREFL 34 H6 VSSA VSSA VSSA 35 K3 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 36 J3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 37 M3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 38 L3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 Pinout K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 244 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 245

144 LQFP 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 39 L4 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 40 M7 XTAL32 XTAL32 XTAL32 41 M6 EXTAL32 EXTAL32 EXTAL32 42 L6 VBAT VBAT VBAT 43 — VDD VDD VDD 44 — VSS VSS VSS 45 M4 PTE24 ADC0_SE17 ADC0_SE17 PTE24 CAN1_TX UART4_TX EWM_OUT_b 46 K5 PTE25 ADC0_SE18 ADC0_SE18 PTE25 CAN1_RX UART4_RX EWM_IN 47 K4 PTE26 DISABLED PTE26 ENET_1588_ CLKIN UART4_CTS_ b RTC_CLKOUT USB_CLKIN 48 J4 PTE27 DISABLED PTE27 UART4_RTS_ b 49 H4 PTE28 DISABLED PTE28 50 J5 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS_ b/ UART0_COL_ b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK 51 J6 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI 52 K6 PTA2 JTAG_TDO/ TRACE_SWO/ EZP_DO TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO 53 K7 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4 PTA3 UART0_RTS_ b FTM0_CH0 JTAG_TMS/ SWD_DIO 54 L7 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b 55 M8 PTA5 DISABLED PTA5 USB_CLKIN FTM0_CH2 RMII0_RXER/ MII0_RXER CMP2_OUT I2S0_TX_ BCLK JTAG_TRST_ b 56 E7 VDD VDD VDD 57 G7 VSS VSS VSS 58 J7 PTA6 DISABLED PTA6 FTM0_CH3 TRACE_ CLKOUT 59 J8 PTA7 ADC0_SE10 ADC0_SE10 PTA7 FTM0_CH4 TRACE_D3 60 K8 PTA8 ADC0_SE11 ADC0_SE11 PTA8 FTM1_CH0 FTM1_QD_ PHA TRACE_D2 61 L8 PTA9 DISABLED PTA9 FTM1_CH1 MII0_RXD3 FTM1_QD_ PHB TRACE_D1 62 M9 PTA10 DISABLED PTA10 FTM2_CH0 MII0_RXD2 FTM2_QD_ PHA TRACE_D0 63 L9 PTA11 DISABLED PTA11 FTM2_CH1 MII0_RXCLK FTM2_QD_ PHB 64 K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_RXD1/ MII0_RXD1 I2S0_TXD0 FTM1_QD_ PHA Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 245 General Business Information

Page 246

144 LQFP 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 65 J9 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 RMII0_RXD0/ MII0_RXD0 I2S0_TX_FS FTM1_QD_ PHB 66 L10 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX RMII0_CRS_ DV/ MII0_RXDV I2S0_RX_ BCLK I2S0_TXD1 67 L11 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX RMII0_TXEN/ MII0_TXEN I2S0_RXD0 68 K10 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_ b/ UART0_COL_ b RMII0_TXD0/ MII0_TXD0 I2S0_RX_FS I2S0_RXD1 69 K11 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_ b RMII0_TXD1/ MII0_TXD1 I2S0_MCLK 70 E8 VDD VDD VDD 71 G8 VSS VSS VSS 72 M12 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0 73 M11 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_ ALT1 74 L12 RESET_b RESET_b RESET_b 75 K12 PTA24 DISABLED PTA24 MII0_TXD2 FB_A29 76 J12 PTA25 DISABLED PTA25 MII0_TXCLK FB_A28 77 J11 PTA26 DISABLED PTA26 MII0_TXD3 FB_A27 78 J10 PTA27 DISABLED PTA27 MII0_CRS FB_A26 79 H12 PTA28 DISABLED PTA28 MII0_TXER FB_A25 80 H11 PTA29 DISABLED PTA29 MII0_COL FB_A24 81 H10 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0 RMII0_MDIO/ MII0_MDIO FTM1_QD_ PHA 82 H9 PTB1 ADC0_SE9/ ADC1_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1 RMII0_MDC/ MII0_MDC FTM1_QD_ PHB 83 G12 PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS_ b ENET0_1588_ TMR0 FTM0_FLT3 84 G11 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS_ b/ UART0_COL_ b ENET0_1588_ TMR1 FTM0_FLT0 85 G10 PTB4 ADC1_SE10 ADC1_SE10 PTB4 ENET0_1588_ TMR2 FTM1_FLT0 86 G9 PTB5 ADC1_SE11 ADC1_SE11 PTB5 ENET0_1588_ TMR3 FTM2_FLT0 87 F12 PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23 88 F11 PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22 89 F10 PTB8 DISABLED PTB8 UART3_RTS_ b FB_AD21 Pinout K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 246 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 247

144 LQFP 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 90 F9 PTB9 DISABLED PTB9 SPI1_PCS1 UART3_CTS_ b FB_AD20 91 E12 PTB10 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1 92 E11 PTB11 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2 93 H7 VSS VSS VSS 94 F5 VDD VDD VDD 95 E10 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN 96 E9 PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT_b 97 D12 PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_ BCLK FB_AD15 FTM2_QD_ PHA 98 D11 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FB_OE_b FTM2_QD_ PHB 99 D10 PTB20 DISABLED PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT 100 D9 PTB21 DISABLED PTB21 SPI2_SCK FB_AD30 CMP1_OUT 101 C12 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29 CMP2_OUT 102 C11 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28 103 B12 PTC0 ADC0_SE14/ TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4 PDB0_EXTRG FB_AD14 I2S0_TXD1 104 B11 PTC1/ LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3 UART1_RTS_ b FTM0_CH0 FB_AD13 I2S0_TXD0 105 A12 PTC2 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2 UART1_CTS_ b FTM0_CH1 FB_AD12 I2S0_TX_FS 106 A11 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_ BCLK 107 H8 VSS VSS VSS 108 — VDD VDD VDD 109 A9 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT 110 D8 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 FB_AD10 CMP0_OUT 111 C8 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_EXTRG I2S0_RX_ BCLK FB_AD9 I2S0_MCLK 112 B8 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FS FB_AD8 113 A8 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 I2S0_MCLK FB_AD7 114 D7 PTC9 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 I2S0_RX_ BCLK FB_AD6 FTM2_FLT0 115 C7 PTC10 ADC1_SE6b ADC1_SE6b PTC10 I2C1_SCL I2S0_RX_FS FB_AD5 116 B7 PTC11/ LLWU_P11 ADC1_SE7b ADC1_SE7b PTC11/ LLWU_P11 I2C1_SDA I2S0_RXD1 FB_RW_b 117 A7 PTC12 DISABLED PTC12 UART4_RTS_ b FB_AD27 Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 247 General Business Information

Page 248

144 LQFP 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 118 D6 PTC13 DISABLED PTC13 UART4_CTS_ b FB_AD26 119 C6 PTC14 DISABLED PTC14 UART4_RX FB_AD25 120 B6 PTC15 DISABLED PTC15 UART4_TX FB_AD24 121 — VSS VSS VSS 122 — VDD VDD VDD 123 A6 PTC16 DISABLED PTC16 CAN1_RX UART3_RX ENET0_1588_ TMR0 FB_CS5_b/ FB_TSIZ1/ FB_BE23_16_ b 124 D5 PTC17 DISABLED PTC17 CAN1_TX UART3_TX ENET0_1588_ TMR1 FB_CS4_b/ FB_TSIZ0/ FB_BE31_24_ b 125 C5 PTC18 DISABLED PTC18 UART3_RTS_ b ENET0_1588_ TMR2 FB_TBST_b/ FB_CS2_b/ FB_BE15_8_b 126 B5 PTC19 DISABLED PTC19 UART3_CTS_ b ENET0_1588_ TMR3 FB_CS3_b/ FB_BE7_0_b FB_TA_b 127 A5 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0 UART2_RTS_ b FB_ALE/ FB_CS1_b/ FB_TS_b 128 D4 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_ b FB_CS0_b 129 C4 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUT UART2_RX FB_AD4 130 B4 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FB_AD3 131 A4 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1 UART0_RTS_ b FTM0_CH4 FB_AD2 EWM_IN 132 A3 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_ b/ UART0_COL_ b FTM0_CH5 FB_AD1 EWM_OUT_b 133 A2 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0 134 M10 VSS VSS VSS 135 F8 VDD VDD VDD 136 A1 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1 137 C9 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16 138 B9 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17 139 B3 PTD10 DISABLED PTD10 UART5_RTS_ b FB_A18 140 B2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_ b SDHC0_ CLKIN FB_A19 141 B1 PTD12 DISABLED PTD12 SPI2_SCK SDHC0_D4 FB_A20 142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21 Pinout K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 248 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 249

144 LQFP 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 10.3.2 K60 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 249 General Business Information

Page 250

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 75 74 73 60 59 58 57 56 55 54 53 52 51 72 71 70 69 68 67 66 65 64 63 62 61 25 24 23 22 21 40 39 38 37 50 49 48 47 46 45 44 43 42 41 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 98 97 96 95 94 93 92 91 90 89 88 80 81 82 83 84 85 86 87 100 108 VDD 107 106 105 104 103 102 101 VSS PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6 PTC0 PTB23 PTB22 116 PTC11/LLWU_P11 115 114 113 112 111 110 109 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 124 PTC17 123 122 121 120 119 118 117 PTC16 VDD VSS PTC15 PTC14 PTC13 PTC12 132 PTD5 131 130 129 128 127 126 125 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC19 PTC18 140 PTD11 139 138 137 136 135 134 133 PTD10 PTD9 PTD8 PTD7 VDD VSS PTD6/LLWU_P15 144 143 142 141 PTD15 PTD14 PTD13 PTD12 PTB20 PTA28 PTA27 PTA26 PTA25 PTB19 PTB18 PTB17 PTB16 VDD VSS PTB11 PTB10 PTB9 PTB8 PTB7 PTA29 PTB0/LLWU_P5 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB21 PTA24 RESET_b PTA19 PTA18 VSS VDD PTA17 PTA16 PTA15 PTA14 PTA13/LLWU_P4 PTA12 PTA11 PTA10 PTA9 PTA8 PTA7 PTA6 VSS VDD PTA5 PTA4/LLWU_P3 PTA3 PTA2 PTA1 PTA0 PTE28 PTE27 PTE26 PTE25 PTE24 VSS VDD VBAT EXTAL32 XTAL32 DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23 DAC0_OUT/CMP1_IN3/ADC0_SE23 VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18 USB0_DM USB0_DP VSS VSS VDD PTE12 PTE11 PTE10 PTE9 PTE8 PTE7 PTE6 PTE5 PTE4/LLWU_P2 VSS VDD PTE3 PTE2/LLWU_P1 PTE1/LLWU_P0 PTE0 ADC1_DP1 ADC0_DM1 ADC0_DP1 VREGIN VOUT33 ADC0_SE16/CMP1_IN2/ADC0_SE21 ADC1_SE16/CMP2_IN2/ADC0_SE22 VSSA VREFL VREFH VDDA PGA1_DM/ADC1_DM0/ADC0_DM3 PGA1_DP/ADC1_DP0/ADC0_DP3 PGA0_DM/ADC0_DM0/ADC1_DM3 PGA0_DP/ADC0_DP0/ADC1_DP3 ADC1_DM1 Figure 10-2. K60 144 LQFP Pinout Diagram Pinout K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 250 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 251

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A B C D E F G H J A B C D E F G H J 10 K K 10 11 11 L L 12 12 M M PTA18 PTC8 PTC4/ NC PTC3/ PTC2 PTA1 PTA6 PTA0 PTE27 ADC0_SE16/ ADC1_SE16/ PTE26 PTE25 PTA2 PTA3 PTA8 PTA7 VSS VSS VSSA VDDA PTE28 VSS USB0_DM ADC0_DM1 ADC1_DM1 PGA0_DM/ DAC0_OUT/ DAC1_OUT/ RTC VBAT PTA4/ PTA9 PTA11 PTA12 PTA13/ PTB1 PTA27 PTB0/ PTB4 PTB5 VSS VSS VREFL VREFH PTE11 PTE12 VREGIN VOUT33 USB0_DP ADC0_DP1 ADC1_DP1 PGA0_DP/ PGA1_DP/ PGA1_DM/ VREF_OUT/ PTE24 NC EXTAL32 XTAL32 PTA5 PTA10 VSS PTA16 PTA14 PTB3 PTA29 PTA26 PTA17 PTA15 PTA19 RESET_b PTA24 PTA25 PTA28 PTB2 PTB6 PTB7 PTB8 PTB9 VDD VDD PTB17 PTB16 PTB10 PTB11 PTB19 PTB18 PTB22 PTB23 NC PTB20 PTB21 PTC5/ PTD8 PTC6/ PTC7 PTD9 NC PTC1/ PTC0 VSS VSS VDD VDD PTC13 PTC9 PTC11/ PTC10 PTC19 PTC15 PTC14 PTC18 PTD2/ PTD3 PTD10 PTD13 PTE0 PTD1 PTC17 VDD VDD PTE7 PTE3 PTE4/ PTE8 PTE9 PTE10 PTE6 PTE5 PTE1/ PTE2/ PTD15 PTD14 PTD11 PTD12 PTC12 PTC16 PTD0/ PTD4/ PTD5 PTD6/ PTD7 LLWU_P15 LLWU_P14 LLWU_P12 LLWU_P8 LLWU_P7 LLWU_P11 LLWU_P6 LLWU_P13 LLWU_P10 LLWU_P1 LLWU_P0 LLWU_P9 LLWU_P2 LLWU_P5 CMP1_IN2/ ADC0_SE21 LLWU_P4 CMP2_IN2/ ADC0_SE22 ADC0_DP0/ ADC1_DP3 ADC0_DM0/ ADC1_DM3 CMP1_IN3/ ADC0_SE23 CMP0_IN4/ CMP2_IN3/ ADC1_SE23 _WAKEUP_B LLWU_P3 CMP1_IN5/ CMP0_IN5/ ADC1_SE18 ADC1_DP0/ ADC0_DP3 ADC1_DM0/ ADC0_DM3 Figure 10-3. K60 144 MAPBGA Pinout Diagram 10.4 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 251 General Business Information

Page 252

10.4.1 Core Modules Table 10-2. JTAG Signal Descriptions Chip signal name Module signal name Description I/O JTAG_TMS JTAG_TMS/ SWD_DIO JTAG Test Mode Selection I/O JTAG_TCLK JTAG_TCLK/ SWD_CLK JTAG Test Clock I JTAG_TDI JTAG_TDI JTAG Test Data Input I JTAG_TDO JTAG_TDO/ TRACE_SWO JTAG Test Data Output O JTAG_TRST JTAG_TRST_b JTAG Reset I Table 10-3. SWD Signal Descriptions Chip signal name Module signal name Description I/O SWD_DIO JTAG_TMS/ SWD_DIO Serial Wire Data I/O SWD_CLK JTAG_TCLK/ SWD_CLK Serial Wire Clock I Table 10-4. TPIU Signal Descriptions Chip signal name Module signal name Description I/O TRACE_CLKOUT TRACECLK Trace clock output from the ARM CoreSight debug block O TRACE_D[3:2] TRACEDATA Trace output data from the ARM CoreSight debug block used for 5- pin interface O TRACE_D[1:0] TRACEDATA Trace output data from the ARM CoreSight debug block used for both 5-pin and 3-pin interfaces O TRACE_SWO JTAG_TDO/ TRACE_SWO Trace output data from the ARM CoreSight debug block over a single pin O Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 252 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 253

10.4.2 System Modules Table 10-5. System Signal Descriptions Chip signal name Module signal name Description I/O NMI — Non-maskable interrupt NOTE: Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin. I RESET — Reset bi-directional signal I/O VDD — MCU power I VSS — MCU ground I Table 10-6. EWM Signal Descriptions Chip signal name Module signal name Description I/O EWM_IN EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. I EWM_OUT EWM_out EWM reset out signal O 10.4.3 Clock Modules Table 10-7. OSC Signal Descriptions Chip signal name Module signal name Description I/O EXTAL0 EXTAL External clock/Oscillator input I XTAL0 XTAL Oscillator output O Table 10-8. RTC OSC Signal Descriptions Chip signal name Module signal name Description I/O EXTAL32 EXTAL32 32.768 kHz oscillator input I XTAL32 XTAL32 32.768 kHz oscillator output O Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 253 General Business Information

Page 254

10.4.4 Memories and Memory Interfaces Table 10-9. EzPort Signal Descriptions Chip signal name Module signal name Description I/O EZP_CLK EZP_CK EzPort Clock Input EZP_CS EZP_CS EzPort Chip Select Input EZP_DI EZP_D EzPort Serial Data In Input EZP_DO EZP_Q EzPort Serial Data Out Output Table 10-10. FlexBus Signal Descriptions Chip signal name Module signal name Description I/O CLKOUT FB_CLK O FlexBus Clock Output FB_A[29:16] FB_A[29:16] Address Bus When FlexBus is used in a nonmultiplexed configuration, this is the address bus. When FlexBus is used in a multiplexed configuration, this bus is not used. O FB_AD[31:0] FB_D31–FB_D0 Data Bus—During the first cycle, this bus drives the upper address byte, addr[31:24]. When FlexBus is used in a nonmultiplexed configuration, this is the data bus, FB_D. When FlexBus is used in a multiplexed configuration, this is the address and data bus, FB_AD. The number of byte lanes carrying the data is determined by the port size associated with the matching chip-select. When FlexBus is used in a multiplexed configuration, the full 32-bit address is driven on the first clock of a bus cycle (address phase). After the first clock, the data is driven on the bus (data phase). During the data phase, the address is driven on the pins not used for data. For example, in 16-bit mode, the lower address is driven on FB_AD15–FB_AD0, and in 8-bit mode, the lower address is driven on FB_AD23–FB_AD0. I/O FB_CS[5:0] FB_CS5–FB_CS0 General Purpose Chip-Selects—Indicate which external memory or peripheral is selected. A particular chip-select is asserted when the transfer address is within the external memory's or peripheral's address space, as defined in CSAR[BA] and CSMR[BAM]. O FB_BE31_24_BLS7_ 0, FB_BE23_16_BLS15 _8, FB_BE15_8_BLS23_ 16, FB_BE7_0_BLS31_2 4 FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 Byte Enables—Indicate that data is to be latched or driven onto a specific byte lane of the data bus. CSCR[BEM] determines if these signals are asserted on reads and writes or on writes only. For external SRAM or flash devices, the FB_BE outputs should be connected to individual byte strobe signals. O FB_OE FB_OE Output Enable—Sent to the external memory or peripheral to enable a read transfer. This signal is asserted during read accesses only when a chip-select matches the current address decode. O Table continues on the next page... Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 254 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 255

Table 10-10. FlexBus Signal Descriptions (continued) Chip signal name Module signal name Description I/O FB_R W FB_R/W Read/Write—Indicates whether the current bus operation is a read operation (FB_R/W high) or a write operation (FB_R/W low). O FB_TS/ FB_ALE FB_TS Transfer Start—Indicates that the chip has begun a bus transaction and that the address and attributes are valid. An inverted FB_TS is available as an address latch enable (FB_ALE), which indicates when the address is being driven on the FB_AD bus. FB_TS/FB_ALE is asserted for one bus clock cycle. The chip can extend this signal until the first positive clock edge after FB_CS asserts. See CSCR[EXTS] and Extended Transfer Start/Address Latch Enable. O FB_TSIZ[1:0] FB_TSIZ1–FB_TSIZ0 Transfer Size—Indicates (along with FB_TBST) the data transfer size of the current bus operation. The interface supports 8-, 16-, and 32-bit operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. • 00b = 4 bytes • 01b = 1 byte • 10b = 2 bytes • 11b = 16 bytes (line) For misaligned transfers, FB_TSIZ1–FB_TSIZ0 indicate the size of each transfer. For example, if a 32-bit access through a 32-bit port device occurs at a misaligned offset of 1h, 8 bits are transferred first (FB_TSIZ1–FB_TSIZ0 = 01b), 16 bits are transferred next at offset 2h (FB_TSIZ1–FB_TSIZ0 = 10b), and the final 8 bits are transferred at offset 4h (FB_TSIZ1–FB_TSIZ0 = 01b). For aligned transfers larger than the port size, FB_TSIZ1– FB_TSIZ0 behave as follows: • If bursting is used, FB_TSIZ1–FB_TSIZ0 are driven to the transfer size. • If bursting is inhibited, FB_TSIZ1–FB_TSIZ0 first show the entire transfer size and then show the port size. For burst-inhibited transfers, FB_TSIZ1–FB_TSIZ0 change with each FB_TS assertion to reflect the next transfer size. For transfers to port sizes smaller than the transfer size, FB_TSIZ1–FB_TSIZ0 indicate the size of the entire transfer on the first access and the size of the current port transfer on subsequent transfers. For example, for a 32-bit write to an 8-bit port, FB_TSIZ1–FB_TSIZ0 are 00b for the first transaction and 01b for the next three transactions. If bursting is used for a 32-bit write to an 8-bit port, FB_TSIZ1–FB_TSIZ0 are driven to 00b for the entire transfer. O Table continues on the next page... Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 255 General Business Information

Page 256

Table 10-10. FlexBus Signal Descriptions (continued) Chip signal name Module signal name Description I/O FB_TA FB_TA Transfer Acknowledge—Indicates that the external data transfer is complete. When FB_TA is asserted during a read transfer, FlexBus latches the data and then terminates the transfer. When FB_TA is asserted during a write transfer, the transfer is terminated. If auto-acknowledge is disabled (CSCR[AA] = 0), the external memory or peripheral drives FB_TA to terminate the transfer. If auto-acknowledge is enabled (CSCR[AA] = 1), FB_TA is generated internally after a specified number of wait states, or the external memory or peripheral may assert external FB_TA before the wait- state countdown to terminate the transfer early. The chip deasserts FB_CS one cycle after the last FB_TA is asserted. During read transfers, the external memory or peripheral must continue to drive data until FB_TA is recognized. For write transfers, the chip continues driving data one clock cycle after FB_CS is deasserted. The number of wait states is determined by CSCR or the external FB_TA input. If the external FB_TA is used, the external memory or peripheral has complete control of the number of wait states. Note: External memory or peripherals should assert FB_TA only while the FB_CS signal to the external memory or peripheral is asserted. The CSPMCR register controls muxing of FB_TA with other signals. If auto-acknowledge is not used and CSPMCR does not allow FB_TA control, FlexBus may hang. I FB_TBST FB_TBST Transfer Burst—Indicates that a burst transfer is in progress as driven by the chip. A burst transfer can be 2 to 16 beats depending on FB_TSIZ1–FB_TSIZ0 and the port size. Note: When a burst transfer is in progress (FB_TBST = 0b), the transfer size is 16 bytes (FB_TSIZ1–FB_TSIZ0 = 11b), and the address is misaligned within the 16-byte boundary, the external memory or peripheral must be able to wrap around the address. O 10.4.5 Analog Table 10-11. ADC 0 Signal Descriptions Chip signal name Module signal name Description I/O ADC0_DP3, PGA0_DP, ADC0_DP[1:0] DADP3–DADP0 Differential Analog Channel Inputs I ADC0_DM3, PGA0_DM, ADC0_DM[1:0] DADM3–DADM0 Differential Analog Channel Inputs I ADC0_SE[18:4] AD23–AD4 Single-Ended Analog Channel Inputs I Table continues on the next page... Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 256 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 257

Table 10-11. ADC 0 Signal Descriptions (continued) Chip signal name Module signal name Description I/O VREFH VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I VDDA VDDA Analog Power Supply I VSSA VSSA Analog Ground I Table 10-12. ADC 1 Signal Descriptions Chip signal name Module signal name Description I/O ADC1_DP3, PGA1_DP, ADC1_DP[1:0] DADP3–DADP0 Differential Analog Channel Inputs I ADC1_DM3, PGA1_DM, ADC1_DM[1:0] DADM3–DADM0 Differential Analog Channel Inputs I ADC1_SE[18:4] AD23–AD4 Single-Ended Analog Channel Inputs I VREFH VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I VDDA VDDA Analog Power Supply I VSSA VSSA Analog Ground I Table 10-13. CMP 0 Signal Descriptions Chip signal name Module signal name Description I/O CMP0_IN[5:0] IN[5:0] Analog voltage inputs I CMP0_OUT CMPO Comparator output O Table 10-14. CMP 1 Signal Descriptions Chip signal name Module signal name Description I/O CMP1_IN[5:0] IN[5:0] Analog voltage inputs I CMP1_OUT CMPO Comparator output O Table 10-15. CMP 2 Signal Descriptions Chip signal name Module signal name Description I/O CMP2_IN[5:0] IN[5:0] Analog voltage inputs I CMP2_OUT CMPO Comparator output O Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 257 General Business Information

Page 258

Table 10-16. DAC 0 Signal Descriptions Chip signal name Module signal name Description I/O DAC0_OUT — DAC output O Table 10-17. DAC 1 Signal Descriptions Chip signal name Module signal name Description I/O DAC1_OUT — DAC output O Table 10-18. TRIAMP 1 Signal Descriptions Chip signal name Module signal name Description I/O TRI1_DP inp_3v Amplifier positive input terminal I TRI1_DM inn_3v Amplifier negative input terminal I TRI1_OUT out_3v Amplifier output terminal O Table 10-19. VREF Signal Descriptions Chip signal name Module signal name Description I/O VREF_OUT VREF_OUT Internally-generated Voltage Reference output O 10.4.6 Timer Modules Table 10-20. FTM 0 Signal Descriptions Chip signal name Module signal name Description I/O FTM_CLKIN[1:0] EXTCLK External clock. FTM external clock can be selected to drive the FTM counter. I FTM0_CH[7:0] CHn FTM channel (n), where n can be 7-0 I/O FTM0_FLT[3:0] FAULTj Fault input (j), where j can be 3-0 I Table 10-21. FTM 1 Signal Descriptions Chip signal name Module signal name Description I/O FTM_CLKIN[1:0] EXTCLK External clock. FTM external clock can be selected to drive the FTM counter. I Table continues on the next page... Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 258 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 259

Table 10-21. FTM 1 Signal Descriptions (continued) Chip signal name Module signal name Description I/O FTM1_CH[1:0] CHn FTM channel (n), where n can be 7-0 I/O FTM1_FLT0 FAULTj Fault input (j), where j can be 3-0 I FTM1_QD_PHA PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. I FTM1_QD_PHB PHB Quadrature decoder phase B input. Input pin associated with quadrature decoder phase B. I Table 10-22. FTM 2 Signal Descriptions Chip signal name Module signal name Description I/O FTM_CLKIN[1:0] EXTCLK External clock. FTM external clock can be selected to drive the FTM counter. I FTM2_CH[1:0] CHn FTM channel (n), where n can be 7-0 I/O FTM2_FLT0 FAULTj Fault input (j), where j can be 3-0 I FTM2_QD_PHA PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. I FTM2_QD_PHB PHB Quadrature decoder phase B input. Input pin associated with quadrature decoder phase B. I Table 10-23. CMT Signal Descriptions Chip signal name Module signal name Description I/O CMT_IRO CMT_IRO Infrared Output O Table 10-24. PDB 0 Signal Descriptions Chip signal name Module signal name Description I/O PDB0_EXTRG EXTRG External Trigger Input Source If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. I Table 10-25. LPT 0 Signal Descriptions Chip signal name Module signal name Description I/O LPT0_ALT[2:1] LPTMR_ALTn I Pulse Counter Input pin Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 259 General Business Information

Page 260

Table 10-26. RTC Signal Descriptions Chip signal name Module signal name Description I/O VBAT — Backup battery supply for RTC and VBAT register file I RTC_CLKOUT RTC_CLKOUT 1 Hz square-wave output O RTC_WAKEUP RTC_WAKEUP Wakeup for external device O Chip signal name Module signal name Description I/O ENET0_1588_TMR[3:0] 1588_TMRn Capture/compare block input/ output event bus. When configured for capture and a rising edge is detected, the current timer value is latched and transferred into the corresponding ENET_TCCRn register for inspection by software. When configured for compare, the corresponding signal 1588_TMRn is asserted for one cycle when the timer reaches the compare value programmed in register ENET_TCCRn. An interrupt or DMA request can be triggered if the corresponding bit in ENET_TCSRn[TIE] or ENET_TCSRn[TDRE] is set. I/O ENET_1588_CLKIN 1588_TMRn Capture/compare block input/ output event bus. When configured for capture and a rising edge is detected, the current timer value is latched and transferred into the corresponding ENET_TCCRn register for inspection by software. When configured for compare, the corresponding signal 1588_TMRn is asserted for one cycle when the timer reaches the compare value programmed in register ENET_TCCRn. An interrupt or DMA request can be triggered if the corresponding bit in ENET_TCSRn[TIE] or ENET_TCSRn[TDRE] is set. I/O Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 260 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 261

10.4.7 Communication Interfaces Ethernet MII Signal Descriptions Chip signal name Module signal name Description I/O MII0_COL MII_COL Asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode. I MII0_CRS MII_CRS Carrier sense. When asserted, indicates transmit or receive medium is not idle. In RMII mode, this signal is present on the RMII_CRS_DV pin. I MII0_MDC MII_MDC Output clock provides a timing reference to the PHY for data transfers on the MDIO signal. O MII0_MDIO MII_MDIO Transfers control information between the external PHY and the media-access controller. Data is synchronous to MDC. This signal is an input after reset. I/O MII0_RXCLK MII_RXCLK In MII mode, provides a timing reference for RXDV, RXD[3:0], and RXER. I MII0_RXDV MII_RXDV Asserting this input indicates the PHY has valid nibbles present on the MII. RXDV must remain asserted from the first recovered nibble of the frame through to the last nibble. Asserting RXDV must start no later than the SFD and exclude any EOF. In RMII mode, this pin also generates the CRS signal. I MII0_RXD[3:0] MII_RXD[3:0] Contains the Ethernet input data transferred from the PHY to the media-access controller when RXDV is asserted. I MII0_RXER MII_RXER When asserted with RXDV, indicates the PHY detects an error in the current frame. I Table continues on the next page... Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 261 General Business Information

Page 262

Chip signal name Module signal name Description I/O MII0_TXCLK MII_TXCLK Input clock, which provides a timing reference for TXEN, TXD[3:0], and TXER. I MII0_TXD[3:0] MII_TXD[3:0] Serial output Ethernet data. Only valid during TXEN assertion. O MII0_TXEN MII_TXEN Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is deasserted before the first TXCLK following the final nibble of the frame. O MII0_TXER MII_TXER When asserted for one or more clock cycles while TXEN is also asserted, PHY sends one or more illegal symbols. O Ethernet RMII Signal Descriptions Chip signal name Module signal name Description I/O RMII0_MDC RMII_MDC Output clock provides a timing reference to the PHY for data transfers on the MDIO signal. O RMII0_MDIO RMII_MDIO Transfers control information between the external PHY and the media-access controller. Data is synchronous to MDC. This signal is an input after reset. I/O RMII0_CRS_DV RMII_CRS_DV Asserting this input indicates the PHY has valid nibbles present on the MII. RXDV must remain asserted from the first recovered nibble of the frame through to the last nibble. Asserting RXDV must start no later than the SFD and exclude any EOF. In RMII mode, this pin also generates the CRS signal. I RMII0_RXD[1:0] RMII_RXD[1:0] Contains the Ethernet input data transferred from the PHY to the media-access controller when RXDV is asserted. I RMII0_RXER RMII_RXER When asserted with RXDV, indicates the PHY detects an error in the current frame. I Table continues on the next page... Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 262 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 263

Chip signal name Module signal name Description I/O RMII0_TXD[1:0] RMII_TXD[1:0] Serial output Ethernet data. Only valid during TXEN assertion. O RMII0_TXEN RMII_TXEN Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is deasserted before the first TXCLK following the final nibble of the frame. O Internal OSCERCLK clock1 RMII_REF_CLK In RMII mode, this signal is the reference clock for receive, transmit, and the control interface. I Table 10-27. USB FS OTG Signal Descriptions Chip signal name Module signal name Description I/O USB0_DM usb_dm USB D- analog data signal on the USB bus. I/O USB0_DP usb_dp USB D+ analog data signal on the USB bus. I/O USB_CLKIN — Alternate USB clock input I Table 10-28. USB VREG Signal Descriptions Chip signal name Module signal name Description I/O VOUT33 reg33_out Regulator output voltage O VREGIN reg33_in Unregulated power supply I Table 10-29. CAN 0 Signal Descriptions Chip signal name Module signal name Description I/O CAN0_RX CAN Rx CAN Receive Pin Input CAN0_TX CAN Tx CAN Transmit Pin Output Table 10-30. CAN 1 Signal Descriptions Chip signal name Module signal name Description I/O CAN1_RX CAN Rx CAN Receive Pin Input CAN1_TX CAN Tx CAN Transmit Pin Output Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 263 General Business Information

Page 264

Table 10-31. SPI 0 Signal Descriptions Chip signal name Module signal name Description I/O SPI0_PCS0 PCS0/SS Peripheral Chip Select 0 output I/O SPI0_PCS[3:1] PCS[3:1] Peripheral Chip Select 1 – 3 O SPI0_PCS4 PCS4 Peripheral Chip Select 4 O SPI0_SIN SIN Serial Data In I SPI0_SOUT SOUT Serial Data Out O SPI0_SCK SCK Master mode: Serial Clock (output) I/O Table 10-32. SPI 1 Signal Descriptions Chip signal name Module signal name Description I/O SPI1_PCS0 PCS0/SS Peripheral Chip Select 0 output I/O SPI1_PCS[3:1] PCS[3:1] Peripheral Chip Select 1 – 3 O SPI1_SIN SIN Serial Data In I SPI1_SOUT SOUT Serial Data Out O SPI1_SCK SCK Master mode: Serial Clock (output) I/O Table 10-33. SPI 2 Signal Descriptions Chip signal name Module signal name Description I/O SPI2_PCS0 PCS0/SS Peripheral Chip Select 0 output I/O SPI2_PCS1 PCS[3:1] Peripheral Chip Select 1 – 3 O SPI2_SIN SIN Serial Data In I SPI2_SOUT SOUT Serial Data Out O SPI2_SCK SCK Master mode: Serial Clock (output) I/O Table 10-34. I2C 0 Signal Descriptions Chip signal name Module signal name Description I/O I2C0_SCL SCL Bidirectional serial clock line of the I2C system. I/O I2C0_SDA SDA Bidirectional serial data line of the I2C system. I/O Table 10-35. I2C 1 Signal Descriptions Chip signal name Module signal name Description I/O I2C1_SCL SCL Bidirectional serial clock line of the I2C system. I/O I2C1_SDA SDA Bidirectional serial data line of the I2C system. I/O Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 264 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 265

Table 10-36. UART 0 Signal Descriptions Chip signal name Module signal name Description I/O UART0_CTS CTS Clear to send I UART0_RTS RTS Request to send O UART0_TX TXD Transmit data O UART0_RX RXD Receive data I UART0_COL Collision Collision detect I Table 10-37. UART 1 Signal Descriptions Chip signal name Module signal name Description I/O UART1_CTS CTS Clear to send I UART1_RTS RTS Request to send O UART1_TX TXD Transmit data O UART1_RX RXD Receive data I Table 10-38. UART 2 Signal Descriptions Chip signal name Module signal name Description I/O UART2_CTS CTS Clear to send I UART2_RTS RTS Request to send O UART2_TX TXD Transmit data O UART2_RX RXD Receive data I Table 10-39. UART 3 Signal Descriptions Chip signal name Module signal name Description I/O UART3_CTS CTS Clear to send I UART3_RTS RTS Request to send O UART3_TX TXD Transmit data O UART3_RX RXD Receive data I Table 10-40. UART 4 Signal Descriptions Chip signal name Module signal name Description I/O UART4_CTS CTS Clear to send I UART4_RTS RTS Request to send O Table continues on the next page... Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 265 General Business Information

Page 266

Table 10-40. UART 4 Signal Descriptions (continued) Chip signal name Module signal name Description I/O UART4_TX TXD Transmit data O UART4_RX RXD Receive data I Table 10-41. UART 5 Signal Descriptions Chip signal name Module signal name Description I/O UART5_CTS CTS Clear to send I UART5_RTS RTS Request to send O UART5_TX TXD Transmit data O UART5_RX RXD Receive data I Table 10-42. SDHC Signal Descriptions Chip signal name Module signal name Description I/O SDHC0_CLKIN — SDHC clock input I SDHC0_DCLK SDHC_DCLK Generated clock used to drive the MMC, SD, SDIO or CE-ATA cards. O SDHC0_CMD SDHC_CMD Send commands to and receive responses from the card. I/O SDHC0_D0 SDHC_D0 DAT0 line or busy-state detect I/O SDHC0_D1 SDHC_D1 8-bit mode: DAT1 line 4-bit mode: DAT1 line or interrupt detect 1-bit mode: Interrupt detect I/O SDHC0_D2 SDHC_D2 4-/8-bit mode: DAT2 line or read wait 1-bit mode: Read wait I/O SDHC0_D3 SDHC_D3 4-/8-bit mode: DAT3 line or configured as card detection pin 1-bit mode: May be configured as card detection pin I/O SDHC0_D4 SDHC_D4 DAT4 line in 8-bit mode Not used in other modes I/O SDHC0_D5 SDHC_D5 DAT5 line in 8-bit mode Not used in other modes I/O SDHC0_D6 SDHC_D6 DAT6 line in 8-bit mode Not used in other modes I/O SDHC0_D7 SDHC_D7 DAT7 line in 8-bit mode Not used in other modes I/O Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 266 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 267

Table 10-43. I2S0 Signal Descriptions Chip signal name Module signal name Description I/O I2S0_MCLK SAI_MCLK Audio Master Clock I/O I2S0_RX_BCLK SAI_RX_BCLK Receive Bit Clock I/O I2S0_RX_FS SAI_RX_SYNC Receive Frame Sync I/O I2S0_RXD SAI_RX_DATA[1:0] Receive Data I I2S0_TX_BCLK SAI_TX_BCLK Transmit Bit Clock I/O I2S0_TX_FS SAI_TX_SYNC Transmit Frame Sync I/O I2S0_TXD SAI_TX_DATA[1:0] Transmit Data O 10.4.8 Human-Machine Interfaces (HMI) Table 10-44. GPIO Signal Descriptions Chip signal name Module signal name Description I/O PTA[31:0]1 PORTA31–PORTA0 General-purpose input/output I/O PTB[31:0]1 PORTB31–PORTB0 General-purpose input/output I/O PTC[31:0]1 PORTC31–PORTC0 General-purpose input/output I/O PTD[31:0]1 PORTD31–PORTD0 General-purpose input/output I/O PTE[31:0]1 PORTE31–PORTE0 General-purpose input/output I/O 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. Table 10-45. TSI 0 Signal Descriptions Chip signal name Module signal name Description I/O TSI0_CH[15:0] TSI_IN[15:0] TSI pins. Switchable driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins I/O Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 267 General Business Information

Page 268

Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 268 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 269

Chapter 11 Port control and interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. 11.2 Overview The port control and interrupt (PORT) module provides support for port control, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state. There is one instance of the PORT module for each port. Not all pins within each port are implemented on a specific device. 11.2.1 Features The PORT module has the following features: • Pin interrupt • Interrupt flag and enable registers for each pin • Support for edge sensitive (rising, falling, both) or level sensitive (low, high) configured per pin • Support for interrupt or DMA request configured per pin K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 269 General Business Information

Page 270

• Asynchronous wakeup in Low-Power modes • Pin interrupt is functional in all digital Pin Muxing modes • Port control • Individual pull control fields with pullup, pulldown, and pull-disablesupport on selected pins • Individual drive strength field supporting high and low drive strength on selected pins • Individual slew rate field supporting fast and slow slew rates on selected pins • Individual input passive filter field supporting enable and disable of the individual input passive filter on selected pins • Individual open drain field supporting enable and disable of the individual open drain output on selected pins • Individual mux control field supporting analog or pin disabled, GPIO, and up to six chip-specific digital functions • Pad configuration fields are functional in all digital Pin Muxing modes 11.2.2 Modes of operation 11.2.2.1 Run mode In Run mode, the PORT operates normally. 11.2.2.2 Wait mode In Wait mode, PORT continues to operate normally and may be configured to exit the Low-Power mode if an enabled interrupt is detected. DMA requests are still generated during the Wait mode, but do not cause an exit from the Low-Power mode. 11.2.2.3 Stop mode In Stop mode, the PORT can be configured to exit the Low-Power mode via an asynchronous wakeup signal if an enabled interrupt is detected. 11.2.2.4 Debug mode In Debug mode, PORT operates normally. Overview K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 270 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 271

11.3 External signal description The following table describes the PORT external signal. Table 11-1. Signal properties Name Function I/O Reset Pull PORTx[31:0] External interrupt I/O 0

NOTE Not all pins within each port are implemented on each device. 11.4 Detailed signal description The following table contains the detailed signal description for the PORT interface. Table 11-2. PORT interface—detailed signal description Signal I/O Description PORTx[31:0] I/O External interrupt. State meaning Asserted—pin is logic one. Negated—pin is logic zero. Timing Assertion—may occur at any time and can assert asynchronously to the system clock. Negation—may occur at any time and can assert asynchronously to the system clock. 11.5 Memory map and register definition Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states. PORT memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_9000 Pin Control Register n (PORTA_PCR0) 32 R/W See section 11.5.1/277 4004_9004 Pin Control Register n (PORTA_PCR1) 32 R/W See section 11.5.1/277 4004_9008 Pin Control Register n (PORTA_PCR2) 32 R/W See section 11.5.1/277 Table continues on the next page... Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 271 General Business Information

Page 272

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_900C Pin Control Register n (PORTA_PCR3) 32 R/W See section 11.5.1/277 4004_9010 Pin Control Register n (PORTA_PCR4) 32 R/W See section 11.5.1/277 4004_9014 Pin Control Register n (PORTA_PCR5) 32 R/W See section 11.5.1/277 4004_9018 Pin Control Register n (PORTA_PCR6) 32 R/W See section 11.5.1/277 4004_901C Pin Control Register n (PORTA_PCR7) 32 R/W See section 11.5.1/277 4004_9020 Pin Control Register n (PORTA_PCR8) 32 R/W See section 11.5.1/277 4004_9024 Pin Control Register n (PORTA_PCR9) 32 R/W See section 11.5.1/277 4004_9028 Pin Control Register n (PORTA_PCR10) 32 R/W See section 11.5.1/277 4004_902C Pin Control Register n (PORTA_PCR11) 32 R/W See section 11.5.1/277 4004_9030 Pin Control Register n (PORTA_PCR12) 32 R/W See section 11.5.1/277 4004_9034 Pin Control Register n (PORTA_PCR13) 32 R/W See section 11.5.1/277 4004_9038 Pin Control Register n (PORTA_PCR14) 32 R/W See section 11.5.1/277 4004_903C Pin Control Register n (PORTA_PCR15) 32 R/W See section 11.5.1/277 4004_9040 Pin Control Register n (PORTA_PCR16) 32 R/W See section 11.5.1/277 4004_9044 Pin Control Register n (PORTA_PCR17) 32 R/W See section 11.5.1/277 4004_9048 Pin Control Register n (PORTA_PCR18) 32 R/W See section 11.5.1/277 4004_904C Pin Control Register n (PORTA_PCR19) 32 R/W See section 11.5.1/277 4004_9050 Pin Control Register n (PORTA_PCR20) 32 R/W See section 11.5.1/277 4004_9054 Pin Control Register n (PORTA_PCR21) 32 R/W See section 11.5.1/277 4004_9058 Pin Control Register n (PORTA_PCR22) 32 R/W See section 11.5.1/277 4004_905C Pin Control Register n (PORTA_PCR23) 32 R/W See section 11.5.1/277 4004_9060 Pin Control Register n (PORTA_PCR24) 32 R/W See section 11.5.1/277 4004_9064 Pin Control Register n (PORTA_PCR25) 32 R/W See section 11.5.1/277 4004_9068 Pin Control Register n (PORTA_PCR26) 32 R/W See section 11.5.1/277 4004_906C Pin Control Register n (PORTA_PCR27) 32 R/W See section 11.5.1/277 4004_9070 Pin Control Register n (PORTA_PCR28) 32 R/W See section 11.5.1/277 4004_9074 Pin Control Register n (PORTA_PCR29) 32 R/W See section 11.5.1/277 4004_9078 Pin Control Register n (PORTA_PCR30) 32 R/W See section 11.5.1/277 4004_907C Pin Control Register n (PORTA_PCR31) 32 R/W See section 11.5.1/277 4004_9080 Global Pin Control Low Register (PORTA_GPCLR) 32 W (always reads 0) 0_0000 _0000h 11.5.2/280 4004_9084 Global Pin Control High Register (PORTA_GPCHR) 32 W (always reads 0) 0_0000 _0000h 11.5.3/280 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 32 w1c 0_0000 _0000h 11.5.4/281 4004_A000 Pin Control Register n (PORTB_PCR0) 32 R/W See section 11.5.1/277 4004_A004 Pin Control Register n (PORTB_PCR1) 32 R/W See section 11.5.1/277 Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 272 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 273

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_A008 Pin Control Register n (PORTB_PCR2) 32 R/W See section 11.5.1/277 4004_A00C Pin Control Register n (PORTB_PCR3) 32 R/W See section 11.5.1/277 4004_A010 Pin Control Register n (PORTB_PCR4) 32 R/W See section 11.5.1/277 4004_A014 Pin Control Register n (PORTB_PCR5) 32 R/W See section 11.5.1/277 4004_A018 Pin Control Register n (PORTB_PCR6) 32 R/W See section 11.5.1/277 4004_A01C Pin Control Register n (PORTB_PCR7) 32 R/W See section 11.5.1/277 4004_A020 Pin Control Register n (PORTB_PCR8) 32 R/W See section 11.5.1/277 4004_A024 Pin Control Register n (PORTB_PCR9) 32 R/W See section 11.5.1/277 4004_A028 Pin Control Register n (PORTB_PCR10) 32 R/W See section 11.5.1/277 4004_A02C Pin Control Register n (PORTB_PCR11) 32 R/W See section 11.5.1/277 4004_A030 Pin Control Register n (PORTB_PCR12) 32 R/W See section 11.5.1/277 4004_A034 Pin Control Register n (PORTB_PCR13) 32 R/W See section 11.5.1/277 4004_A038 Pin Control Register n (PORTB_PCR14) 32 R/W See section 11.5.1/277 4004_A03C Pin Control Register n (PORTB_PCR15) 32 R/W See section 11.5.1/277 4004_A040 Pin Control Register n (PORTB_PCR16) 32 R/W See section 11.5.1/277 4004_A044 Pin Control Register n (PORTB_PCR17) 32 R/W See section 11.5.1/277 4004_A048 Pin Control Register n (PORTB_PCR18) 32 R/W See section 11.5.1/277 4004_A04C Pin Control Register n (PORTB_PCR19) 32 R/W See section 11.5.1/277 4004_A050 Pin Control Register n (PORTB_PCR20) 32 R/W See section 11.5.1/277 4004_A054 Pin Control Register n (PORTB_PCR21) 32 R/W See section 11.5.1/277 4004_A058 Pin Control Register n (PORTB_PCR22) 32 R/W See section 11.5.1/277 4004_A05C Pin Control Register n (PORTB_PCR23) 32 R/W See section 11.5.1/277 4004_A060 Pin Control Register n (PORTB_PCR24) 32 R/W See section 11.5.1/277 4004_A064 Pin Control Register n (PORTB_PCR25) 32 R/W See section 11.5.1/277 4004_A068 Pin Control Register n (PORTB_PCR26) 32 R/W See section 11.5.1/277 4004_A06C Pin Control Register n (PORTB_PCR27) 32 R/W See section 11.5.1/277 4004_A070 Pin Control Register n (PORTB_PCR28) 32 R/W See section 11.5.1/277 4004_A074 Pin Control Register n (PORTB_PCR29) 32 R/W See section 11.5.1/277 4004_A078 Pin Control Register n (PORTB_PCR30) 32 R/W See section 11.5.1/277 4004_A07C Pin Control Register n (PORTB_PCR31) 32 R/W See section 11.5.1/277 4004_A080 Global Pin Control Low Register (PORTB_GPCLR) 32 W (always reads 0) 0_0000 _0000h 11.5.2/280 4004_A084 Global Pin Control High Register (PORTB_GPCHR) 32 W (always reads 0) 0_0000 _0000h 11.5.3/280 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 32 w1c 0_0000 _0000h 11.5.4/281 4004_B000 Pin Control Register n (PORTC_PCR0) 32 R/W See section 11.5.1/277 Table continues on the next page... Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 273 General Business Information

Page 274

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_B004 Pin Control Register n (PORTC_PCR1) 32 R/W See section 11.5.1/277 4004_B008 Pin Control Register n (PORTC_PCR2) 32 R/W See section 11.5.1/277 4004_B00C Pin Control Register n (PORTC_PCR3) 32 R/W See section 11.5.1/277 4004_B010 Pin Control Register n (PORTC_PCR4) 32 R/W See section 11.5.1/277 4004_B014 Pin Control Register n (PORTC_PCR5) 32 R/W See section 11.5.1/277 4004_B018 Pin Control Register n (PORTC_PCR6) 32 R/W See section 11.5.1/277 4004_B01C Pin Control Register n (PORTC_PCR7) 32 R/W See section 11.5.1/277 4004_B020 Pin Control Register n (PORTC_PCR8) 32 R/W See section 11.5.1/277 4004_B024 Pin Control Register n (PORTC_PCR9) 32 R/W See section 11.5.1/277 4004_B028 Pin Control Register n (PORTC_PCR10) 32 R/W See section 11.5.1/277 4004_B02C Pin Control Register n (PORTC_PCR11) 32 R/W See section 11.5.1/277 4004_B030 Pin Control Register n (PORTC_PCR12) 32 R/W See section 11.5.1/277 4004_B034 Pin Control Register n (PORTC_PCR13) 32 R/W See section 11.5.1/277 4004_B038 Pin Control Register n (PORTC_PCR14) 32 R/W See section 11.5.1/277 4004_B03C Pin Control Register n (PORTC_PCR15) 32 R/W See section 11.5.1/277 4004_B040 Pin Control Register n (PORTC_PCR16) 32 R/W See section 11.5.1/277 4004_B044 Pin Control Register n (PORTC_PCR17) 32 R/W See section 11.5.1/277 4004_B048 Pin Control Register n (PORTC_PCR18) 32 R/W See section 11.5.1/277 4004_B04C Pin Control Register n (PORTC_PCR19) 32 R/W See section 11.5.1/277 4004_B050 Pin Control Register n (PORTC_PCR20) 32 R/W See section 11.5.1/277 4004_B054 Pin Control Register n (PORTC_PCR21) 32 R/W See section 11.5.1/277 4004_B058 Pin Control Register n (PORTC_PCR22) 32 R/W See section 11.5.1/277 4004_B05C Pin Control Register n (PORTC_PCR23) 32 R/W See section 11.5.1/277 4004_B060 Pin Control Register n (PORTC_PCR24) 32 R/W See section 11.5.1/277 4004_B064 Pin Control Register n (PORTC_PCR25) 32 R/W See section 11.5.1/277 4004_B068 Pin Control Register n (PORTC_PCR26) 32 R/W See section 11.5.1/277 4004_B06C Pin Control Register n (PORTC_PCR27) 32 R/W See section 11.5.1/277 4004_B070 Pin Control Register n (PORTC_PCR28) 32 R/W See section 11.5.1/277 4004_B074 Pin Control Register n (PORTC_PCR29) 32 R/W See section 11.5.1/277 4004_B078 Pin Control Register n (PORTC_PCR30) 32 R/W See section 11.5.1/277 4004_B07C Pin Control Register n (PORTC_PCR31) 32 R/W See section 11.5.1/277 4004_B080 Global Pin Control Low Register (PORTC_GPCLR) 32 W (always reads 0) 0_0000 _0000h 11.5.2/280 4004_B084 Global Pin Control High Register (PORTC_GPCHR) 32 W (always reads 0) 0_0000 _0000h 11.5.3/280 4004_B0A0 Interrupt Status Flag Register (PORTC_ISFR) 32 w1c 0_0000 _0000h 11.5.4/281 Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 274 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 275

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_C000 Pin Control Register n (PORTD_PCR0) 32 R/W See section 11.5.1/277 4004_C004 Pin Control Register n (PORTD_PCR1) 32 R/W See section 11.5.1/277 4004_C008 Pin Control Register n (PORTD_PCR2) 32 R/W See section 11.5.1/277 4004_C00C Pin Control Register n (PORTD_PCR3) 32 R/W See section 11.5.1/277 4004_C010 Pin Control Register n (PORTD_PCR4) 32 R/W See section 11.5.1/277 4004_C014 Pin Control Register n (PORTD_PCR5) 32 R/W See section 11.5.1/277 4004_C018 Pin Control Register n (PORTD_PCR6) 32 R/W See section 11.5.1/277 4004_C01C Pin Control Register n (PORTD_PCR7) 32 R/W See section 11.5.1/277 4004_C020 Pin Control Register n (PORTD_PCR8) 32 R/W See section 11.5.1/277 4004_C024 Pin Control Register n (PORTD_PCR9) 32 R/W See section 11.5.1/277 4004_C028 Pin Control Register n (PORTD_PCR10) 32 R/W See section 11.5.1/277 4004_C02C Pin Control Register n (PORTD_PCR11) 32 R/W See section 11.5.1/277 4004_C030 Pin Control Register n (PORTD_PCR12) 32 R/W See section 11.5.1/277 4004_C034 Pin Control Register n (PORTD_PCR13) 32 R/W See section 11.5.1/277 4004_C038 Pin Control Register n (PORTD_PCR14) 32 R/W See section 11.5.1/277 4004_C03C Pin Control Register n (PORTD_PCR15) 32 R/W See section 11.5.1/277 4004_C040 Pin Control Register n (PORTD_PCR16) 32 R/W See section 11.5.1/277 4004_C044 Pin Control Register n (PORTD_PCR17) 32 R/W See section 11.5.1/277 4004_C048 Pin Control Register n (PORTD_PCR18) 32 R/W See section 11.5.1/277 4004_C04C Pin Control Register n (PORTD_PCR19) 32 R/W See section 11.5.1/277 4004_C050 Pin Control Register n (PORTD_PCR20) 32 R/W See section 11.5.1/277 4004_C054 Pin Control Register n (PORTD_PCR21) 32 R/W See section 11.5.1/277 4004_C058 Pin Control Register n (PORTD_PCR22) 32 R/W See section 11.5.1/277 4004_C05C Pin Control Register n (PORTD_PCR23) 32 R/W See section 11.5.1/277 4004_C060 Pin Control Register n (PORTD_PCR24) 32 R/W See section 11.5.1/277 4004_C064 Pin Control Register n (PORTD_PCR25) 32 R/W See section 11.5.1/277 4004_C068 Pin Control Register n (PORTD_PCR26) 32 R/W See section 11.5.1/277 4004_C06C Pin Control Register n (PORTD_PCR27) 32 R/W See section 11.5.1/277 4004_C070 Pin Control Register n (PORTD_PCR28) 32 R/W See section 11.5.1/277 4004_C074 Pin Control Register n (PORTD_PCR29) 32 R/W See section 11.5.1/277 4004_C078 Pin Control Register n (PORTD_PCR30) 32 R/W See section 11.5.1/277 4004_C07C Pin Control Register n (PORTD_PCR31) 32 R/W See section 11.5.1/277 4004_C080 Global Pin Control Low Register (PORTD_GPCLR) 32 W (always reads 0) 0_0000 _0000h 11.5.2/280 4004_C084 Global Pin Control High Register (PORTD_GPCHR) 32 W (always reads 0) 0_0000 _0000h 11.5.3/280 Table continues on the next page... Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 275 General Business Information

Page 276

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_C0A0 Interrupt Status Flag Register (PORTD_ISFR) 32 w1c 0_0000 _0000h 11.5.4/281 4004_D000 Pin Control Register n (PORTE_PCR0) 32 R/W See section 11.5.1/277 4004_D004 Pin Control Register n (PORTE_PCR1) 32 R/W See section 11.5.1/277 4004_D008 Pin Control Register n (PORTE_PCR2) 32 R/W See section 11.5.1/277 4004_D00C Pin Control Register n (PORTE_PCR3) 32 R/W See section 11.5.1/277 4004_D010 Pin Control Register n (PORTE_PCR4) 32 R/W See section 11.5.1/277 4004_D014 Pin Control Register n (PORTE_PCR5) 32 R/W See section 11.5.1/277 4004_D018 Pin Control Register n (PORTE_PCR6) 32 R/W See section 11.5.1/277 4004_D01C Pin Control Register n (PORTE_PCR7) 32 R/W See section 11.5.1/277 4004_D020 Pin Control Register n (PORTE_PCR8) 32 R/W See section 11.5.1/277 4004_D024 Pin Control Register n (PORTE_PCR9) 32 R/W See section 11.5.1/277 4004_D028 Pin Control Register n (PORTE_PCR10) 32 R/W See section 11.5.1/277 4004_D02C Pin Control Register n (PORTE_PCR11) 32 R/W See section 11.5.1/277 4004_D030 Pin Control Register n (PORTE_PCR12) 32 R/W See section 11.5.1/277 4004_D034 Pin Control Register n (PORTE_PCR13) 32 R/W See section 11.5.1/277 4004_D038 Pin Control Register n (PORTE_PCR14) 32 R/W See section 11.5.1/277 4004_D03C Pin Control Register n (PORTE_PCR15) 32 R/W See section 11.5.1/277 4004_D040 Pin Control Register n (PORTE_PCR16) 32 R/W See section 11.5.1/277 4004_D044 Pin Control Register n (PORTE_PCR17) 32 R/W See section 11.5.1/277 4004_D048 Pin Control Register n (PORTE_PCR18) 32 R/W See section 11.5.1/277 4004_D04C Pin Control Register n (PORTE_PCR19) 32 R/W See section 11.5.1/277 4004_D050 Pin Control Register n (PORTE_PCR20) 32 R/W See section 11.5.1/277 4004_D054 Pin Control Register n (PORTE_PCR21) 32 R/W See section 11.5.1/277 4004_D058 Pin Control Register n (PORTE_PCR22) 32 R/W See section 11.5.1/277 4004_D05C Pin Control Register n (PORTE_PCR23) 32 R/W See section 11.5.1/277 4004_D060 Pin Control Register n (PORTE_PCR24) 32 R/W See section 11.5.1/277 4004_D064 Pin Control Register n (PORTE_PCR25) 32 R/W See section 11.5.1/277 4004_D068 Pin Control Register n (PORTE_PCR26) 32 R/W See section 11.5.1/277 4004_D06C Pin Control Register n (PORTE_PCR27) 32 R/W See section 11.5.1/277 4004_D070 Pin Control Register n (PORTE_PCR28) 32 R/W See section 11.5.1/277 4004_D074 Pin Control Register n (PORTE_PCR29) 32 R/W See section 11.5.1/277 4004_D078 Pin Control Register n (PORTE_PCR30) 32 R/W See section 11.5.1/277 4004_D07C Pin Control Register n (PORTE_PCR31) 32 R/W See section 11.5.1/277 4004_D080 Global Pin Control Low Register (PORTE_GPCLR) 32 W (always reads 0) 0_0000 _0000h 11.5.2/280 Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 276 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 277

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_D084 Global Pin Control High Register (PORTE_GPCHR) 32 W (always reads 0) 0_0000 _0000h 11.5.3/280 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 32 w1c 0_0000 _0000h 11.5.4/281 11.5.1 Pin Control Register n (PORTx_PCRn) NOTE Refer to the Signal Multiplexing and Signal Descriptions chapter for the reset value of this device. Address: Base address + 0h offset + (4d × i), where i=0d to 31d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 ISF 0 IRQC W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LK 0 MUX 0 DSE ODE PFE 0 SRE PE PS W Reset 0 0 0 0 0 x* x* x* 0 x* 0 x* 0 x* x* x*

Notes: x = Undefined at reset. • PORTx_PCRn field descriptions Field Description 31–25 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 24 ISF Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes. 0 Configured interrupt is not detected. 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. Table continues on the next page... Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 277 General Business Information

Page 278

PORTx_PCRn field descriptions (continued) Field Description 23–20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19–16 IRQC Interrupt Configuration The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured to generate interrupt/DMA request as follows: 0000 Interrupt/DMA request disabled. 0001 DMA request on rising edge. 0010 DMA request on falling edge. 0011 DMA request on either edge. 0100 Reserved. 1000 Interrupt when logic zero. 1001 Interrupt on rising edge. 1010 Interrupt on falling edge. 1011 Interrupt on either edge. 1100 Interrupt when logic one. Others Reserved. 15 LK Lock Register 0 Pin Control Register fields [15:0] are not locked. 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. 14–11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10–8 MUX Pin Mux Control Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in configuring the pin for a different pin muxing slot. The corresponding pin is configured in the following pin muxing slot as follows: 000 Pin disabled (analog). 001 Alternative 1 (GPIO). 010 Alternative 2 (chip-specific). 011 Alternative 3 (chip-specific). 100 Alternative 4 (chip-specific). 101 Alternative 5 (chip-specific). 110 Alternative 6 (chip-specific). 111 Alternative 7 (chip-specific). 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 DSE Drive Strength Enable This bit is read only for pins that do not support a configurable drive strength. Drive strength configuration is valid in all digital pin muxing modes. 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 5 ODE Open Drain Enable Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 278 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 279

PORTx_PCRn field descriptions (continued) Field Description This bit is read only for pins that do not support a configurable open drain output. Open drain configuration is valid in all digital pin muxing modes. 0 Open drain output is disabled on the corresponding pin. 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 4 PFE Passive Filter Enable This bit is read only for pins that do not support a configurable passive input filter. Passive filter configuration is valid in all digital pin muxing modes. 0 Passive input filter is disabled on the corresponding pin. 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter of 10 MHz to 30 MHz bandwidth is enabled on the digital input path. Disable the passive input filter when high speed interfaces of more than 2 MHz are supported on the pin. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 SRE Slew Rate Enable This bit is read only for pins that do not support a configurable slew rate. Slew rate configuration is valid in all digital pin muxing modes. 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 1 PE Pull Enable This bit is read only for pins that do not support a configurable pull resistor. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for the pins that support a configurable pull resistor. Pull configuration is valid in all digital pin muxing modes. 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. 0 PS Pull Select This bit is read only for pins that do not support a configurable pull resistor direction. Pull configuration is valid in all digital pin muxing modes. 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 279 General Business Information

Page 280

11.5.2 Global Pin Control Low Register (PORTx_GPCLR) Only 32-bit writes are supported to this register. Address: Base address + 80h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_GPCLR field descriptions Field Description 31–16 GPWE Global Pin Write Enable Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD. If a selected Pin Control Register is locked then the write to that register is ignored. 0 Corresponding Pin Control Register is not updated with the value in GPWD. 1 Corresponding Pin Control Register is updated with the value in GPWD. 15–0 GPWD Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. 11.5.3 Global Pin Control High Register (PORTx_GPCHR) Only 32-bit writes are supported to this register. Address: Base address + 84h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_GPCHR field descriptions Field Description 31–16 GPWE Global Pin Write Enable Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD. If a selected Pin Control Register is locked then the write to that register is ignored. 0 Corresponding Pin Control Register is not updated with the value in GPWD. 1 Corresponding Pin Control Register is updated with the value in GPWD. 15–0 GPWD Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 280 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 281

11.5.4 Interrupt Status Flag Register (PORTx_ISFR) The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt Status Flag for each pin is also visible in the corresponding Pin Control Register, and each flag can be cleared in either location. Address: Base address + A0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ISF W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_ISFR field descriptions Field Description 31–0 ISF Interrupt Status Flag Each bit in the field indicates the detection of the configured interrupt of the same number as the field. 0 Configured interrupt is not detected. 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. 11.6 Functional description 11.6.1 Pin control Each port pin has a corresponding pin control register, PORT_PCRn, associated with it. The upper half of the pin control register configures the pin's capability to either interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as well as a logic level occurring on the port pin. It also includes a flag to indicate that an interrupt has occurred. The lower half of the pin control register configures the following functions for each pin within the 32-bit port. • Pullup or pulldown enable on selected pins • Drive strength and slew rate configuration on selected pins Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 281 General Business Information

Page 282

• Open drain enable on selected pins • Passive input filter enable on selected pins • Pin Muxing mode The functions apply across all digital Pin Muxing modes and individual peripherals do not override the configuration in the pin control register. For example, if an I2C function is enabled on a pin, that does not override the pullup or open drain configuration for that pin. When the Pin Muxing mode is configured for analog or is disabled, all the digital functions on that pin are disabled. This includes the pullup and pulldown enables, digital output buffer enable, digital input buffer enable, and passive filter enable. A lock field also exists that allows the configuration for each pin to be locked until the next system reset. When locked, writes to the lower half of that pin control register are ignored, although a bus error is not generated on an attempted write to a locked register. The configuration of each pin control register is retained when the PORT module is disabled. 11.6.2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to sixteen pins, all with the same value. Registers that are locked cannot be written using the global pin control registers. The global pin control registers are designed to enable software to quickly configure multiple pins within the one port for the same peripheral function. However, the interrupt functions cannot be configured using the global pin control registers. The global pin control registers are write-only registers, that always read as zero. 11.6.3 External interrupts The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled. Each pin can be individually configured for any of the following external interrupt modes: • Interrupt disabled, default out of reset • Active high level sensitive interrupt • Active low level sensitive interrupt Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 282 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 283

• Rising edge sensitive interrupt • Falling edge sensitive interrupt • Rising and falling edge sensitive interrupt • Rising edge sensitive DMA request • Falling edge sensitive DMA request • Rising and falling edge sensitive DMA request The interrupt status flag is set when the configured edge or level is detected on the output of the pin. When not in Stop mode, the input is first synchronized to the bus clock to detect the configured level or edge transition. The PORT module generates a single interrupt that asserts when the interrupt status flag is set for any enabled interrupt for that port. The interrupt negates after the interrupt status flags for all enabled interrupts have been cleared by writing a logic 0 to the ISF flag in the PORT_PCRn register. The PORT module generates a single DMA request that asserts when the interrupt status flag is set for any enabled DMA request in that port. The DMA request negates after the DMA transfer is completed, because that clears the interrupt status flags for all enabled DMA requests. During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously set if the required level or edge is detected. This also generates an asynchronous wakeup signal to exit the Low-Power mode. Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 283 General Business Information

Page 284

Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 284 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 285

Chapter 12 System Integration Module (SIM) 12.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The System Integration Module (SIM) provides system control and chip configuration registers. 12.1.1 Features Features of the SIM include: • System clocking configuration • System clock divide values • Architectural clock gating control • USB clock selection and divide values • SDHC clock source selection • Ethernet 1588 timestamp and RMII clock source selection • Flash and system RAM size configuration • USB regulator configuration • FlexTimer external clock, hardware trigger, and fault source selection • UART0 and UART1 receive/transmit source selection/configuration K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 285 General Business Information

Page 286

12.2 Memory map and register definition The SIM module contains many fields for selecting the clock source and dividers for various module clocks. See the Clock Distribution chapter for more information, including block diagrams and clock definitions. NOTE The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers. SIM memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_7000 System Options Register 1 (SIM_SOPT1) 32 R/W See section 12.2.1/287 4004_7004 SOPT1 Configuration Register (SIM_SOPT1CFG) 32 R/W 0_0000 _0000h 12.2.2/289 4004_8004 System Options Register 2 (SIM_SOPT2) 32 R/W 0000_1000 _1000h 12.2.3/290 4004_800C System Options Register 4 (SIM_SOPT4) 32 R/W 0_0000 _0000h 12.2.4/293 4004_8010 System Options Register 5 (SIM_SOPT5) 32 R/W 0_0000 _0000h 12.2.5/295 4004_8018 System Options Register 7 (SIM_SOPT7) 32 R/W 0_0000 _0000h 12.2.6/297 4004_8024 System Device Identification Register (SIM_SDID) 32 R Undefined 12.2.7/299 4004_8028 System Clock Gating Control Register 1 (SIM_SCGC1) 32 R/W 0_0000 _0000h 12.2.8/300 4004_802C System Clock Gating Control Register 2 (SIM_SCGC2) 32 R/W 0_0000 _0000h 12.2.9/301 4004_8030 System Clock Gating Control Register 3 (SIM_SCGC3) 32 R/W 0_0000 _0000h 12.2.10/302 4004_8034 System Clock Gating Control Register 4 (SIM_SCGC4) 32 R/W E010_0030 _E010 _0030h 12.2.11/304 4004_8038 System Clock Gating Control Register 5 (SIM_SCGC5) 32 R/W 0_0040_1824 _0182h 12.2.12/306 4004_803C System Clock Gating Control Register 6 (SIM_SCGC6) 32 R/W 4000_0001 _4000_0001h 12.2.13/308 4004_8040 System Clock Gating Control Register 7 (SIM_SCGC7) 32 R/W 0_0000 _0077h 12.2.14/310 4004_8044 System Clock Divider Register 1 (SIM_CLKDIV1) 32 R/W See section 12.2.15/311 Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 286 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 287

SIM memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_8048 System Clock Divider Register 2 (SIM_CLKDIV2) 32 R/W 0_0000 _0000h 12.2.16/314 4004_804C Flash Configuration Register 1 (SIM_FCFG1) 32 R See section 12.2.17/314 4004_8050 Flash Configuration Register 2 (SIM_FCFG2) 32 R See section 12.2.18/317 4004_8054 Unique Identification Register High (SIM_UIDH) 32 R See section 12.2.19/318 4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) 32 R See section 12.2.20/319 4004_805C Unique Identification Register Mid Low (SIM_UIDML) 32 R See section 12.2.21/319 4004_8060 Unique Identification Register Low (SIM_UIDL) 32 R See section 12.2.22/320 12.2.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD. Address: 4004_7000h base + 0h offset = 4004_7000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R USBREGEN USBSSTBY USBVSTBY 0 OSC32KSEL 0 W Reset 1* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RAMSIZE 0 Reserved W Reset 1* 1* 1* 1* 0* 0* 0* 0* 0* 0* 1* 1* 1* 1* 1* 1*

Notes: Reset value loaded during System Reset from Flash IFR. • Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 287 General Business Information

Page 288

SIM_SOPT1 field descriptions Field Description 31 USBREGEN USB voltage regulator enable Controls whether the USB voltage regulator is enabled. 0 USB voltage regulator is disabled. 1 USB voltage regulator is enabled. 30 USBSSTBY USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. Controls whether the USB voltage regulator is placed in standby mode during Stop, VLPS, LLS and VLLS modes. 0 USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. 1 USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. 29 USBVSTBY USB voltage regulator in standby mode during VLPR and VLPW modes Controls whether the USB voltage regulator is placed in standby mode during VLPR and VLPW modes. 0 USB voltage regulator not in standby during VLPR and VLPW modes. 1 USB voltage regulator in standby during VLPR and VLPW modes. 28–20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19–18 OSC32KSEL 32K oscillator clock select Selects the 32 kHz clock source (ERCLK32K) for TSI,and LPTMR. This bit is reset only for POR/LVD. 00 System oscillator (OSC32KCLK) 01 Reserved 10 RTC 32.768kHz oscillator 11 LPO 1 kHz 17–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15–12 RAMSIZE RAM size This field specifies the amount of system RAM available on the device. 0000 Undefined 0001 8 KBytes 0010 Undefined 0011 16 KBytes 0100 Undefined 0101 32 KBytes 0110 Undefined 0111 64 KBytes 1000 Undefined 1001 128 KBytes 1010 Undefined 1011 Undefined 1100 Undefined 1101 Undefined Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 288 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 289

SIM_SOPT1 field descriptions (continued) Field Description 1110 Undefined 1111 Undefined 11–6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5–0 Reserved This field is reserved. 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG) NOTE The SOPT1CFG register is reset on System Reset not VLLS. Address: 4004_7000h base + 4h offset = 4004_7004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 USSWE UVSWE URWE 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT1CFG field descriptions Field Description 31–27 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26 USSWE USB voltage regulator stop standby write enable Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written. This register bit clears after a write to USBSSTBY. 0 SOPT1 USBSSTBY cannot be written. 1 SOPT1 USBSSTBY can be written. 25 UVSWE USB voltage regulator VLP standby write enable Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written. This register bit clears after a write to USBVSTBY. Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 289 General Business Information

Page 290

SIM_SOPT1CFG field descriptions (continued) Field Description 0 SOPT1 USBVSTBY cannot be written. 1 SOPT1 USBVSTBY can be written. 24 URWE USB voltage regulator enable write enable Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This register bit clears after a write to USBREGEN. 0 SOPT1 USBREGEN cannot be written. 1 SOPT1 USBREGEN can be written. 23–10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.2.3 System Options Register 2 (SIM_SOPT2) SOPT2 contains the controls for selecting many of the module clock source options on this device. See the Clock Distribution chapter for more information including clocking diagrams and definitions of device clocks. Address: 4004_7000h base + 1004h offset = 4004_8004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SDHCSRC 0 TIMESRC RMIISRC USBSRC 0 PLLFLLSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TRACECLKSE L PTD7PAD 0 FBSL CLKOUTSEL RTCCLKOUTS EL 0 W Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 290 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 291

SIM_SOPT2 field descriptions Field Description 31–30 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 29–28 SDHCSRC SDHC clock source select Selects the clock source for the SDHC clock . 00 Core/system clock. 01 MCGPLLCLK/MCGFLLCLK clock 10 OSCERCLK clock 11 External bypass clock (SDHC0_CLKIN) 27–22 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 21–20 TIMESRC IEEE 1588 timestamp clock source select Selects the clock source for the Ethernet timestamp clock. 00 Core/system clock. 01 MCGPLLCLK/MCGFLLCLK clock 10 OSCERCLK clock 11 External bypass clock (ENET_1588_CLKIN). 19 RMIISRC RMII clock source select Selects the clock source for the Ethernet RMII interface 0 EXTAL clock 1 External bypass clock (ENET_1588_CLKIN). 18 USBSRC USB clock source select Selects the clock source for the USB 48 MHz clock. 0 External bypass clock (USB_CLKIN). 1 MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider. See the SIM_CLKDIV2[USBFRAC, USBDIV] descriptions. 17 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 16 PLLFLLSEL PLL/FLL clock select Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking options. 0 MCGFLLCLK clock 1 MCGPLLCLK clock 15–13 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12 TRACECLKSEL Debug trace clock select Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace clock source. 0 MCGOUTCLK 1 Core/system clock Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 291 General Business Information

Page 292

SIM_SOPT2 field descriptions (continued) Field Description 11 PTD7PAD PTD7 pad drive strength Controls the output drive strength of the PTD7 pin by selecting either one or two pads to drive it. 0 Single-pad drive strength for PTD7. 1 Double pad drive strength for PTD7. 10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9–8 FBSL FlexBus security level If flash security is enabled, then this field affects what CPU operations can access off-chip via the FlexBus interface. This field has no effect if flash security is not enabled. 00 All off-chip accesses (instruction and data) via the FlexBus are disallowed. 01 All off-chip accesses (instruction and data) via the FlexBus are disallowed. 10 Off-chip instruction accesses are disallowed. Data accesses are allowed. 11 Off-chip instruction accesses and data accesses are allowed. 7–5 CLKOUTSEL CLKOUT select Selects the clock to output on the CLKOUT pin. 000 FlexBus CLKOUT 001 Reserved 010 Flash clock 011 LPO clock (1 kHz) 100 MCGIRCLK 101 RTC 32.768kHz clock 110 OSCERCLK0 111 Reserved 4 RTCCLKOUTSEL RTC clock out select Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the RTC_CLKOUT pin. 0 RTC 1 Hz clock is output on the RTC_CLKOUT pin. 1 RTC 32.768kHz clock is output on the RTC_CLKOUT pin. 3–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 292 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 293

12.2.4 System Options Register 4 (SIM_SOPT4) Address: 4004_7000h base + 100Ch offset = 4004_800Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 FTM0TRG1SR C FTM0TRG0SR C 0 FTM2CLKSEL FTM1CLKSEL FTM0CLKSEL 0 FTM2CH0SRC FTM1CH0SRC 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FTM2FLT0 0 FTM1FLT0 0 FTM0FLT2 FTM0FLT1 FTM0FLT0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT4 field descriptions Field Description 31–30 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 29 FTM0TRG1SRC FlexTimer 0 Hardware Trigger 1 Source Select Selects the source of FTM0 hardware trigger 1. 0 PDB output trigger 1 drives FTM0 hardware trigger 1 1 FTM2 channel match drives FTM0 hardware trigger 1 28 FTM0TRG0SRC FlexTimer 0 Hardware Trigger 0 Source Select Selects the source of FTM0 hardware trigger 0. 0 HSCMP0 output drives FTM0 hardware trigger 0 1 FTM1 channel match drives FTM0 hardware trigger 0 27 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26 FTM2CLKSEL FlexTimer 2 External Clock Pin Select Selects the external pin used to drive the clock to the FTM2 module. NOTE: The selected pin must also be configured for the FTM2 module external clock function through the appropriate pin control register in the port control module. 0 FTM2 external clock driven by FTM_CLK0 pin. 1 FTM2 external clock driven by FTM_CLK1 pin. 25 FTM1CLKSEL FTM1 External Clock Pin Select Selects the external pin used to drive the clock to the FTM1 module. Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 293 General Business Information

Page 294

SIM_SOPT4 field descriptions (continued) Field Description NOTE: The selected pin must also be configured for the FTM external clock function through the appropriate pin control register in the port control module. 0 FTM_CLK0 pin 1 FTM_CLK1 pin 24 FTM0CLKSEL FlexTimer 0 External Clock Pin Select Selects the external pin used to drive the clock to the FTM0 module. NOTE: The selected pin must also be configured for the FTM external clock function through the appropriate pin control register in the port control module. 0 FTM_CLK0 pin 1 FTM_CLK1 pin 23–22 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 21–20 FTM2CH0SRC FTM2 channel 0 input capture source select Selects the source for FTM2 channel 0 input capture. NOTE: When the FTM is not in input capture mode, clear this field. 00 FTM2_CH0 signal 01 CMP0 output 10 CMP1 output 11 Reserved 19–18 FTM1CH0SRC FTM1 channel 0 input capture source select Selects the source for FTM1 channel 0 input capture. NOTE: When the FTM is not in input capture mode, clear this field. 00 FTM1_CH0 signal 01 CMP0 output 10 CMP1 output 11 USB start of frame pulse 17–9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8 FTM2FLT0 FTM2 Fault 0 Select Selects the source of FTM2 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate PORTx pin control register. 0 FTM2_FLT0 pin 1 CMP0 out 7–5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 FTM1FLT0 FTM1 Fault 0 Select Selects the source of FTM1 fault 0. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 294 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 295

SIM_SOPT4 field descriptions (continued) Field Description NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 FTM1_FLT0 pin 1 CMP0 out 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 FTM0FLT2 FTM0 Fault 2 Select Selects the source of FTM0 fault 2. NOTE: The pin source for fault 2 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 FTM0_FLT2 pin 1 CMP2 out 1 FTM0FLT1 FTM0 Fault 1 Select Selects the source of FTM0 fault 1. NOTE: The pin source for fault 1 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 FTM0_FLT1 pin 1 CMP1 out 0 FTM0FLT0 FTM0 Fault 0 Select Selects the source of FTM0 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 FTM0_FLT0 pin 1 CMP0 out 12.2.5 System Options Register 5 (SIM_SOPT5) Address: 4004_7000h base + 1010h offset = 4004_8010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 UART1RXSR C UART1TXSR C UART0RXSR C UART0TXSR C W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 295 General Business Information

Page 296

SIM_SOPT5 field descriptions Field Description 31–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7–6 UART1RXSRC UART 1 receive data source select Selects the source for the UART 1 receive data. 00 UART1_RX pin 01 CMP0 10 CMP1 11 Reserved 5–4 UART1TXSRC UART 1 transmit data source select Selects the source for the UART 1 transmit data. 00 UART1_TX pin 01 UART1_TX pin modulated with FTM1 channel 0 output 10 UART1_TX pin modulated with FTM2 channel 0 output 11 Reserved 3–2 UART0RXSRC UART 0 receive data source select Selects the source for the UART 0 receive data. 00 UART0_RX pin 01 CMP0 10 CMP1 11 Reserved 1–0 UART0TXSRC UART 0 transmit data source select Selects the source for the UART 0 transmit data. 00 UART0_TX pin 01 UART0_TX pin modulated with FTM1 channel 0 output 10 UART0_TX pin modulated with FTM2 channel 0 output 11 Reserved Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 296 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 297

12.2.6 System Options Register 7 (SIM_SOPT7) Address: 4004_7000h base + 1018h offset = 4004_8018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ADC1ALTTRGE N 0 ADC1PRETRGS EL ADC1TRGSEL ADC0ALTTRGE N 0 ADC0PRETRGS EL ADC0TRGSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT7 field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15 ADC1ALTTRGEN ADC1 alternate trigger enable Enable alternative conversion triggers for ADC1. 0 PDB trigger selected for ADC1 1 Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. 14–13 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12 ADC1PRETRGSEL ADC1 pre-trigger select Selects the ADC1 pre-trigger source when alternative triggers are enabled through ADC1ALTTRGEN. 0 Pre-trigger A selected for ADC1. 1 Pre-trigger B selected for ADC1. 11–8 ADC1TRGSEL ADC1 trigger select Selects the ADC1 trigger source when alternative triggers are functional in stop and VLPS modes. 0000 PDB external trigger pin input (PDB0_EXTRG) 0001 High speed comparator 0 output 0010 High speed comparator 1 output 0011 High speed comparator 2 output 0100 PIT trigger 0 0101 PIT trigger 1 Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 297 General Business Information

Page 298

SIM_SOPT7 field descriptions (continued) Field Description 0110 PIT trigger 2 0111 PIT trigger 3 1000 FTM0 trigger 1001 FTM1 trigger 1010 FTM2 trigger 1011 Unused 1100 RTC alarm 1101 RTC seconds 1110 Low-power timer trigger 1111 Unused 7 ADC0ALTTRGEN ADC0 alternate trigger enable Enable alternative conversion triggers for ADC0. 0 PDB trigger selected for ADC0. 1 Alternate trigger selected for ADC0. 6–5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 ADC0PRETRGSEL ADC0 pretrigger select Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN. 0 Pre-trigger A 1 Pre-trigger B 3–0 ADC0TRGSEL ADC0 trigger select Selects the ADC0 trigger source when alternative triggers are functional in stop and VLPS modes. . 0000 PDB external trigger pin input (PDB0_EXTRG) 0001 High speed comparator 0 output 0010 High speed comparator 1 output 0011 High speed comparator 2 output 0100 PIT trigger 0 0101 PIT trigger 1 0110 PIT trigger 2 0111 PIT trigger 3 1000 FTM0 trigger 1001 FTM1 trigger 1010 FTM2 trigger 1011 Unused 1100 RTC alarm 1101 RTC seconds 1110 Low-power timer trigger 1111 Unused Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 298 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 299

12.2.7 System Device Identification Register (SIM_SDID) Address: 4004_7000h base + 1024h offset = 4004_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R REVID 0 0 0 1 0 FAMID PINID W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • SIM_SDID field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15–12 REVID Device revision number Specifies the silicon implementation number for the device. 11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6–4 FAMID Kinetis family identification Specifies the Kinetis family of the device. 000 K10 001 K20 010 K30 011 K40 100 K60 101 Reserved 110 K50and K52 111 K51and K53 Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 299 General Business Information

Page 300

SIM_SDID field descriptions (continued) Field Description 3–0 PINID Pincount identification Specifies the pincount of the device. 0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 80-pin 0111 81-pin 1000 100-pin 1001 121-pin 1010 144-pin 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved 12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1) Address: 4004_7000h base + 1028h offset = 4004_8028h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 UART5 UART4 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SCGC1 field descriptions Field Description 31–25 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 24 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 300 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 301

SIM_SCGC1 field descriptions (continued) Field Description 23–22 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 21 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 20–12 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 11 UART5 UART5 Clock Gate Control This bit controls the clock gate to the UART5 module. 0 Clock disabled 1 Clock enabled 10 UART4 UART4 Clock Gate Control This bit controls the clock gate to the UART4 module. 0 Clock disabled 1 Clock enabled 9–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2) Address: 4004_7000h base + 102Ch offset = 4004_802Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DAC1 DAC0 0 ENET W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 301 General Business Information

Page 302

SIM_SCGC2 field descriptions Field Description 31–14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 DAC1 DAC1 Clock Gate Control This bit controls the clock gate to the DAC1 module. 0 Clock disabled 1 Clock enabled 12 DAC0 DAC0 Clock Gate Control This bit controls the clock gate to the DAC0 module. 0 Clock disabled 1 Clock enabled 11–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 ENET ENET Clock Gate Control This bit controls the clock gate to the ENET module. 0 Clock disabled 1 Clock enabled 12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3) Address: 4004_7000h base + 1030h offset = 4004_8030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 ADC1 0 0 FTM2 0 SDHC 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SPI2 0 FLEXCAN1 0 RNGA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SCGC3 field descriptions Field Description 31 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 302 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 303

SIM_SCGC3 field descriptions (continued) Field Description 30 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 29–28 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 27 ADC1 ADC1 Clock Gate Control This bit controls the clock gate to the ADC1 module. 0 Clock disabled 1 Clock enabled 26 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 25 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 24 FTM2 FTM2 Clock Gate Control This bit controls the clock gate to the FTM2 module. 0 Clock disabled 1 Clock enabled 23–18 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 17 SDHC SDHC Clock Gate Control This bit controls the clock gate to the SDHC module. 0 Clock disabled 1 Clock enabled 16–13 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12 SPI2 SPI2 Clock Gate Control This bit controls the clock gate to the SPI2 module. 0 Clock disabled 1 Clock enabled 11–5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 FLEXCAN1 FlexCAN1 Clock Gate Control This bit controls the clock gate to the FlexCAN1 module. 0 Clock disabled 1 Clock enabled 3–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 RNGA RNGA Clock Gate Control This bit controls the clock gate to the RNGA module. Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 303 General Business Information

Page 304

SIM_SCGC3 field descriptions (continued) Field Description 0 Clock disabled 1 Clock enabled 12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4) Address: 4004_7000h base + 1034h offset = 4004_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 1 LLWU 0 VREF CMP USBOTG 0 W Reset 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 UART3 UART2 UART1 UART0 0 I2C1 I2C0 1 0 CMT EWM 0 W Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 SIM_SCGC4 field descriptions Field Description 31–29 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 28 LLWU LLWU Clock Gate Control This bit controls software access to the LLWU module. 0 Access disabled 1 Access enabled 27–21 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 20 VREF VREF Clock Gate Control This bit controls the clock gate to the VREF module. 0 Clock disabled 1 Clock enabled 19 CMP Comparator Clock Gate Control This bit controls the clock gate to the comparator module. 0 Clock disabled 1 Clock enabled Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 304 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 305

SIM_SCGC4 field descriptions (continued) Field Description 18 USBOTG USB Clock Gate Control This bit controls the clock gate to the USB module. 0 Clock disabled 1 Clock enabled 17–14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 UART3 UART3 Clock Gate Control This bit controls the clock gate to the UART3 module. 0 Clock disabled 1 Clock enabled 12 UART2 UART2 Clock Gate Control This bit controls the clock gate to the UART2 module. 0 Clock disabled 1 Clock enabled 11 UART1 UART1 Clock Gate Control This bit controls the clock gate to the UART1 module. 0 Clock disabled 1 Clock enabled 10 UART0 UART0 Clock Gate Control This bit controls the clock gate to the UART0 module. 0 Clock disabled 1 Clock enabled 9–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7 I2C1 I2C1 Clock Gate Control This bit controls the clock gate to the I 2 C1 module. 0 Clock disabled 1 Clock enabled 6 I2C0 I2C0 Clock Gate Control This bit controls the clock gate to the I 2 C0 module. 0 Clock disabled 1 Clock enabled 5–4 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 305 General Business Information

Page 306

SIM_SCGC4 field descriptions (continued) Field Description 2 CMT CMT Clock Gate Control This bit controls the clock gate to the CMT module. 0 Clock disabled 1 Clock enabled 1 EWM EWM Clock Gate Control This bit controls the clock gate to the EWM module. 0 Clock disabled 1 Clock enabled 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5) Address: 4004_7000h base + 1038h offset = 4004_8038h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 1 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PORTE PORTD PORTC PORTB PORTA 1 0 TSI 0 0 1 LPTIMER W Reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 SIM_SCGC5 field descriptions Field Description 31–19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 17–14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 PORTE Port E Clock Gate Control This bit controls the clock gate to the Port E module. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 306 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 307

SIM_SCGC5 field descriptions (continued) Field Description 0 Clock disabled 1 Clock enabled 12 PORTD Port D Clock Gate Control This bit controls the clock gate to the Port D module. 0 Clock disabled 1 Clock enabled 11 PORTC Port C Clock Gate Control This bit controls the clock gate to the Port C module. 0 Clock disabled 1 Clock enabled 10 PORTB Port B Clock Gate Control This bit controls the clock gate to the Port B module. 0 Clock disabled 1 Clock enabled 9 PORTA Port A Clock Gate Control This bit controls the clock gate to the Port A module. 0 Clock disabled 1 Clock enabled 8–7 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 TSI TSI Clock Gate Control This bit controls the clock gate to the TSI module. 0 Clock disabled 1 Clock enabled 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3–2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 0 LPTIMER Low Power Timer Access Control This bit controls software access to the Low Power Timer module. 0 Access disabled 1 Access enabled Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 307 General Business Information

Page 308

12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 1 RTC 0 ADC0 0 FTM1 FTM0 PIT PDB USBDCD 0 CRC 0 W Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R I2S 0 SPI1 SPI0 0 0 0 FLEXCAN0 0 DMAMUX FTFL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SIM_SCGC6 field descriptions Field Description 31 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 29 RTC RTC Access Control This bit controls software access and interrupts to the RTC module. 0 Access and interrupts disabled 1 Access and interrupts enabled 28 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 27 ADC0 ADC0 Clock Gate Control This bit controls the clock gate to the ADC0 module. 0 Clock disabled 1 Clock enabled 26 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 25 FTM1 FTM1 Clock Gate Control This bit controls the clock gate to the FTM1 module. 0 Clock disabled 1 Clock enabled 24 FTM0 FTM0 Clock Gate Control This bit controls the clock gate to the FTM0 module. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 308 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 309

SIM_SCGC6 field descriptions (continued) Field Description 0 Clock disabled 1 Clock enabled 23 PIT PIT Clock Gate Control This bit controls the clock gate to the PIT module. 0 Clock disabled 1 Clock enabled 22 PDB PDB Clock Gate Control This bit controls the clock gate to the PDB module. 0 Clock disabled 1 Clock enabled 21 USBDCD USB DCD Clock Gate Control This bit controls the clock gate to the USB DCD module. 0 Clock disabled 1 Clock enabled 20–19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 CRC CRC Clock Gate Control This bit controls the clock gate to the CRC module. 0 Clock disabled 1 Clock enabled 17–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15 I2S I2S Clock Gate Control This bit controls the clock gate to the I 2 S module. 0 Clock disabled 1 Clock enabled 14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 SPI1 SPI1 Clock Gate Control This bit controls the clock gate to the SPI1 module. 0 Clock disabled 1 Clock enabled 12 SPI0 SPI0 Clock Gate Control This bit controls the clock gate to the SPI0 module. 0 Clock disabled 1 Clock enabled Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 309 General Business Information

Page 310

SIM_SCGC6 field descriptions (continued) Field Description 11–10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8–5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 FLEXCAN0 FlexCAN0 Clock Gate Control This bit controls the clock gate to the FlexCAN0 module. 0 Clock disabled 1 Clock enabled 3–2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 DMAMUX DMA Mux Clock Gate Control This bit controls the clock gate to the DMA Mux module. 0 Clock disabled 1 Clock enabled 0 FTFL Flash Memory Clock Gate Control This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory is clock gated, but entry into low power modes is blocked. 0 Clock disabled 1 Clock enabled 12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7) Address: 4004_7000h base + 1040h offset = 4004_8040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 MPU DMA FLEXBUS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 310 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 311

SIM_SCGC7 field descriptions Field Description 31–3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 MPU MPU Clock Gate Control This bit controls the clock gate to the MPU module. 0 Clock disabled 1 Clock enabled 1 DMA DMA Clock Gate Control This bit controls the clock gate to the DMA module. 0 Clock disabled 1 Clock enabled 0 FLEXBUS FlexBus Clock Gate Control This bit controls the clock gate to the FlexBus module. 0 Clock disabled 1 Clock enabled 12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1) NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode. Address: 4004_7000h base + 1044h offset = 4004_8044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R OUTDIV1 OUTDIV2 OUTDIV3 OUTDIV4 0 W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 1* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

Notes: Reset value loaded during Syetem Reset from FTFL_FOPT[LPBOOT]. • SIM_CLKDIV1 field descriptions Field Description 31–28 OUTDIV1 Clock 1 output divider value This field sets the divide value for the core/system clock. At the end of reset, it is loaded with either 0000 or 0111 depending on FTFL_FOPT[LPBOOT]. 0000 Divide-by-1. Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 311 General Business Information

Page 312

SIM_CLKDIV1 field descriptions (continued) Field Description 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 27–24 OUTDIV2 Clock 2 output divider value This field sets the divide value for the bus clock. At the end of reset, it is loaded with either 0000 or 0111 depending on FTFL_FOPT[LPBOOT]. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 23–20 OUTDIV3 Clock 3 output divider value This field sets the divide value for the FlexBus clock driven to the external pin (FB_CLK). At the end of reset, it is loaded with either 0001 or 1111 depending on FTFL_FOPT[LPBOOT]. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 312 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 313

SIM_CLKDIV1 field descriptions (continued) Field Description 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 19–16 OUTDIV4 Clock 4 output divider value This field sets the divide value for the flash clock. At the end of reset, it is loaded with either 0001 or 1111 depending on FTFL_FOPT[LPBOOT]. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 15–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 313 General Business Information

Page 314

12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2) Address: 4004_7000h base + 1048h offset = 4004_8048h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 USBDIV USBFRAC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_CLKDIV2 field descriptions Field Description 31–4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3–1 USBDIV USB clock divider divisor This field sets the divide value for the fractional clock divider when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] 0 USBFRAC USB clock divider fraction This field sets the fraction multiply value for the fractional clock divider when the MCGFLLCLK/ MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] 12.2.17 Flash Configuration Register 1 (SIM_FCFG1) For devices with FlexNVM: The reset value of EESIZE and DEPART are based on user programming in user IFR via the PGMPART flash command. For devices with program flash only: The EESIZE and DEPART filelds are not applicable. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 314 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 315

Address: 4004_7000h base + 104Ch offset = 4004_804Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R NVMSIZE PFSIZE 0 EESIZE W Reset 1* 1* 1* 1* 1* 1* 1* 1* 0* 0* 0* 0* 1* 1* 1* 1* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DEPART 0 FLASHDOZE FLASHDIS W Reset 0* 0* 0* 0* 1* 1* 1* 1* 0* 0* 0* 0* 0* 0* 0* 0*

Notes: Reset value loaded during System Reset from Flash IFR. • SIM_FCFG1 field descriptions Field Description 31–28 NVMSIZE FlexNVM size This field specifies the amount of FlexNVM memory available on the device . Undefined values are reserved. 0000 0 KB of FlexNVM 0111 128 KB of FlexNVM, 32 KB protection region 1001 256 KB of FlexNVM, 32 KB protection region 27–24 PFSIZE Program flash size This field specifies the amount of program flash memory available on the device . Undefined values are reserved. 0111 128 KB of program flash, 4 KB protection region 1001 256 KB of program flash, 8 KB protection region 1011 512 KB of program flash, 16 KB protection region 23–20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 315 General Business Information

Page 316

SIM_FCFG1 field descriptions (continued) Field Description 19–16 EESIZE EEPROM size EEPROM data size . 0000 Reserved 0001 Reserved 0010 4 KB 0011 0100 1 KB 0101 512 Bytes 0110 256 Bytes 0111 128 Bytes 1000 64 Bytes 1001 32 Bytes 1010-1110 Reserved 1111 0 Bytes 15–12 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 11–8 DEPART FlexNVM partition For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit description in FTFL chapter. For devices without FlexNVM: Reserved 7–2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 FLASHDOZE Flash Doze When set, Flash memory is disabled for the duration of Wait mode. An attempt by the DMA or other bus master to access the Flash when the Flash is disabled will result in a bus error. This bit should be clear during VLP modes. The Flash will be automatically enabled again at the end of Wait mode so interrupt vectors do not need to be relocated out of Flash memory. The wakeup time from Wait mode is extended when this bit is set. 0 Flash remains enabled during Wait mode 1 Flash is disabled for the duration of Wait mode 0 FLASHDIS Flash Disable Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. 0 Flash is enabled 1 Flash is disabled Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 316 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 317

12.2.18 Flash Configuration Register 2 (SIM_FCFG2) Address: 4004_7000h base + 1050h offset = 4004_8050h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SWAPPFLSH MAXADDR0 PFLSH MAXADDR1 W Reset 0* 1* 1* 1* 1* 1* 1* 1* 0* 1* 1* 1* 1* 1* 1* 1* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

Notes: Reset value loaded during System Reset from Flash IFR. • SIM_FCFG2 field descriptions Field Description 31 SWAPPFLSH Swap program flash For devices without FlexNVM: Indicates that swap is active . 0 Swap is not active. 1 Swap is active. 30–24 MAXADDR0 Max address block 0 Table continues on the next page... Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 317 General Business Information

Page 318

SIM_FCFG2 field descriptions (continued) Field Description This field concatenated with leading zeros indicates the first invalid address of flash block 0 (program flash 0). For example, if MAXADDR0 = 0x20 the first invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0 value for a device with 256 KB program flash in flash block 0. 23 PFLSH Program flash For devices with FlexNVM, this bit is always clear. For devices without FlexNVM, this bit is always set. 0 Physical flash block 1 is used as FlexNVM Reserved for devices without FlexNVM 1 Physical flash block 1 is used as program flash 22–16 MAXADDR1 Max address block 1 For devices with FlexNVM: This field concatenated with leading zeros plus the FlexNVM base address indicates the first invalid address of the FlexNVM (flash block 1). For example, if MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value for a device with 256 KB FlexNVM. For devices with program flash only: This field concatenated with leading zeros plus the value of the MAXADDR1 field indicates the first invalid address of the second program flash block (flash block 1). For example, if MAXADDR0 = MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be the MAXADDR1 value for a device with 512 KB program flash memory and no FlexNVM. 15–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.2.19 Unique Identification Register High (SIM_UIDH) Address: 4004_7000h base + 1054h offset = 4004_8054h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UID W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

Notes: Reset value loaded during System Reset from Flash IFR. • SIM_UIDH field descriptions Field Description 31–0 UID Unique Identification Unique identification for the device. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 318 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 319

12.2.20 Unique Identification Register Mid-High (SIM_UIDMH) Address: 4004_7000h base + 1058h offset = 4004_8058h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UID W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

Notes: Reset value loaded during System Reset from Flash IFR. • SIM_UIDMH field descriptions Field Description 31–0 UID Unique Identification Unique identification for the device. 12.2.21 Unique Identification Register Mid Low (SIM_UIDML) Address: 4004_7000h base + 105Ch offset = 4004_805Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UID W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
Notes: Reset value loaded during System Reset from Flash IFR. • SIM_UIDML field descriptions Field Description 31–0 UID Unique Identification Unique identification for the device. Chapter 12 System Integration Module (SIM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 319 General Business Information

Page 320

12.2.22 Unique Identification Register Low (SIM_UIDL) Address: 4004_7000h base + 1060h offset = 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UID W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

Notes: Reset value loaded during System Reset from Flash IFR. • SIM_UIDL field descriptions Field Description 31–0 UID Unique Identification Unique identification for the device. 12.3 Functional description For more information about the functions of SIM, see the Introduction section. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 320 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 321

Chapter 13 Reset Control Module (RCM) 13.1 Introduction This chapter describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. 13.2 Reset memory map and register descriptions The Reset Control Module (RCM) registers provide reset status information and reset filter control. RCM memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4007_F000 System Reset Status Register 0 (RCM_SRS0) 8 R 8282h 13.2.1/321 4007_F001 System Reset Status Register 1 (RCM_SRS1) 8 R 000h 13.2.2/323 4007_F004 Reset Pin Filter Control register (RCM_RPFC) 8 R/W 000h 13.2.3/324 4007_F005 Reset Pin Filter Width register (RCM_RPFW) 8 R/W 000h 13.2.4/325 4007_F007 Mode Register (RCM_MR) 8 R 000h 13.2.5/327 13.2.1 System Reset Status Register 0 (RCM_SRS0) This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: • POR (including LVD) — 0x82 K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 321 General Business Information

Page 322

• LVD (without POR) — 0x02 • VLLS mode wakeup due to RESET pin assertion — 0x41 • VLLS mode wakeup due to other wakeup sources — 0x01 • Other reset — a bit is set if its corresponding reset source caused the reset Address: 4007_F000h base + 0h offset = 4007_F000h Bit 7 6 5 4 3 2 1 0 Read POR PIN WDOG 0 LOL LOC LVD WAKEUP Write Reset 1 0 0 0 0 0 1 0 RCM_SRS0 field descriptions Field Description 7 POR Power-On Reset Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 Reset not caused by POR 1 Reset caused by POR 6 PIN External Reset Pin Indicates a reset has been caused by an active-low level on the external RESET pin. 0 Reset not caused by external reset pin 1 Reset caused by external reset pin 5 WDOG Watchdog Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog. 0 Reset not caused by watchdog timeout 1 Reset caused by watchdog timeout 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 LOL Loss-of-Lock Reset Indicates a reset has been caused by a loss of lock in the MCG PLL. See the MCG description for information on the loss-of-clock event. 0 Reset not caused by a loss of lock in the PLL 1 Reset caused by a loss of lock in the PLL 2 LOC Loss-of-Clock Reset Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the clock monitor. Table continues on the next page... Reset memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 322 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 323

RCM_SRS0 field descriptions (continued) Field Description 0 Reset not caused by a loss of external clock. 1 Reset caused by a loss of external clock. 1 LVD Low-Voltage Detect Reset If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is also set by POR. 0 Reset not caused by LVD trip or POR 1 Reset caused by LVD trip or POR 0 WAKEUP Low Leakage Wakeup Reset Indicates a reset has been caused by an enabled LLWU module wakeup source while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset except WAKEUP. 0 Reset not caused by LLWU module wakeup source 1 Reset caused by LLWU module wakeup source 13.2.2 System Reset Status Register 1 (RCM_SRS1) This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: • POR (including LVD) — 0x00 • LVD (without POR) — 0x00 • VLLS mode wakeup — 0x00 • Other reset — a bit is set if its corresponding reset source caused the reset Address: 4007_F000h base + 1h offset = 4007_F001h Bit 7 6 5 4 3 2 1 0 Read 0 0 SACKERR EZPT MDM_AP SW LOCKUP JTAG Write Reset 0 0 0 0 0 0 0 0 RCM_SRS1 field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... Chapter 13 Reset Control Module (RCM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 323 General Business Information

Page 324

RCM_SRS1 field descriptions (continued) Field Description 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 SACKERR Stop Mode Acknowledge Error Reset Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode. 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode 4 EZPT EzPort Reset Indicates a reset has been caused by EzPort receiving the RESET command while the device is in EzPort mode. 0 Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode 1 Reset caused by EzPort receiving the RESET command while the device is in EzPort mode 3 MDM_AP MDM-AP System Reset Request Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM-AP Control Register. 0 Reset not caused by host debugger system setting of the System Reset Request bit 1 Reset caused by host debugger system setting of the System Reset Request bit 2 SW Software Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register in the ARM core. 0 Reset not caused by software setting of SYSRESETREQ bit 1 Reset caused by software setting of SYSRESETREQ bit 1 LOCKUP Core Lockup Indicates a reset has been caused by the ARM core indication of a LOCKUP event. 0 Reset not caused by core LOCKUP event 1 Reset caused by core LOCKUP event 0 JTAG JTAG Generated Reset Indicates a reset has been caused by JTAG selection of certain IR codes: EZPORT, EXTEST, HIGHZ, and CLAMP. 0 Reset not caused by JTAG 1 Reset caused by JTAG 13.2.3 Reset Pin Filter Control register (RCM_RPFC) NOTE The reset values of bits 2-0 are for Chip POR only. They are unaffected by other reset types. Reset memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 324 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 325

NOTE The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled or when entering any low leakage stop mode . Address: 4007_F000h base + 4h offset = 4007_F004h Bit 7 6 5 4 3 2 1 0 Read 0 RSTFLTSS RSTFLTSRW Write Reset 0 0 0 0 0 0 0 0 RCM_RPFC field descriptions Field Description 7–3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 RSTFLTSS Reset Pin Filter Select in Stop Mode Selects how the reset pin filter is enabled in Stop and VLPS modes . 0 All filtering disabled 1 LPO clock filter enabled 1–0 RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes Selects how the reset pin filter is enabled in run and wait modes. 00 All filtering disabled 01 Bus clock filter enabled for normal operation 10 LPO clock filter enabled for normal operation 11 Reserved 13.2.4 Reset Pin Filter Width register (RCM_RPFW) NOTE The reset values of the bits in the RSTFLTSEL field are for Chip POR only. They are unaffected by other reset types. Address: 4007_F000h base + 5h offset = 4007_F005h Bit 7 6 5 4 3 2 1 0 Read 0 RSTFLTSEL Write Reset 0 0 0 0 0 0 0 0 Chapter 13 Reset Control Module (RCM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 325 General Business Information

Page 326

RCM_RPFW field descriptions Field Description 7–5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4–0 RSTFLTSEL Reset Pin Filter Bus Clock Select Selects the reset pin bus clock filter width. 00000 Bus clock filter count is 1 00001 Bus clock filter count is 2 00010 Bus clock filter count is 3 00011 Bus clock filter count is 4 00100 Bus clock filter count is 5 00101 Bus clock filter count is 6 00110 Bus clock filter count is 7 00111 Bus clock filter count is 8 01000 Bus clock filter count is 9 01001 Bus clock filter count is 10 01010 Bus clock filter count is 11 01011 Bus clock filter count is 12 01100 Bus clock filter count is 13 01101 Bus clock filter count is 14 01110 Bus clock filter count is 15 01111 Bus clock filter count is 16 10000 Bus clock filter count is 17 10001 Bus clock filter count is 18 10010 Bus clock filter count is 19 10011 Bus clock filter count is 20 10100 Bus clock filter count is 21 10101 Bus clock filter count is 22 10110 Bus clock filter count is 23 10111 Bus clock filter count is 24 11000 Bus clock filter count is 25 11001 Bus clock filter count is 26 11010 Bus clock filter count is 27 11011 Bus clock filter count is 28 11100 Bus clock filter count is 29 11101 Bus clock filter count is 30 11110 Bus clock filter count is 31 11111 Bus clock filter count is 32 Reset memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 326 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 327

13.2.5 Mode Register (RCM_MR) This register includes read-only status flags to indicate the state of the mode pins during the last Chip Reset. Address: 4007_F000h base + 7h offset = 4007_F007h Bit 7 6 5 4 3 2 1 0 Read 0 EZP_MS 0 Write Reset 0 0 0 0 0 0 0 0 RCM_MR field descriptions Field Description 7–2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 EZP_MS EZP_MS_B pin state Reflects the state of the EZP_MS pin during the last Chip Reset 0 Pin deasserted (logic 1) 1 Pin asserted (logic 0) 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Chapter 13 Reset Control Module (RCM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 327 General Business Information

Page 328

Reset memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 328 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 329

Chapter 14 System Mode Controller 14.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The system mode controller (SMC) is responsible for sequencing the system into and out of all low power stop and run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode. This chapter describes all the available low power modes, the sequence followed to enter/ exit each mode, and the functionality available while in each of the modes. The SMC is able to function during even the deepest low power modes. 14.2 Modes of operation The ARM CPU has three primary modes of operation: • Run • Sleep • Deep Sleep K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 329 General Business Information

Page 330

The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, wait and stop are the common terms used for the primary operating modes of Freescale microcontrollers. The following table shows the translation between the ARM CPU modes and the Freescale MCU power modes. ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. In addition, Freescale MCUs also augment stop, wait, and run modes in a number of ways. The power management controller (PMC) contains a run and a stop mode regulator. Run regulation is used in normal run, wait and stop modes. Stop mode regulation is used during all very low power and low leakage modes. During stop mode regulation, the bus frequencies are limited in the very low power modes. The SMC provides the user with multiple power options. The Very Low Power Run (VLPR) mode can drastically reduce run time power when maximum bus frequency is not required to handle the application needs. From Normal Run mode, the Run Mode (RUNM) field can be modified to change the MCU into VLPR mode when limited frequency is sufficient for the application. From VLPR mode, a corresponding wait (VLPW) and stop (VLPS) mode can be entered. Depending on the needs of the user application, a variety of stop modes are available that allow the state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. Several registers are used to configure the various modes of operation for the device. The following table describes the power modes available for the device. Table 14-1. Power modes Mode Description RUN The MCU can be run at full speed and the internal supply is fully regulated, that is, in run regulation. This mode is also referred to as Normal Run mode. WAIT The core clock is gated off. The system clock continues to operate. Bus clocks, if enabled, continue to operate. Run regulation is maintained. STOP The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. VLPR The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the Power Management chapter for details about the maximum allowable frequencies. Table continues on the next page... Modes of operation K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 330 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 331

Table 14-1. Power modes (continued) Mode Description VLPW The core clock is gated off. The system, bus, and flash clocks continue to operate, although their maximum frequency is restricted. See the Power Management chapter for details on the maximum allowable frequencies. VLPS The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. LLS The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by reducing the voltage to internal logic. Internal logic states are retained. VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic. All system RAM contents are retained and I/O states are held. Internal logic states are not retained. VLLS2 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid.The MCU is placed in a low leakage mode by powering down the internal logic and the system RAM3 partition. The system RAM2 partition can be optionally retained using VLLSCTRL[RAM2PO]. The system RAM1 partition contents are retained in this mode. Internal logic states are not retained. 1 VLLS1 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal logic states are not retained. 1. See the devices' chip configuration details for the size and location of the system RAM partitions. 14.3 Memory map and register descriptions Details follow about the registers related to the system mode controller. Different SMC registers reset on different reset types. Each register's description provides details. For more information about the types of reset on this chip, refer to the Reset section details. SMC memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4007_E000 Power Mode Protection register (SMC_PMPROT) 8 R/W 000h 14.3.1/332 4007_E001 Power Mode Control register (SMC_PMCTRL) 8 R/W 000h 14.3.2/333 4007_E002 VLLS Control register (SMC_VLLSCTRL) 8 R/W 033h 14.3.3/334 4007_E003 Power Mode Status register (SMC_PMSTAT) 8 R 011h 14.3.4/335 Chapter 14 System Mode Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 331 General Business Information

Page 332

14.3.1 Power Mode Protection register (SMC_PMPROT) This register provides protection for entry into any low-power run or stop mode. The enabling of the low-power run or stop mode occurs by configuring the Power Mode Control register (PMCTRL). The PMPROT register can be written only once after any system reset. If the MCU is configured for a disallowed or reserved power mode, the MCU remains in its current power mode. For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and the RUNM bits remain 00b, indicating the MCU is still in Normal Run mode. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 0h offset = 4007_E000h Bit 7 6 5 4 3 2 1 0 Read 0 AVLP 0 ALLS 0 AVLLS 0 Write Reset 0 0 0 0 0 0 0 0 SMC_PMPROT field descriptions Field Description 7–6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 AVLP Allow Very-Low-Power Modes Provided the appropriate control bits are set up in PMCTRL, this write-once bit allows the MCU to enter any very-low-power modes: VLPR, VLPW, and VLPS. 0 VLPR, VLPW and VLPS are not allowed 1 VLPR, VLPW and VLPS are allowed 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 ALLS Allow Low-Leakage Stop Mode This write once bit allows the MCU to enter any low-leakage stop mode (LLS), provided the appropriate control bits are set up in PMCTRL. 0 LLS is not allowed 1 LLS is allowed Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 332 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 333

SMC_PMPROT field descriptions (continued) Field Description 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 AVLLS Allow Very-Low-Leakage Stop Mode Provided the appropriate control bits are set up in PMCTRL, this write once bit allows the MCU to enter any very-low-leakage stop mode (VLLSx). 0 Any VLLSx mode is not allowed 1 Any VLLSx mode is allowed 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 14.3.2 Power Mode Control register (SMC_PMCTRL) The PMCTRL register controls entry into low-power run and stop modes, provided that the selected power mode is allowed via an appropriate setting of the protection (PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 1h offset = 4007_E001h Bit 7 6 5 4 3 2 1 0 Read LPWUI RUNM 0 STOPA STOPM Write Reset 0 0 0 0 0 0 0 0 SMC_PMCTRL field descriptions Field Description 7 LPWUI Low-Power Wake Up On Interrupt Causes the SMC to exit to normal RUN mode when any active MCU interrupt occurs while in a VLP mode (VLPR, VLPW or VLPS). NOTE: If VLPS mode was entered directly from RUN mode, the SMC will always exit back to normal RUN mode regardless of the LPWUI setting. NOTE: LPWUI must be modified only while the system is in RUN mode, that is, when PMSTAT=RUN. 0 The system remains in a VLP mode on an interrupt 1 The system exits to Normal RUN mode on an interrupt Table continues on the next page... Chapter 14 System Mode Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 333 General Business Information

Page 334

SMC_PMCTRL field descriptions (continued) Field Description 6–5 RUNM Run Mode Control When written, causes entry into the selected run mode. Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. This field is cleared by hardware on any exit to normal RUN mode. NOTE: RUNM must be set to VLPR only when PMSTAT=RUN. After being written to VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. NOTE: RUNM must be set to RUN only when PMSTAT=VLPR. After being written to RUN, RUNM should not be written back to VLPR until PMSTAT=RUN. 00 Normal Run mode (RUN) 01 Reserved 10 Very-Low-Power Run mode (VLPR) 11 Reserved 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 STOPA Stop Aborted When set, this read-only status bit indicates an interrupt or reset occured during the previous stop mode entry sequence, preventing the system from entering that mode. This bit is cleared by hardware at the beginning of any stop mode entry sequence and is set if the sequence was aborted. 0 The previous stop mode entry was successsful. 1 The previous stop mode entry was aborted. 2–0 STOPM Stop Mode Control When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. After any system reset, this field is cleared by hardware on any successful write to the PMPROT register. NOTE: When set to VLLSx, the VLLSM bits in the VLLSCTRL register is used to further select the particular VLLS submode which will be entered. NOTE: 000 Normal Stop (STOP) 001 Reserved 010 Very-Low-Power Stop (VLPS) 011 Low-Leakage Stop (LLS) 100 Very-Low-Leakage Stop (VLLSx) 101 Reserved 110 Reseved 111 Reserved 14.3.3 VLLS Control register (SMC_VLLSCTRL) The VLLSCTRL register controls features related to VLLS modes. Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 334 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 335

NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 2h offset = 4007_E002h Bit 7 6 5 4 3 2 1 0 Read 0 0 RAM2PO 0 VLLSM Write Reset 0 0 0 0 0 0 1 1 SMC_VLLSCTRL field descriptions Field Description 7–6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 RAM2PO RAM2 Power Option Controls powering of RAM partition 2 in VLLS2 mode. NOTE: See the device's chip configuration details for the size and location of RAM parition 2 0 RAM2 not powered in VLLS2 1 RAM2 powered in VLLS2 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2–0 VLLSM VLLS Mode Control Controls which VLLS sub-mode to enter if STOPM=VLLS. 000 Reserved 001 VLLS1 010 VLLS2 011 VLLS3 100 Reserved 101 Reserved 110 Reserved 111 Reserved 14.3.4 Power Mode Status register (SMC_PMSTAT) PMSTAT is a read-only, one-hot register which indicates the current power mode of the system. Chapter 14 System Mode Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 335 General Business Information

Page 336

NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 3h offset = 4007_E003h Bit 7 6 5 4 3 2 1 0 Read 0 PMSTAT Write Reset 0 0 0 0 0 0 0 1 SMC_PMSTAT field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6–0 PMSTAT NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS 000_0001 Current power mode is RUN 000_0010 Current power mode is STOP 000_0100 Current power mode is VLPR 000_1000 Current power mode is VLPW 001_0000 Current power mode is VLPS 010_0000 Current power mode is LLS 100_0000 Current power mode is VLLS 14.4 Functional description 14.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal run state. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 336 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 337

WAIT STOP RUN LLS VLLSx VLPS VLPR VLPW Any reset 4 6 7 3 1 2 8 10 11 9 5 Figure 14-5. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 14-7. Power mode transition triggers Transition # From To Trigger conditions 1 RUN WAIT Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note.1 WAIT RUN Interrupt or Reset Table continues on the next page... Chapter 14 System Mode Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 337 General Business Information

Page 338

Table 14-7. Power mode transition triggers (continued) Transition # From To Trigger conditions 2 RUN STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 STOP RUN Interrupt or Reset 3 RUN VLPR Reduce system, bus and core frequency to 2 MHz or less, Flash access limited to 1 MHz. Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10. VLPR RUN Set PMCTRL[RUNM]=00 or Interrupt with PMCTRL[LPWUI] =1 or Reset. 4 VLPR VLPW Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, which is controlled in System Control Register in ARM core. See note.1 VLPW VLPR Interrupt with PMCTRL[LPWUI]=0 5 VLPW RUN Interrupt with PMCTRL[LPWUI]=1 or Reset 6 VLPR VLPS PMCTRL[STOPM]=000 or 010, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 VLPS VLPR Interrupt with PMCTRL[LPWUI]=0 NOTE: If VLPS was entered directly from RUN, hardware will not allow this transition and will force exit back to RUN 7 RUN VLPS PMPROT[AVLP]=1, PMCTRL[STOPM]=010, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 VLPS RUN Interrupt with PMCTRL[LPWUI]=1 or Interrupt with PMCTRL[LPWUI]=0 and VLPS mode was entered directly from RUN or Reset 8 RUN VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, VLLSCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. VLLSx RUN Wakeup from enabled LLWU input source or RESET pin Table continues on the next page... Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 338 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 339

Table 14-7. Power mode transition triggers (continued) Transition # From To Trigger conditions 9 VLPR VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, VLLSCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. 10 RUN LLS PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. LLS RUN Wakeup from enabled LLWU input source or RESET pin. 11 VLPR LLS PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. 1. If debug is enabled, the core clock remains to support debug. 14.4.2 Power mode entry/exit sequencing When entering or exiting low-power modes, the system must conform to an orderly sequence to manage transitions safely. The SMC manages the system's entry into and exit from all power modes. The following diagram illustrates the connections of the SMC with other system components in the chip that are necessary to sequence the system through all power modes. Chapter 14 System Mode Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 339 General Business Information

Page 340

System Mode Controller (SMC) System Power (PMC) Low- Leakage Wakeup (LLWU) System Clocks (MCG) LP exit Flash CPU LP exit Clock Control Module (CCM) Module Memory Bus masters low power bus (non-CPU) Bus slaves low power bus Stop/Wait CCM low power bus MCG enable PMC low power bus Flash low power bus Reset Control (RCM) Module Figure 14-6. Low-power system components and connections 14.4.2.1 Stop mode entry sequence Entry into a low-power stop mode (Stop, VLPS, LLS, VLLSx) is initiated by CPU execution of the WFI instruction. After the instruction is executed, the following sequence occurs:

The CPU clock is gated off immediately.
Requests are made to all non-CPU bus masters to enter Stop mode.
After all masters have acknowledged they are ready to enter Stop mode, requests are made to all bus slaves to enter Stop mode.
After all slaves have acknowledged they are ready to enter Stop mode, all system and bus clocks are gated off.
Clock generators are disabled in the MCG.
The on-chip regulator in the PMC and internal power switches are configured to meet the power consumption goals for the targeted low-power mode. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 340 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 341

14.4.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR):

The on-chip regulator in the PMC and internal power switches are restored.
Clock generators are enabled in the MCG.
System and bus clocks are enabled to all masters and slaves.
The CPU clock is enabled and the CPU begins servicing the reset or interrupt that initiated the exit from the low-power stop mode. 14.4.2.3 Aborted stop mode entry If an interrupt or a reset occurs during a stop entry sequence, the SMC can abort the transition early and return to RUN mode without completely entering the stop mode. An aborted entry is possible only if the reset or interrupt occurs before the PMC begins the transition to stop mode regulation. After this point, the interrupt or reset is ignored until the PMC has completed its transition to stop mode regulation. When an aborted stop mode entry sequence occurs, the SMC's PMCTRL[STOPA] is set to 1. 14.4.2.4 Transition to wait modes For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-in- wait functionality have their clocks disabled in these configurations. 14.4.2.5 Transition from stop modes to Debug mode The debugger module supports a transition from STOP, WAIT, VLPS, and VLPW back to a Halted state when the debugger has been enabled, that is, ENBDM is 1. As part of this transition, system clocking is re-established and is equivalent to the normal RUN and VLPR mode clocking configuration. 14.4.3 Run modes The device contains two different run modes: • Run • Very Low-Power Run (VLPR) Chapter 14 System Mode Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 341 General Business Information

Page 342

14.4.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): • The processor reads the start SP (SP_main) from vector-table offset 0x000 • The processor reads the start PC from vector-table offset 0x004 • LR is set to 0xFFFF_FFFF. To reduce power in this mode, disable the clocks to unused modules using their corresponding clock gating control bits in the SIM's registers. 14.4.3.2 Very-Low Power Run (VLPR) mode In VLPR mode, the on-chip voltage regulator is put into a stop mode regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules using their corresponding clock gating control bits in the SIM's registers. Before entering this mode, the following conditions must be met: • The MCG must be configured in a mode which is supported during VLPR. See the Power Management details for information about these MCG modes. • All clock monitors in the MCG must be disabled. • The maximum frequencies of the system, bus, flash, and core are restricted. See the Power Management details about which frequencies are supported. • Mode protection must be set to allow VLP modes, that is, PMPROT[AVLP] is 1. • PMCTRL[RUNM] is set to 10b to enter VLPR. • Flash programming/erasing is not allowed. NOTE Do not change the clock frequency while in VLPR mode, because the regulator is slow responding and cannot manage fast load transitions. In addition, do not modify the clock source in the MCG module, the module clock enables in the SIM, or any clock divider registers. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 342 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 343

To reenter Normal Run mode, clear RUNM. The PMSTAT register is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode. If a higher execution frequency is desired, poll the PMSTAT register until it is set to RUN when returning from VLPR mode. VLPR mode also provides the option to return to run regulation if any interrupt occurs. Implement this option by setting Low-Power Wakeup On Interrupt (LPWUI) in the PMCTRL register. Any reset always causes an exit from VLPR and returns the device to RUN mode after the MCU exits its reset flow. The RUNM bits are cleared by hardware on any interrupt when LPWUI is set or on any reset. 14.4.4 Wait modes This device contains two different wait modes: • Wait • Very-Low Power Wait (VLPW) 14.4.4.1 WAIT mode WAIT mode is entered when the ARM core enters the Sleep-Now or Sleep-On-Exit modes while SLEEDEEP is cleared. The ARM CPU enters a low-power state in which it is not clocked, but peripherals continue to be clocked provided they are enabled. Clock gating to the peripheral is enabled via the SIM.. When an interrupt request occurs, the CPU exits WAIT mode and resumes processing in RUN mode, beginning with the stacking operations leading to the interrupt service routine. A system reset will cause an exit from WAIT mode, returning the device to normal RUN mode. 14.4.4.2 Very-Low-Power Wait (VLPW) mode VLPW is entered by the entering the Sleep-Now or Sleep-On-Exit mode while SLEEPDEEP is cleared and the MCU is in VLPR mode. Chapter 14 System Mode Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 343 General Business Information

Page 344

In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules by clearing the peripherals' corresponding clock gating control bits in the SIM. VLPR mode restrictions also apply to VLPW. VLPW mode provides the option to return to fully-regulated normal RUN mode if any enabled interrupt occurs. This is done by setting PMCTRL[LPWUI]. Wait for the PMSTAT register to set to RUN before increasing the frequency. If the LPWUI bit is clear, when an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. A system reset will cause an exit from VLPW mode, returning the device to normal RUN mode. 14.4.5 Stop modes This device contains a variety of stop modes to meet your application needs. The stop modes range from: • a stopped CPU, with all I/O, logic, and memory states retained, and certain asynchronous mode peripherals operating to: • a powered down CPU, with only I/O and a small register file retained, very few asynchronous mode peripherals operating, while the remainder of the MCU is powered down. The choice of stop mode depends upon the user's application, and how power usage and state retention versus functional needs may be traded off. The various stop modes are selected by setting the appropriate fields in PMPROT and PMCTRL. The selected stop mode mode is entered during the sleep-now or sleep-on-exit entry with the SLEEPDEEP bit set in the System Control Register in the ARM core. The available stop modes are: • Normal Stop (STOP) • Very-Low Power Stop (VLPS) • Low-Leakage Stop (LLS) • Very-Low-Leakage Stop (VLLSx) Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 344 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 345

14.4.5.1 STOP mode STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running. A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's Power Management chapter for peripheral, I/O, and memory operation in STOP mode. When an interrupt request occurs, the CPU exits STOP mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. A system reset will cause an exit from STOP mode, returning the device to normal RUN mode via an MCU reset. 14.4.5.2 Very-Low-Power Stop (VLPS) mode VLPS mode can be entered in one of two ways: • Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core while the MCU is in VLPR mode and STOPM=010 or 000 in the PMCTRL register. • Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core while the MCU is in normal RUN mode and STOPM=010 in the PMCTRL register. When VLPS is entered directly from RUN mode, exit to VLPR is disabled by hardware and the system will always exit back to RUN. In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR. A module capable of providing an asynchronous interrupt to the device takes the device out of VLPS and returns the device to VLPR mode, provided LPWUI is clear. If LPWUI is set, the device returns to normal RUN mode upon an interrupt request. PMSTAT must be set to RUN before allowing the system to return to a frequency higher than that allowed in VLPR mode. A system reset will also cause a VLPS exit, returning the device to normal RUN mode. Chapter 14 System Mode Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 345 General Business Information

Page 346

14.4.5.3 Low-Leakage Stop (LLS) mode Low-Leakage Stop (LLS) mode can be entered from normal RUN or VLPR modes. The MCU enters LLS mode if: • In Sleep-Now or Sleep-On-Exit mode, SLEEPDEEP is set in the System Control Register in the ARM core, and • The device is configured as shown in Table 14-7. In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put in a state-retention mode that does not allow them to operate while in LLS. Before entering LLS mode, the user should configure the low-leakage wakeup (LLWU) module to enable the desired wakeup sources. The available wakeup sources in LLS are detailed in the chip configuration details for this device. After wakeup from LLS, the device returns to normal RUN mode with a pending LLWU module interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wakeup flags to determine the source of the wakeup. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. An asserted RESET pin will cause an exit from LLS mode, returning the device to normal RUN mode. When LLS is exiting via the RESET pin, the PIN and WAKEUP bits are set in the SRS0 register of the reset control module (RCM). 14.4.5.4 Very-Low-Leakage Stop (VLLSx) modes This device contains these very low leakage modes: • VLLS3 • VLLS2 • VLLS1 VLLSx is often used in this document to refer to all of these modes. All VLLSx modes can be entered from normal RUN or VLPR modes. The MCU enters the configured VLLS mode if: • In Sleep-Now or Sleep-On-Exit mode, the SLEEPDEEP bit is set in the System Control Register in the ARM core, and • The device is configured as shown in Table 14-7. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 346 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 347

In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital logic is powered off. Before entering VLLS mode, the user should configure the low-leakage wakeup (LLWU) module to enable the desired wakeup sources. The available wakeup sources in VLLS are detailed in the chip configuration details for this device. After wakeup from VLLS, the device returns to normal RUN mode with a pending LLWU interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wakeup flags to determine the source of the wakeup. When entering VLLS, each I/O pin is latched as configured before executing VLLS. Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before the ACKISO bit in the PMC is set. An asserted RESET pin will cause an exit from any VLLS mode, returning the device to normal RUN mode. When exiting VLLS via the RESET pin, the PIN and WAKEUP bits are set in the SRS0 register of the reset control module (RCM). 14.4.6 Debug in low power modes When the MCU is secure, the device disables/limits debugger operation. When the MCU is unsecure, the ARM debugger can assert two power-up request signals: • System power up, via SYSPWR in the Debug Port Control/Stat register • Debug power up, via CDBGPWRUPREQ in the Debug Port Control/Stat register When asserted while in RUN, WAIT, VLPR, or VLPW, the mode controller drives a corresponding acknowledge for each signal, that is, both CDBGPWRUPACK and CSYSPWRUPACK. When both requests are asserted, the mode controller handles attempts to enter STOP and VLPS by entering an emulated stop state. In this emulated stop state: • the regulator is in run regulation, • the MCG-generated clock source is enabled, • all system clocks, except the core clock, are disabled, • the debug module has access to core registers, and • access to the on-chip peripherals is blocked. No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention mode and all debug operation can continue after waking from LLS, even in cases where system wakeup is due to a system reset event. Chapter 14 System Mode Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 347 General Business Information

Page 348

Entering into a VLLS mode causes all of the debug controls and settings to be powered off. To give time to the debugger to sync with the MCU, the MDM AP Control Register includes a Very-Low-Leakage Debug Request (VLLDBGREQ) bit that is set to configure the Reset Controller logic to hold the system in reset after the next recovery from a VLLS mode. This bit allows the debugger time to reinitialize the debug module before the debug session continues. The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge (VLLDBGACK) bit that is set to release the ARM core being held in reset following a VLLS recovery. The debugger reinitializes all debug IP, and then asserts the VLLDBGACK control bit to allow the RCM to release the ARM core from reset and allow CPU operation to begin. The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 348 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 349

Chapter 15 Power Management Controller 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system. 15.2 Features The PMC features include: • Internal voltage regulator • Active POR providing brown-out detect • Low-voltage detect supporting two low-voltage trip points with four warning levels per trip point 15.3 Low-voltage detect (LVD) system This device includes a system to guard against low-voltage conditions. This protects memory contents and controls MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user- K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 349 General Business Information

Page 350

selectable trip voltage: high (VLVDH) or low (VLVDL). The trip voltage is selected by the LVDSC1[LVDV] bits. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. Two flags are available to indicate the status of the low-voltage detect system: • The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF bit is set when the supply voltage falls below the selected trip point (VLVD). The LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal supply has returned above the trip point; otherwise, the LVDF bit remains set. • The low voltage warning flag (LVWF) operates in a level sensitive manner. The LVWF bit is set when the supply voltage falls below the selected monitor trip point (VLVW). The LVWF bit is cleared by writing one to the LVWACK bit, but only if the internal supply has returned above the trip point; otherwise, the LVWF bit remains set. 15.3.1 LVD reset operation By setting the LVDRE bit, the LVD generates a reset upon detection of a low voltage condition. The low voltage detection threshold is determined by the LVDV bits. After an LVD reset occurs, the LVD system holds the MCU in reset until the supply voltage rises above this threshold. The LVD bit in the SRS register is set following an LVD or power- on reset. 15.3.2 LVD interrupt operation By configuring the LVD circuit for interrupt operation (LVDIE set and LVDRE clear), LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a low voltage condition. The LVDF bit is cleared by writing one to the LVDSC1[LVDACK] bit. 15.3.3 Low-voltage warning (LVW) interrupt operation The LVD system contains a low-voltage warning flag (LVWF) to indicate that the supply voltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt, which is enabled by setting the LVDSC2[LVWIE] bit. If enabled, an LVW interrupt request occurs when the LVWF is set. LVWF is cleared by writing one to the LVDSC2[LVWACK] bit. The LVDSC2[LVWV] bits select one of four trip voltages: Low-voltage detect (LVD) system K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 350 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 351

• Highest: VLVW4 • Two mid-levels: VLVW3 and VLVW2 • Lowest: VLVW1 15.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode. The I/O are released immediately after a wakeup or reset event. In the case of LLS exit via a RESET pin, the I/O default to their reset state. When in VLLS modes, the I/O states are held on a wakeup event (with the exception of wakeup by reset event) until the wakeup has been acknowledged via a write to the ACKISO bit. In the case of VLLS exit via a RESET pin, the I/O are released and default to their reset state. In this case, no write to the ACKISO is needed. 15.5 Memory map and register descriptions PMC register details follow. NOTE Different portions of PMC registers are reset only by particular reset types. Each register's description provides details. For more information about the types of reset on this chip, refer to the Reset section details. PMC memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4007_D000 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) 8 R/W 1010h 15.5.1/352 4007_D001 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) 8 R/W 000h 15.5.2/353 4007_D002 Regulator Status And Control register (PMC_REGSC) 8 R/W 044h 15.5.3/354 Chapter 15 Power Management Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 351 General Business Information

Page 352

15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect systems that must have LVD always on, configure the SMC's power mode protection register (PMPROT) to disallow any very low power or low leakage modes from being enabled. See the device's data sheet for the exact LVD trip voltages. NOTE The LVDV bits are reset solely on a POR Only event. The register's other bits are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. Address: 4007_D000h base + 0h offset = 4007_D000h Bit 7 6 5 4 3 2 1 0 Read LVDF 0 LVDIE LVDRE 0 LVDV Write LVDACK Reset 0 0 0 1 0 0 0 0 PMC_LVDSC1 field descriptions Field Description 7 LVDF Low-Voltage Detect Flag This read-only status bit indicates a low-voltage detect event. 0 Low-voltage event not detected 1 Low-voltage event detected 6 LVDACK Low-Voltage Detect Acknowledge This write-only bit is used to acknowledge low voltage detection errors. Write 1 to clear LVDF. Reads always return 0. 5 LVDIE Low-Voltage Detect Interrupt Enable Enables hardware interrupt requests for LVDF. 0 Hardware interrupt disabled (use polling) 1 Request a hardware interrupt when LVDF = 1 Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 352 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 353

PMC_LVDSC1 field descriptions (continued) Field Description 4 LVDRE Low-Voltage Detect Reset Enable This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored. 0 LVDF does not generate hardware resets 1 Force an MCU reset when LVDF = 1 3–2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1–0 LVDV Low-Voltage Detect Voltage Select Selects the LVD trip point voltage (V LVD ). 00 Low trip point selected (V LVD = V LVDL ) 01 High trip point selected (V LVD = V LVDH ) 10 Reserved 11 Reserved 15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) This register contains status and control bits to support the low voltage warning function. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC2 settings. See the device's data sheet for the exact LVD trip voltages. NOTE The LVW trip voltages depend on LVWV and LVDV bits. NOTE The LVWV bits are reset solely on a POR Only event. The register's other bits are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. Address: 4007_D000h base + 1h offset = 4007_D001h Bit 7 6 5 4 3 2 1 0 Read LVWF 0 LVWIE 0 LVWV Write LVWACK Reset 0 0 0 0 0 0 0 0 Chapter 15 Power Management Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 353 General Business Information

Page 354

PMC_LVDSC2 field descriptions Field Description 7 LVWF Low-Voltage Warning Flag This read-only status bit indicates a low-voltage warning event. LVWF is set when VSupply transitions below the trip point, or after reset and VSupply is already below VLVW . 0 Low-voltage warning event not detected 1 Low-voltage warning event detected 6 LVWACK Low-Voltage Warning Acknowledge This write-only bit is used to acknowledge low voltage warning errors. Write 1 to clear LVWF. Reads always return 0. 5 LVWIE Low-Voltage Warning Interrupt Enable Enables hardware interrupt requests for LVWF. 0 Hardware interrupt disabled (use polling) 1 Request a hardware interrupt when LVWF = 1 4–2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1–0 LVWV Low-Voltage Warning Voltage Select Selects the LVW trip point voltage (VLVW). The actual voltage for the warning depends on LVDSC1[LVDV]. 00 Low trip point selected (VLVW = VLVW1) 01 Mid 1 trip point selected (VLVW = VLVW2) 10 Mid 2 trip point selected (VLVW = VLVW3) 11 High trip point selected (VLVW = VLVW4) 15.5.3 Regulator Status And Control register (PMC_REGSC) The PMC contains an internal voltage regulator. The voltage regulator design uses a bandgap reference that is also available through a buffer as input to certain internal peripherals, such as the CMP and ADC. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation. NOTE This register is reset on Chip Reset Not VLLS and by reset types that trigger Chip Reset not VLLS. See the Reset section for more information. Address: 4007_D000h base + 2h offset = 4007_D002h Bit 7 6 5 4 3 2 1 0 Read 0 BGEN ACKISO REGONS Reserved BGBE Write w1c Reset 0 0 0 0 0 1 0 0 Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 354 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 355

PMC_REGSC field descriptions Field Description 7–5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 BGEN Bandgap Enable In VLPx Operation BGEN controls whether the bandgap is enabled in lower power modes of operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage reference in low power modes of operation, set BGEN to continue to enable the bandgap operation. NOTE: When the bandgap voltage reference is not needed in low power modes, clear BGEN to avoid excess power consumption. 0 Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes 1 Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes 3 ACKISO Acknowledge Isolation Reading this bit indicates whether certain peripherals and the I/O pads are in a latched state as a result of having been in a VLLS mode. Writing one to this bit when it is set releases the I/O pads and certain peripherals to their normal run mode state. NOTE: After recovering from a VLLS mode, user should restore chip configuration before clearing ACKISO. In particular, pin configuration for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from being falsely set when ACKISO is cleared. 0 Peripherals and I/O pads are in normal run state 1 Certain peripherals and I/O pads are in an isolated and latched state 2 REGONS Regulator In Run Regulation Status This read-only bit provides the current status of the internal voltage regulator. 0 Regulator is in stop regulation or in transition to/from it 1 Regulator is in run regulation 1 Reserved This field is reserved. NOTE: This reserved bit must remain cleared (set to 0). 0 BGBE Bandgap Buffer Enable Enables the bandgap buffer. 0 Bandgap buffer not enabled 1 Bandgap buffer enabled Chapter 15 Power Management Controller K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 355 General Business Information

Page 356

Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 356 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 357

Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The LLWU module allows the user to select up to 16 external pin sources and up to 8 internal modules as a wakeup source from low-leakage power modes. The input sources are described in the device's chip configuration details. Each of the available wakeup sources can be individually enabled. The RESET pin is an additional source for triggering an exit from low-leakage power modes, and causes the MCU to exit both LLS and VLLS through a reset flow. The LLWU_RST[LLRSTE] bit must be set to allow an exit from low-leakage modes via the RESET pin. On a device where the RESET pin is shared with other functions, the explicit port mux control register must be set for the RESET pin before the RESET pin can be used as a low-leakage reset source. The LLWU module also includes three optional digital pin filters: two for the external wakeup pins and one for the RESET pin. 16.1.1 Features The LLWU module features include: • Support for up to 16 external input pins and up to 8 internal modules with individual enable bits K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 357 General Business Information

Page 358

• Input sources may be external pins or from internal peripherals capable of running in LLS or VLLS. See the chip configuration information for wakeup input sources for this device. • External pin wakeup inputs, each of which is programmable as falling-edge, rising- edge, or any change • Wakeup inputs that are activated if enabled after MCU enters a low-leakage power mode • Optional digital filters provided to qualify an external pin detect and RESET pin detect. 16.1.2 Modes of operation The LLWU module becomes functional on entry into a low-leakage power mode. After recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the LLWU continues to detect wakeup events until the user has acknowledged the wakeup via a write to the PMC_REGSC[ACKISO] bit. 16.1.2.1 LLS mode The LLWU module provides up to 16 external wakeup inputs and up to 8 internal module wakeup inputs. An LLS reset event can be initiated via assertion of the RESET pin. Wakeup events due to external wakeup inputs and internal module wakeup inputs result in an interrupt flow when exiting LLS. A reset event due to RESET pin assertion results in a reset flow when exiting LLS. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery. 16.1.2.2 VLLS modes The LLWU module provides up to 16 external wakeup inputs and up to 8 internal module wakeup inputs. A VLLS reset event can be initiated via assertion of the RESET pin. All wakeup and reset events result in VLLS exit via a reset flow. Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 358 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 359

16.1.2.3 Non-low leakage modes The LLWU is not active in all non-low leakage modes where detection and control logic are in a static state. The LLWU registers are accessible in non-low leakage modes and are available for configuring and reading status when bus transactions are possible. When theRESET pin filter or wakeup pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within 5 LPO clock cycles of an active edge, the edge event will be detected by the LLWU. For RESET pin filtering, this means that there is no restart to the minimum LPO cycle duration as the filtering transitions from a non-low leakage filter, which is implemented in the RCM, to the LLWU filter. 16.1.2.4 Debug mode When the chip is in Debug mode and then enters LLS or a VLLSx mode, no debug logic works in the fully-functional low-leakage mode. Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive. 16.1.3 Block diagram The following figure is the block diagram for the LLWU module. Chapter 16 Low-Leakage Wakeup Unit (LLWU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 359 General Business Information

Page 360

Module0 interrupt flag (LLWU_M0IF) WUME0 LLWU_MWUF0 occurred Internal module sources LLWU controller External pin sources exit low leakge mode interrupt flow reset flow reset occurred RSTFILT RESET LLWU_P0 LLWU_P15 Pin filter 1 wakeup occurred Interrupt module flag detect WUPE15 2 Edge detect enter low leakge mode WUPE0 Edge detect Module7 interrupt flag (LLWU_M7IF) WUME7 LLWU_MWUF7 occurred Interrupt module flag detect LPO Pin filter 2 LPO FILT1[FILTE] Pin filter 1 Synchronizer Synchronizer Edge detect LLWU_P15 wakeup occurred Edge detect Pin filter 2 wakeup occurred 2 LLWU_P0 wakeup occurred RESET Pin filter LPO FILT2[FILTSEL] FILT1[FILTSEL] FILT2[FILTE] Figure 16-1. LLWU block diagram 16.2 LLWU signal descriptions The signal properties of LLWU are shown in the following table. The external wakeup input pins can be enabled to detect either rising-edge, falling-edge, or on any change. Table 16-1. LLWU signal descriptions Signal Description I/O LLWU_Pn Wakeup inputs (n = 0-15) I LLWU signal descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 360 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 361

16.3 Memory map/register definition The LLWU includes the following registers: • Five 8-bit wakeup source enable registers • Enable external pin input sources • Enable internal peripheral sources • Three 8-bit wakeup flag registers • Indication of wakeup source that caused exit from a low-leakage power mode includes external pin or internal module interrupt • Two 8-bit wakeup pin filter enable registers • One 8-bit RESET pin filter enable register NOTE All LLWU registers are reset by Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. Each register's displayed reset value represents this subset of reset types. LLWU registers are unaffected by reset types that do not trigger Chip Reset not VLLS. For more information about the types of reset on this chip, refer to the Introduction details. LLWU memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4007_C000 LLWU Pin Enable 1 register (LLWU_PE1) 8 R/W 000h 16.3.1/362 4007_C001 LLWU Pin Enable 2 register (LLWU_PE2) 8 R/W 000h 16.3.2/363 4007_C002 LLWU Pin Enable 3 register (LLWU_PE3) 8 R/W 000h 16.3.3/364 4007_C003 LLWU Pin Enable 4 register (LLWU_PE4) 8 R/W 000h 16.3.4/365 4007_C004 LLWU Module Enable register (LLWU_ME) 8 R/W 000h 16.3.5/366 4007_C005 LLWU Flag 1 register (LLWU_F1) 8 R/W 000h 16.3.6/368 4007_C006 LLWU Flag 2 register (LLWU_F2) 8 R/W 000h 16.3.7/369 4007_C007 LLWU Flag 3 register (LLWU_F3) 8 R/W 000h 16.3.8/371 4007_C008 LLWU Pin Filter 1 register (LLWU_FILT1) 8 R/W 000h 16.3.9/373 4007_C009 LLWU Pin Filter 2 register (LLWU_FILT2) 8 R/W 000h 16.3.10/374 4007_C00A LLWU Reset Enable register (LLWU_RST) 8 R/W 022h 16.3.11/375 Chapter 16 Low-Leakage Wakeup Unit (LLWU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 361 General Business Information

Page 362

16.3.1 LLWU Pin Enable 1 register (LLWU_PE1) LLWU_PE1 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P3-LLWU_P0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 0h offset = 4007_C000h Bit 7 6 5 4 3 2 1 0 Read WUPE3 WUPE2 WUPE1 WUPE0 Write Reset 0 0 0 0 0 0 0 0 LLWU_PE1 field descriptions Field Description 7–6 WUPE3 Wakeup Pin Enable For LLWU_P3 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 5–4 WUPE2 Wakeup Pin Enable For LLWU_P2 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 3–2 WUPE1 Wakeup Pin Enable For LLWU_P1 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 1–0 WUPE0 Wakeup Pin Enable For LLWU_P0 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 362 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 363

LLWU_PE1 field descriptions (continued) Field Description 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 16.3.2 LLWU Pin Enable 2 register (LLWU_PE2) LLWU_PE2 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P7-LLWU_P4. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 1h offset = 4007_C001h Bit 7 6 5 4 3 2 1 0 Read WUPE7 WUPE6 WUPE5 WUPE4 Write Reset 0 0 0 0 0 0 0 0 LLWU_PE2 field descriptions Field Description 7–6 WUPE7 Wakeup Pin Enable For LLWU_P7 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 5–4 WUPE6 Wakeup Pin Enable For LLWU_P6 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 3–2 WUPE5 Wakeup Pin Enable For LLWU_P5 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection Table continues on the next page... Chapter 16 Low-Leakage Wakeup Unit (LLWU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 363 General Business Information

Page 364

LLWU_PE2 field descriptions (continued) Field Description 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 1–0 WUPE4 Wakeup Pin Enable For LLWU_P4 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 16.3.3 LLWU Pin Enable 3 register (LLWU_PE3) LLWU_PE3 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P11-LLWU_P8. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 2h offset = 4007_C002h Bit 7 6 5 4 3 2 1 0 Read WUPE11 WUPE10 WUPE9 WUPE8 Write Reset 0 0 0 0 0 0 0 0 LLWU_PE3 field descriptions Field Description 7–6 WUPE11 Wakeup Pin Enable For LLWU_P11 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 5–4 WUPE10 Wakeup Pin Enable For LLWU_P10 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 364 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 365

LLWU_PE3 field descriptions (continued) Field Description 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 3–2 WUPE9 Wakeup Pin Enable For LLWU_P9 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 1–0 WUPE8 Wakeup Pin Enable For LLWU_P8 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 16.3.4 LLWU Pin Enable 4 register (LLWU_PE4) LLWU_PE4 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P15-LLWU_P12. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 3h offset = 4007_C003h Bit 7 6 5 4 3 2 1 0 Read WUPE15 WUPE14 WUPE13 WUPE12 Write Reset 0 0 0 0 0 0 0 0 LLWU_PE4 field descriptions Field Description 7–6 WUPE15 Wakeup Pin Enable For LLWU_P15 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection Table continues on the next page... Chapter 16 Low-Leakage Wakeup Unit (LLWU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 365 General Business Information

Page 366

LLWU_PE4 field descriptions (continued) Field Description 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 5–4 WUPE14 Wakeup Pin Enable For LLWU_P14 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 3–2 WUPE13 Wakeup Pin Enable For LLWU_P13 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 1–0 WUPE12 Wakeup Pin Enable For LLWU_P12 Enables and configures the edge detection for the wakeup pin. 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 16.3.5 LLWU Module Enable register (LLWU_ME) LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7-MWUF0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 4h offset = 4007_C004h Bit 7 6 5 4 3 2 1 0 Read WUME7 WUME6 WUME5 WUME4 WUME3 WUME2 WUME1 WUME0 Write Reset 0 0 0 0 0 0 0 0 Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 366 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 367

LLWU_ME field descriptions Field Description 7 WUME7 Wakeup Module Enable For Module 7 Enables an internal module as a wakeup source input. 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source 6 WUME6 Wakeup Module Enable For Module 6 Enables an internal module as a wakeup source input. 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source 5 WUME5 Wakeup Module Enable For Module 5 Enables an internal module as a wakeup source input. 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source 4 WUME4 Wakeup Module Enable For Module 4 Enables an internal module as a wakeup source input. 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source 3 WUME3 Wakeup Module Enable For Module 3 Enables an internal module as a wakeup source input. 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source 2 WUME2 Wakeup Module Enable For Module 2 Enables an internal module as a wakeup source input. 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source 1 WUME1 Wakeup Module Enable for Module 1 Enables an internal module as a wakeup source input. 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source 0 WUME0 Wakeup Module Enable For Module 0 Enables an internal module as a wakeup source input. 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source Chapter 16 Low-Leakage Wakeup Unit (LLWU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 367 General Business Information

Page 368

16.3.6 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 5h offset = 4007_C005h Bit 7 6 5 4 3 2 1 0 Read WUF7 WUF6 WUF5 WUF4 WUF3 WUF2 WUF1 WUF0 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F1 field descriptions Field Description 7 WUF7 Wakeup Flag For LLWU_P7 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF7. 0 LLWU_P7 input was not a wakeup source 1 LLWU_P7 input was a wakeup source 6 WUF6 Wakeup Flag For LLWU_P6 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF6. 0 LLWU_P6 input was not a wakeup source 1 LLWU_P6 input was a wakeup source 5 WUF5 Wakeup Flag For LLWU_P5 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF5. 0 LLWU_P5 input was not a wakeup source 1 LLWU_P5 input was a wakeup source Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 368 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 369

LLWU_F1 field descriptions (continued) Field Description 4 WUF4 Wakeup Flag For LLWU_P4 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF4. 0 LLWU_P4 input was not a wakeup source 1 LLWU_P4 input was a wakeup source 3 WUF3 Wakeup Flag For LLWU_P3 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF3. 0 LLWU_P3 input was not a wakeup source 1 LLWU_P3 input was a wakeup source 2 WUF2 Wakeup Flag For LLWU_P2 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF2. 0 LLWU_P2 input was not a wakeup source 1 LLWU_P2 input was a wakeup source 1 WUF1 Wakeup Flag For LLWU_P1 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF1. 0 LLWU_P1 input was not a wakeup source 1 LLWU_P1 input was a wakeup source 0 WUF0 Wakeup Flag For LLWU_P0 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF0. 0 LLWU_P0 input was not a wakeup source 1 LLWU_P0 input was a wakeup source 16.3.7 LLWU Flag 2 register (LLWU_F2) LLWU_F2 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared. Chapter 16 Low-Leakage Wakeup Unit (LLWU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 369 General Business Information

Page 370

NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 6h offset = 4007_C006h Bit 7 6 5 4 3 2 1 0 Read WUF15 WUF14 WUF13 WUF12 WUF11 WUF10 WUF9 WUF8 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F2 field descriptions Field Description 7 WUF15 Wakeup Flag For LLWU_P15 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF15. 0 LLWU_P15 input was not a wakeup source 1 LLWU_P15 input was a wakeup source 6 WUF14 Wakeup Flag For LLWU_P14 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF14. 0 LLWU_P14 input was not a wakeup source 1 LLWU_P14 input was a wakeup source 5 WUF13 Wakeup Flag For LLWU_P13 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF13. 0 LLWU_P13 input was not a wakeup source 1 LLWU_P13 input was a wakeup source 4 WUF12 Wakeup Flag For LLWU_P12 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF12. 0 LLWU_P12 input was not a wakeup source 1 LLWU_P12 input was a wakeup source 3 WUF11 Wakeup Flag For LLWU_P11 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF11. 0 LLWU_P11 input was not a wakeup source 1 LLWU_P11 input was a wakeup source 2 WUF10 Wakeup Flag For LLWU_P10 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 370 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 371

LLWU_F2 field descriptions (continued) Field Description Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF10. 0 LLWU_P10 input was not a wakeup source 1 LLWU_P10 input was a wakeup source 1 WUF9 Wakeup Flag For LLWU_P9 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF9. 0 LLWU_P9 input was not a wakeup source 1 LLWU_P9 input was a wakeup source 0 WUF8 Wakeup Flag For LLWU_P8 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF8. 0 LLWU_P8 input was not a wakeup source 1 LLWU_P8 input was a wakeup source 16.3.8 LLWU Flag 3 register (LLWU_F3) LLWU_F3 contains the wakeup flags indicating which internal wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. For internal peripherals that are capable of running in a low-leakage power mode, such as RTC or CMP modules, the flag from the associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to the MWUFx bit. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 7h offset = 4007_C007h Bit 7 6 5 4 3 2 1 0 Read MWUF7 MWUF6 MWUF5 MWUF4 MWUF3 MWUF2 MWUF1 MWUF0 Write Reset 0 0 0 0 0 0 0 0 Chapter 16 Low-Leakage Wakeup Unit (LLWU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 371 General Business Information

Page 372

LLWU_F3 field descriptions Field Description 7 MWUF7 Wakeup flag For module 7 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 Module 7 input was not a wakeup source 1 Module 7 input was a wakeup source 6 MWUF6 Wakeup flag For module 6 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 Module 6 input was not a wakeup source 1 Module 6 input was a wakeup source 5 MWUF5 Wakeup flag For module 5 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 Module 5 input was not a wakeup source 1 Module 5 input was a wakeup source 4 MWUF4 Wakeup flag For module 4 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 Module 4 input was not a wakeup source 1 Module 4 input was a wakeup source 3 MWUF3 Wakeup flag For module 3 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 Module 3 input was not a wakeup source 1 Module 3 input was a wakeup source 2 MWUF2 Wakeup flag For module 2 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 Module 2 input was not a wakeup source 1 Module 2 input was a wakeup source 1 MWUF1 Wakeup flag For module 1 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 Module 1 input was not a wakeup source 1 Module 1 input was a wakeup source 0 MWUF0 Wakeup flag For module 0 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 372 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 373

LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 Module 0 input was not a wakeup source 1 Module 0 input was a wakeup source 16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1) LLWU_FILT1 is a control and status register that is used to enable/disable the digital filter 1 features for an external pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 8h offset = 4007_C008h Bit 7 6 5 4 3 2 1 0 Read FILTF FILTE 0 FILTSEL Write w1c Reset 0 0 0 0 0 0 0 0 LLWU_FILT1 field descriptions Field Description 7 FILTF Filter Detect Flag Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. 0 Pin Filter 1 was not a wakeup source 1 Pin Filter 1 was a wakeup source 6–5 FILTE Digital Filter On External Pin Controls the digital filter options for the external pin detect. 00 Filter disabled 01 Filter posedge detect enabled 10 Filter negedge detect enabled 11 Filter any edge detect enabled 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... Chapter 16 Low-Leakage Wakeup Unit (LLWU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 373 General Business Information

Page 374

LLWU_FILT1 field descriptions (continued) Field Description 3–0 FILTSEL Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 Select LLWU_P0 for filter ... ... 1111 Select LLWU_P15 for filter 16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2) LLWU_FILT2 is a control and status register that is used to enable/disable the digital filter 2 features for an external pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 9h offset = 4007_C009h Bit 7 6 5 4 3 2 1 0 Read FILTF FILTE 0 FILTSEL Write w1c Reset 0 0 0 0 0 0 0 0 LLWU_FILT2 field descriptions Field Description 7 FILTF Filter Detect Flag Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. 0 Pin Filter 2 was not a wakeup source 1 Pin Filter 2 was a wakeup source 6–5 FILTE Digital Filter On External Pin Controls the digital filter options for the external pin detect. 00 Filter disabled 01 Filter posedge detect enabled 10 Filter negedge detect enabled 11 Filter any edge detect enabled 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 374 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 375

LLWU_FILT2 field descriptions (continued) Field Description 3–0 FILTSEL Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 Select LLWU_P0 for filter ... ... 1111 Select LLWU_P15 for filter 16.3.11 LLWU Reset Enable register (LLWU_RST) LLWU_RST is a control register that is used to enable/disable the digital filter for the external pin detect and RESET pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + Ah offset = 4007_C00Ah Bit 7 6 5 4 3 2 1 0 Read 0 LLRSTE RSTFILT Write Reset 0 0 0 0 0 0 1 0 LLWU_RST field descriptions Field Description 7–2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 LLRSTE Low-Leakage Mode RESET Enable This bit must be set to allow the device to be reset while in a low-leakage power mode. On devices where Reset is not a dedicated pin, the RESET pin must also be enabled in the explicit port mux control. 0 RESET pin not enabled as a leakage mode exit source 1 RESET pin enabled as a low leakage mode exit source 0 RSTFILT Digital Filter On RESET Pin Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or VLLS1 modes. 0 Filter not enabled 1 Filter enabled Chapter 16 Low-Leakage Wakeup Unit (LLWU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 375 General Business Information

Page 376

16.4 Functional description This on-chip peripheral module is called a low-leakage wakeup unit (LLWU) module because it allows internal peripherals and external input pins as a source of wakeup from low-leakage modes. It is operational only in LLS and VLLSx modes. The LLWU module contains pin enables for each external pin and internal module. For each external pin, the user can disable or select the edge type for the wakeup. Type options are: • Falling-edge • Rising-edge • Either-edge When an external pin is enabled as a wakeup source, the pin must be configured as an input pin. The LLWU implements optional 3-cycle glitch filters, based on the LPO clock. A detected external pin, either wakeup or RESET, is required to remain asserted until the enabled glitch filter times out. Additional latency of up to 2 cycles is due to synchronization, which results in a total of up to 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. Two wakeup detect filters are available to detect up to two external pins. A separate reset filter is on the RESET pin. Glitch filtering is not provided on the internal modules. For internal module wakeup operation, the WUMEx bit enables the associated module as a wakeup source. 16.4.1 LLS mode Wakeup events triggered from either an external pin input or an internal module input result in a CPU interrupt flow to begin user code execution. An LLS reset event due to RESET pin assertion causes an exit via a system reset. State retention data is lost, and the I/O states return to their reset state. The RCM_SRS[WAKEUP] and RCM_SRS[PIN] bits are set and the system executes a reset flow before CPU operation begins with a reset vector fetch. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 376 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 377

16.4.2 VLLS modes In the case of a wakeup due to external pin or internal module wakeup, recovery is always via a reset flow and the RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active. State retention data is lost and I/O will be restored after PMC_REGSC[ACKISO] has been written. A VLLS exit event due to RESET pin assertion causes an exit via a system reset. State retention data is lost and the I/O states immediately return to their reset state. The RCM_SRS[WAKEUP] and RCM_SRS[PIN] bits are set and the system executes a reset flow before CPU operation begins with a reset vector fetch. 16.4.3 Initialization For an enabled peripheral wakeup input, the peripheral flag must be cleared by software before entering LLS or VLLSx mode to avoid an immediate exit from the mode. Flags associated with external input pins, filtered and unfiltered, must also be cleared by software prior to entry to LLS or VLLSx mode. After enabling an external pin filter or changing the source pin, wait at least 5 LPO clock cycles before entering LLS or VLLSx mode to allow the filter to initialize. NOTE After recovering from a VLLS mode, user must restore chip configuration before clearing ACKISO. In particular, pin configuration for enabled LLWU wakeup pins must be restored to avoid any LLWU flag from being falsely set when ACKISO is cleared. The signal selected as a wakeup source pin must be a digital pin, as selected in the pin mux control. Chapter 16 Low-Leakage Wakeup Unit (LLWU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 377 General Business Information

Page 378

Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 378 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 379

Chapter 17 Miscellaneous Control Module (MCM) 17.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 17.1.1 Features The MCM includes the following features: • Program-visible information on the platform configuration and revision • Control and counting logic for embedded trace buffer (ETB) almost full 17.2 Memory map/register descriptions The memory map and register descriptions below describe the registers using byte addresses. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 379 General Business Information

Page 380

MCM memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page E008_0008 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) 16 R 00_1F1Fh 17.2.1/380 E008_000A Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) 16 R 00_3F3Fh 17.2.2/381 E008_000C Control Register (MCM_CR) 32 R/W 0_0000 _0000h 17.2.3/381 E008_0010 Interrupt Status Register (MCM_ISR) 32 R 0_0000 _0000h 17.2.4/383 E008_0014 ETB Counter Control register (MCM_ETBCC) 32 R/W 0_0000 _0000h 17.2.5/384 E008_0018 ETB Reload register (MCM_ETBRL) 32 R/W 0_0000 _0000h 17.2.6/385 E008_001C ETB Counter Value register (MCM_ETBCNT) 32 R 0_0000 _0000h 17.2.7/385 E008_0030 Process ID register (MCM_PID) 32 R/W 0_0000 _0000h 17.2.8/386 17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device’s crossbar switch. Address: E008_0000h base + 8h offset = E008_0008h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 ASC Write Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 MCM_PLASC field descriptions Field Description 15–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7–0 ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 A bus slave connection to AXBS input port n is absent 1 A bus slave connection to AXBS input port n is present Memory map/register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 380 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 381

17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: E008_0000h base + Ah offset = E008_000Ah Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 AMC Write Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 MCM_PLAMC field descriptions Field Description 15–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7–0 AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 A bus master connection to AXBS input port n is absent 1 A bus master connection to AXBS input port n is present 17.2.3 Control Register (MCM_CR) CR defines the arbitration and protection schemes for the two system RAM arrays. NOTE Bits 23-0 are undefined after reset. Address: E008_0000h base + Ch offset = E008_000Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SRAMLWP SRAMLAP 0 SRAMUWP SRAMUAP Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 17 Miscellaneous Control Module (MCM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 381 General Business Information

Page 382

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_CR field descriptions Field Description 31 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30 SRAMLWP SRAM_L Write Protect When this bit is set, writes to SRAM_L array generates a bus error. 29–28 SRAMLAP SRAM_L arbitration priority Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the SRAM_L array. 00 Round robin 01 Special round robin (favors SRAM backoor accesses over the processor) 10 Fixed priority. Processor has highest, backdoor has lowest 11 Fixed priority. Backdoor has highest, processor has lowest 27 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26 SRAMUWP SRAM_U write protect When this bit is set, writes to SRAM_U array generates a bus error. 25–24 SRAMUAP SRAM_U arbitration priority Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the SRAM_U array. 00 Round robin 01 Special round robin (favors SRAM backoor accesses over the processor) 10 Fixed priority. Processor has highest, backdoor has lowest 11 Fixed priority. Backdoor has highest, processor has lowest 23–10 Reserved This field is reserved. 9 Reserved This field is reserved. 8–0 Reserved This field is reserved. Memory map/register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 382 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 383

17.2.4 Interrupt Status Register (MCM_ISR) Address: E008_0000h base + 10h offset = E008_0010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DHREQ NMI IRQ 0 W w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_ISR field descriptions Field Description 31–4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 DHREQ Debug Halt Request Indicator Indicates that a debug halt request is initiated due to a ETB counter expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the counter is disabled or when the ETB counter is reloaded. 0 No debug halt request 1 Debug halt request initiated 2 NMI Non-maskable Interrupt Pending If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires. 0 No pending NMI 1 Due to the ETB counter expiring, an NMI is pending 1 IRQ Normal Interrupt Pending If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires. Table continues on the next page... Chapter 17 Miscellaneous Control Module (MCM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 383 General Business Information

Page 384

MCM_ISR field descriptions (continued) Field Description 0 No pending interrupt 1 Due to the ETB counter expiring, a normal interrupt is pending 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 17.2.5 ETB Counter Control register (MCM_ETBCC) Address: E008_0000h base + 14h offset = E008_0014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 ITDIS ETDIS RLRQ RSPT CNTEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_ETBCC field descriptions Field Description 31–6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 ITDIS ITM-To-TPIU Disable Disables the trace path from ITM to TPIU. 0 ITM-to-TPIU trace path enabled 1 ITM-to-TPIU trace path disabled 4 ETDIS ETM-To-TPIU Disable Disables the trace path from ETM to TPIU. 0 ETM-to-TPIU trace path enabled 1 ETM-to-TPIU trace path disabled 3 RLRQ Reload Request Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI interrupts were enabled and an NMI or IRQ interrupt was generated on counter expiration, setting this bit clears the pending NMI or IRQ interrupt request. Table continues on the next page... Memory map/register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 384 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 385

MCM_ETBCC field descriptions (continued) Field Description If debug halt was enabled and a debug halt request was asserted on counter expiration, setting this bit clears the debug halt request. 0 No effect 1 Clears pending debug halt, NMI, or IRQ interrupt requests 2–1 RSPT Response Type 00 No response when the ETB count expires 01 Generate a normal interrupt when the ETB count expires 10 Generate an NMI when the ETB count expires 11 Generate a debug halt when the ETB count expires 0 CNTEN Counter Enable Enables the ETB counter. 0 ETB counter disabled 1 ETB counter enabled 17.2.6 ETB Reload register (MCM_ETBRL) Address: E008_0000h base + 18h offset = E008_0018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RELOAD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_ETBRL field descriptions Field Description 31–11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10–0 RELOAD Byte Count Reload Value Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4 value to this field results in a bus error. 17.2.7 ETB Counter Value register (MCM_ETBCNT) Address: E008_0000h base + 1Ch offset = E008_001Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 COUNTER W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 17 Miscellaneous Control Module (MCM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 385 General Business Information

Page 386

MCM_ETBCNT field descriptions Field Description 31–11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10–0 COUNTER Byte Count Counter Value Indicates the current 0-mod-4 value of the counter. 17.2.8 Process ID register (MCM_PID) This register drives the M0_PID and M1_PID values in the Memory Protection Unit(MPU). System software loads this register before passing control to a given user mode process. If the PID of the process does not match the value in this register, a bus error occurs. See the MPU chapter for more details. Address: E008_0000h base + 30h offset = E008_0030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PID W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_PID field descriptions Field Description 31–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7–0 PID M0_PID And M1_PID For MPU Drives the M0_PID and M1_PID values in the MPU. 17.3 Functional description This section describes the functional description of MCM module. 17.3.1 Interrupts The MCM generates two interrupt requests: • Non-maskable interrupt • Normal interrupt Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 386 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 387

17.3.1.1 Non-maskable interrupt The MCM's NMI is generated if: • ISCR[ETBN] is set, when • The ETB counter is enabled, ETBCC[CNTEN] = 1 • The ETB count expires • The response to counter expiration is an NMI, MCM_ETBCC[RSPT] = 10 17.3.1.2 Normal interrupt The MCM's normal interrupt is generated if any of the following is true: • ISCR[ETBI] is set, when • The ETB counter is enabled, ETBCC[CNTEN] = 1 • The ETB count expires • The response to counter expiration is a normal interrupt, ETBCC[RSPT] = 01 Chapter 17 Miscellaneous Control Module (MCM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 387 General Business Information

Page 388

Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 388 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 389

Chapter 18 Crossbar Switch (AXBS) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure. This structure allows all bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave. A variety of bus arbitration methods and attributes may be programmed on a slave-by-slave basis. 18.1.1 Features The crossbar switch includes these distinctive features: • Symmetric crossbar bus switch implementation • Allows concurrent accesses from different masters to different slaves • Slave arbitration attributes configured on a slave-by-slave basis • 32-bit width and support for byte, 2-byte, 4-byte, and 16-byte burst transfers • Operation at a 1-to-1 clock frequency with the bus masters • Low-Power Park mode support K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 389 General Business Information

Page 390

18.2 Memory Map / Register Definition Each slave port of the crossbar switch contains configuration registers. Read- and write- transfers require two bus clock cycles. The registers can be read from and written to only in supervisor mode. Additionally, these registers can be read from or written to only by 32-bit accesses. A bus error response is returned if an unimplemented location is accessed within the crossbar switch. The slave registers also feature a bit that, when set, prevents the registers from being written. The registers remain readable, but future write attempts have no effect on the registers and are terminated with a bus error response to the master initiating the write. The core, for example, takes a bus error interrupt. NOTE This section shows the registers for all eight master and slave ports. If a master or slave is not used on this particular device, then unexpected results occur when writing to its registers. See the chip configuration details for the exact master/slave assignments for your device. AXBS memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_4000 Priority Registers Slave (AXBS_PRS0) 32 R/W See section 18.2.1/391 4000_4010 Control Register (AXBS_CRS0) 32 R/W 0_0000 _0000h 18.2.2/394 4000_4100 Priority Registers Slave (AXBS_PRS1) 32 R/W See section 18.2.1/391 4000_4110 Control Register (AXBS_CRS1) 32 R/W 0_0000 _0000h 18.2.2/394 4000_4200 Priority Registers Slave (AXBS_PRS2) 32 R/W See section 18.2.1/391 4000_4210 Control Register (AXBS_CRS2) 32 R/W 0_0000 _0000h 18.2.2/394 4000_4300 Priority Registers Slave (AXBS_PRS3) 32 R/W See section 18.2.1/391 4000_4310 Control Register (AXBS_CRS3) 32 R/W 0_0000 _0000h 18.2.2/394 4000_4400 Priority Registers Slave (AXBS_PRS4) 32 R/W See section 18.2.1/391 4000_4410 Control Register (AXBS_CRS4) 32 R/W 0_0000 _0000h 18.2.2/394 4000_4500 Priority Registers Slave (AXBS_PRS5) 32 R/W See section 18.2.1/391 Table continues on the next page... Memory Map / Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 390 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 391

AXBS memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_4510 Control Register (AXBS_CRS5) 32 R/W 0_0000 _0000h 18.2.2/394 4000_4600 Priority Registers Slave (AXBS_PRS6) 32 R/W See section 18.2.1/391 4000_4610 Control Register (AXBS_CRS6) 32 R/W 0_0000 _0000h 18.2.2/394 4000_4700 Priority Registers Slave (AXBS_PRS7) 32 R/W See section 18.2.1/391 4000_4710 Control Register (AXBS_CRS7) 32 R/W 0_0000 _0000h 18.2.2/394 4000_4800 Master General Purpose Control Register (AXBS_MGPCR0) 32 R/W 0_0000 _0000h 18.2.3/396 4000_4900 Master General Purpose Control Register (AXBS_MGPCR1) 32 R/W 0_0000 _0000h 18.2.3/396 4000_4A00 Master General Purpose Control Register (AXBS_MGPCR2) 32 R/W 0_0000 _0000h 18.2.3/396 4000_4B00 Master General Purpose Control Register (AXBS_MGPCR3) 32 R/W 0_0000 _0000h 18.2.3/396 4000_4C00 Master General Purpose Control Register (AXBS_MGPCR4) 32 R/W 0_0000 _0000h 18.2.3/396 4000_4D00 Master General Purpose Control Register (AXBS_MGPCR5) 32 R/W 0_0000 _0000h 18.2.3/396 4000_4E00 Master General Purpose Control Register (AXBS_MGPCR6) 32 R/W 0_0000 _0000h 18.2.3/396 4000_4F00 Master General Purpose Control Register (AXBS_MGPCR7) 32 R/W 0_0000 _0000h 18.2.3/396 18.2.1 Priority Registers Slave (AXBS_PRSn) The priority registers (PRSn) set the priority of each master port on a per slave port basis and reside in each slave port. The priority register can be accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn register can only be read; attempts to write to it have no effect on PRSn and result in a bus-error response to the master initiating the write. No two available master ports may be programmed with the same priority level. Attempts to program two or more masters with the same priority level result in a bus-error response and the PRSn is not updated. NOTE The possible values for the PRSn fields depend on the number of masters available on the device. See the device's chip configuration details for the number of masters supported. Chapter 18 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 391 General Business Information

Page 392

• If the device contains less than five masters, values 000– 011 are valid and writing other values results in an error. • If the device contains n masters where n ≥ 5, values 0 to n -1 are valid and writing other values results in an error. Address: 4000_4000h base + 0h offset + (256d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 M7 0 M6 0 M5 0 M4 W Reset 0* 1* 1* 1* 0* 1* 1* 0* 0* 1* 0* 1* 0* 1* 0* 0* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 M3 0 M2 0 M1 0 M0 W Reset 0* 0* 1* 1* 0* 0* 1* 0* 0* 0* 0* 1* 0* 0* 0* 0*

Notes: See the device configuration details for the reset value of this register. • AXBS_PRSn field descriptions Field Description 31 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30–28 M7 Master 7 Priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. 27 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26–24 M6 Master 6 Priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. 23 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 22–20 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. Table continues on the next page... Memory Map / Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 392 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 393

AXBS_PRSn field descriptions (continued) Field Description 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. 19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18–16 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. 15 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 14–12 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. 11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10–8 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... Chapter 18 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 393 General Business Information

Page 394

AXBS_PRSn field descriptions (continued) Field Description 6–4 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2–0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. 18.2.2 Control Register (AXBS_CRSn) These registers control several features of each slave port and must be accessed using 32- bit accesses. After CRSn[RO] is set, the PRSn can only be read; attempts to write to it have no effect and result in an error response. Address: 4000_4000h base + 10h offset + (256d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R RO HLP 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 ARB 0 PCTL 0 PARK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AXBS_CRSn field descriptions Field Description 31 RO Read Only Forces the slave port’s CSRn and PRSn registers to be read-only. After set, only a hardware reset clears it. Table continues on the next page... Memory Map / Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 394 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 395

AXBS_CRSn field descriptions (continued) Field Description 0 The slave port’s registers are writeable 1 The slave port’s registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. 30 HLP Halt Low Priority Sets the initial arbitration priority for low power mode requests . Setting this bit will not affect the request for low power mode from attaining highest priority once it has control of the slave ports. 0 The low power mode request has the highest priority for arbitration on this slave port 1 The low power mode request has the lowest initial priority for arbitration on this slave port 29–10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9–8 ARB Arbitration Mode Selects the arbitration policy for the slave port. 00 Fixed priority 01 Round-robin, or rotating, priority 10 Reserved 11 Reserved 7–6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5–4 PCTL Parking Control Determines the slave port’s parking control. The low-power park feature results in an overall power savings if the slave port is not saturated. However, this forces an extra latency clock when any master tries to access the slave port while not in use because it is not parked on any master. 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 11 Reserved 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2–0 PARK Park Determines which master port the current slave port parks on when no masters are actively making requests and the PCTL bits are cleared. NOTE: Only select master ports that are actually present on the device. If not, undefined behavior may occur. 000 Park on master port M0 001 Park on master port M1 010 Park on master port M2 011 Park on master port M3 100 Park on master port M4 101 Park on master port M5 Table continues on the next page... Chapter 18 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 395 General Business Information

Page 396

AXBS_CRSn field descriptions (continued) Field Description 110 Park on master port M6 111 Park on master port M7 18.2.3 Master General Purpose Control Register (AXBS_MGPCRn) The MGPCR controls only whether the master’s undefined length burst accesses are allowed to complete uninterrupted or whether they can be broken by requests from higher priority masters. The MGPCR can be accessed only in Supervisor mode with 32-bit accesses. Address: 4000_4000h base + 800h offset + (256d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 AULB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AXBS_MGPCRn field descriptions Field Description 31–3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2–0 AULB Arbitrates On Undefined Length Bursts Determines whether, and when, the crossbar switch arbitrates away the slave port the master owns when the master is performing undefined length burst accesses. 000 No arbitration is allowed during an undefined length burst 001 Arbitration is allowed at any time during an undefined length burst 010 Arbitration is allowed after four beats of an undefined length burst 011 Arbitration is allowed after eight beats of an undefined length burst 100 Arbitration is allowed after 16 beats of an undefined length burst 101 Reserved 110 Reserved 111 Reserved 18.3 Functional Description Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 396 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 397

18.3.1 General operation When a master accesses the crossbar switch the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. Single-clock, or -zero-wait state, accesses are possible through the crossbar. If the targeted slave port of the access is busy or parked on a different master port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request. The latency in servicing the request depends on each master's priority level and the responding peripheral's access time. Because the crossbar switch appears to be just another slave to the master device, the master device has no knowledge of whether it actually owns the slave port it is targeting. While the master does not have control of the slave port it is targeting, it simply waits. A master is given control of the targeted slave port only after a previous access to a different slave port completes, regardless of its priority on the newly targeted slave port. This prevents deadlock from occurring when: • A higher priority master has: • An outstanding request to one slave port that has a long response time and • A pending access to a different slave port, and • A lower priority master is also making a request to the same slave port as the pending access of the higher priority master. After the master has control of the slave port it is targeting, the master remains in control of that slave port until it gives up the slave port by running an IDLE cycle or by leaving that slave port for its next access. The master could also lose control of the slave port if another higher priority master makes a request to the slave port; however, if the master is running a fixed-length burst transfer it retains control of the slave port until that transfer completes. Based on MGPCR[AULB], the master either retains control of the slave port when doing undefined length incrementing burst transfers or loses the bus to a higher priority master. The crossbar terminates all master IDLE transfers, as opposed to allowing the termination to come from one of the slave buses. Additionally, when no master is requesting access to a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port. When a slave bus is being idled by the crossbar, it can park the slave port on the master port indicated by CRSn[PARK]. This is done to save the initial clock of arbitration delay that otherwise would be seen if the master had to arbitrate to gain control of the slave port. The slave port can also be put into Low Power Park mode to save power, by using CRSn[PCTL]. Chapter 18 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 397 General Business Information

Page 398

18.3.2 Register coherency The operation of the crossbar is affected as soon as a register is written. The values of the registers do not track with slave-port-related master accesses, but instead track only with slave accesses. The MGPCRx[AULB] bits are the exception to this rule. The update of these bits is only recognized when the master on that master port runs an IDLE cycle, even though the slave bus cycle to write them will have already terminated successfully. If the MGPCRx[AULB] bits are written between two burst accesses, the new AULB encodings do not take effect until an IDLE cycle is initiated by the master on that master port. 18.3.3 Arbitration The crossbar switch supports two arbitration schemes: • A fixed-priority comparison algorithm • A round-robin fairness algorithm The arbitration scheme is independently programmable for each slave port. 18.3.3.1 Arbitration during undefined length bursts Arbitration points during an undefined length burst are defined by the current master's MGPCR[AULB] field setting. When a defined length is imposed on the burst via the AULB bits, the undefined length burst is treated as a single or series of single back-to- back fixed-length burst accesses. The following figure illustrates an example: Lost control Lost control Master-to-slave transfer 1 2 3 4 5 6 7 8 9 10 11 12 1 beat 1 beat 12 beat burst No arbitration Arbitration allowed No arbitration No arbitration MGPCR[AULB] Figure 18-28. Undefined length burst example In this example, a master runs an undefined length burst and the MGPCR[AULB] bits indicate arbitration occurs after the fourth beat of the burst. The master runs two sequential beats and then starts what will be a 12-beat undefined length burst access to a new address within the same slave port region as the previous access. The crossbar does Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 398 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 399

not allow an arbitration point until the fourth overall access, or the second beat of the second burst. At that point, all remaining accesses are open for arbitration until the master loses control of the slave port. Assume the master loses control of the slave port after the fifth beat of the second burst. After the master regains control of the slave port no arbitration point is available until after the master has run four more beats of its burst. After the fourth beat of the now continued burst, or the ninth beat of the second burst from the master's perspective, is taken, all beats of the burst are once again open for arbitration until the master loses control of the slave port. Assume the master again loses control of the slave port on the fifth beat of the third now continued burst, or the 10th beat of the second burst from the master's perspective. After the master regains control of the slave port, it is allowed to complete its final two beats of its burst without facing arbitration. Note Fixed-length burst accesses are not affected by the AULB bits. All fixed-length burst accesses lock out arbitration until the last beat of the fixed-length burst. 18.3.3.2 Fixed-priority operation When operating in Fixed-Priority mode, each master is assigned a unique priority level in the priority registers (PRSn) . If two masters request access to a slave port, the master with the highest priority in the selected priority register gains control over the slave port. When a master makes a request to a slave port, the slave port checks whether the new requesting master's priority level is higher than that of the master that currently has control over the slave port, unless the slave port is in a parked state. The slave port performs an arbitration check at every clock edge to ensure that the proper master, if any, has control of the slave port. The following table describes possible scenarios based on the requesting master port: Table 18-29. How AXBS grants control of a slave port to a master When Then AXBS grants control to the requesting master Both of the following are true: • The current master is not running a transfer. • The new requesting master's priority level is higher than that of the current master. At the next clock edge Table continues on the next page... Chapter 18 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 399 General Business Information

Page 400

Table 18-29. How AXBS grants control of a slave port to a master (continued) When Then AXBS grants control to the requesting master Both of the following are true: • The current master is running a fixed length burst transfer or a locked transfer. • The requesting master's priority level is higher than that of the current master. At the end of the burst transfer or locked transfer Both of the following are true: • The current master is running an undefined length burst transfer. • The requesting master's priority level is higher than that of the current master. At the next arbitration point for the undefined length burst transfer NOTE: Arbitration points for an undefined length burst are defined in the MGPCR for each master. The requesting master's priority level is lower than the current master. At the conclusion of one of the following cycles: • An IDLE cycle • A non-IDLE cycle to a location other than the current slave port 18.3.3.3 Round-robin priority operation When operating in Round-Robin mode, each master is assigned a relative priority based on the master port number. This relative priority is compared to the master port number (ID) of the last master to perform a transfer on the slave bus. The highest priority requesting master becomes owner of the slave bus at the next transfer boundary, accounting for locked and fixed-length burst transfers. Priority is based on how far ahead the ID of the requesting master is to the ID of the last master. After granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line is granted access to the slave port at the next transfer boundary, or possibly on the next clock cycle if the current master has no pending access request. As an example of arbitration in Round-Robin mode, assume the crossbar is implemented with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and master 0, 4 and 5 make simultaneous requests, they are serviced in the order 4, 5, and then 0. Parking may continue to be used in a round-robin mode, but does not affect the round- robin pointer unless the parked master actually performs a transfer. Handoff occurs to the next master in line after one cycle of arbitration. If the slave port is put into low-power park mode, the round-robin pointer is reset to point at master port 0, giving it the highest priority. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 400 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 401

18.3.3.4 Priority assignment Each master port must be assigned a unique 3-bit priority level. If an attempt is made to program multiple master ports with the same priority level within the priority registers (PRSn), the crossbar switch responds with a bus error and the registers are not updated. 18.4 Initialization/application information No initialization is required by or for the crossbar switch. Hardware reset ensures all the register bits used by the crossbar switch are properly initialized to a valid state. However, settings and priorities may be programmed to achieve maximum system performance. Chapter 18 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 401 General Business Information

Page 402

Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 402 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 403

Chapter 19 Memory Protection Unit (MPU) 19.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The memory protection unit (MPU) provides hardware access control for all memory references generated in the device. 19.2 Overview The MPU concurrently monitors all system bus transactions and evaluates their appropriateness using pre-programmed region descriptors that define memory spaces and their access rights. Memory references that have sufficient access control rights are allowed to complete, while references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. 19.2.1 Block diagram A simplified block diagram of the MPU module is shown in the following figure. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 403 General Business Information

Page 404

Slave Port n Internal Region Descriptor 0 Region Descriptor 1 Region Descriptor x Access Evaluation Macro Access Evaluation Macro Access Evaluation Macro Mux Address Phase Signals Peripheral Bus MPU_EARn MPU_EDRn Figure 19-1. MPU block diagram The hardware's two-dimensional connection matrix is clearly visible with the basic access evaluation macro shown as the replicated submodule block. The crossbar switch slave ports are shown on the left, the region descriptor registers in the middle, and the peripheral bus interface on the right side. The evaluation macro contains two magnitude comparators connected to the start and end address registers from each region descriptor as well as the combinational logic blocks to determine the region hit and the access protection error. For details of the access evaluation macro, see Access evaluation macro. 19.2.2 Features The MPU implements a two-dimensional hardware array of memory region descriptors and the crossbar slave ports to continuously monitor the legality of every memory reference generated by each bus master in the system. The feature set includes: • 12 program-visible 128-bit region descriptors, accessible by four 32-bit words each • Each region descriptor defines a modulo-32 byte space, aligned anywhere in memory Overview K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 404 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 405

• Region sizes can vary from 32 bytes to 4 Gbytes • Two access control permissions defined in a single descriptor word • Masters 0–3: read, write, and execute attributes for supervisor and user accesses • Masters 4–7: read and write attributes • Hardware-assisted maintenance of the descriptor valid bit minimizes coherency issues • Alternate programming model view of the access control permissions word • Priority given to granting permission over denying access for overlapping region descriptors • Detects access protection errors if a memory reference does not hit in any memory region, or if the reference is illegal in all hit memory regions. If an access error occurs, the reference is terminated with an error response, and the MPU inhibits the bus cycle being sent to the targeted slave device. • Error registers, per slave port, capture the last faulting address, attributes, and other information • Global MPU enable/disable control bit 19.3 Memory map/register definition The programming model is partitioned into three groups: • Control/status registers • The data structure containing the region descriptors • The alternate view of the region descriptor access control values The programming model can only be referenced using 32-bit accesses. Attempted references using different access sizes, to undefined, that is, reserved, addresses, or with a non-supported access type, such as a write to a read-only register, or a read of a write- only register, generate an error termination. The programming model can be accessed only in supervisor mode. NOTE See the chip configuration details for any chip-specific register information this module. Chapter 19 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 405 General Business Information

Page 406

MPU memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_D000 Control/Error Status Register (MPU_CESR) 32 R/W 00_8151 _0181_5101h 19.3.1/409 4000_D010 Error Address Register, slave port n (MPU_EAR0) 32 R Undefined 19.3.2/410 4000_D014 Error Detail Register, slave port n (MPU_EDR0) 32 R Undefined 19.3.3/411 4000_D018 Error Address Register, slave port n (MPU_EAR1) 32 R Undefined 19.3.2/410 4000_D01C Error Detail Register, slave port n (MPU_EDR1) 32 R Undefined 19.3.3/411 4000_D020 Error Address Register, slave port n (MPU_EAR2) 32 R Undefined 19.3.2/410 4000_D024 Error Detail Register, slave port n (MPU_EDR2) 32 R Undefined 19.3.3/411 4000_D028 Error Address Register, slave port n (MPU_EAR3) 32 R Undefined 19.3.2/410 4000_D02C Error Detail Register, slave port n (MPU_EDR3) 32 R Undefined 19.3.3/411 4000_D030 Error Address Register, slave port n (MPU_EAR4) 32 R Undefined 19.3.2/410 4000_D034 Error Detail Register, slave port n (MPU_EDR4) 32 R Undefined 19.3.3/411 4000_D400 Region Descriptor n, Word 0 (MPU_RGD0_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D404 Region Descriptor n, Word 1 (MPU_RGD0_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D408 Region Descriptor n, Word 2 (MPU_RGD0_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D40C Region Descriptor n, Word 3 (MPU_RGD0_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D410 Region Descriptor n, Word 0 (MPU_RGD1_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D414 Region Descriptor n, Word 1 (MPU_RGD1_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D418 Region Descriptor n, Word 2 (MPU_RGD1_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D41C Region Descriptor n, Word 3 (MPU_RGD1_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D420 Region Descriptor n, Word 0 (MPU_RGD2_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D424 Region Descriptor n, Word 1 (MPU_RGD2_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D428 Region Descriptor n, Word 2 (MPU_RGD2_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D42C Region Descriptor n, Word 3 (MPU_RGD2_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D430 Region Descriptor n, Word 0 (MPU_RGD3_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D434 Region Descriptor n, Word 1 (MPU_RGD3_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D438 Region Descriptor n, Word 2 (MPU_RGD3_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 406 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 407

MPU memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_D43C Region Descriptor n, Word 3 (MPU_RGD3_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D440 Region Descriptor n, Word 0 (MPU_RGD4_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D444 Region Descriptor n, Word 1 (MPU_RGD4_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D448 Region Descriptor n, Word 2 (MPU_RGD4_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D44C Region Descriptor n, Word 3 (MPU_RGD4_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D450 Region Descriptor n, Word 0 (MPU_RGD5_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D454 Region Descriptor n, Word 1 (MPU_RGD5_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D458 Region Descriptor n, Word 2 (MPU_RGD5_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D45C Region Descriptor n, Word 3 (MPU_RGD5_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D460 Region Descriptor n, Word 0 (MPU_RGD6_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D464 Region Descriptor n, Word 1 (MPU_RGD6_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D468 Region Descriptor n, Word 2 (MPU_RGD6_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D46C Region Descriptor n, Word 3 (MPU_RGD6_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D470 Region Descriptor n, Word 0 (MPU_RGD7_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D474 Region Descriptor n, Word 1 (MPU_RGD7_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D478 Region Descriptor n, Word 2 (MPU_RGD7_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D47C Region Descriptor n, Word 3 (MPU_RGD7_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D480 Region Descriptor n, Word 0 (MPU_RGD8_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D484 Region Descriptor n, Word 1 (MPU_RGD8_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D488 Region Descriptor n, Word 2 (MPU_RGD8_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D48C Region Descriptor n, Word 3 (MPU_RGD8_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D490 Region Descriptor n, Word 0 (MPU_RGD9_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 Table continues on the next page... Chapter 19 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 407 General Business Information

Page 408

MPU memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_D494 Region Descriptor n, Word 1 (MPU_RGD9_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D498 Region Descriptor n, Word 2 (MPU_RGD9_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D49C Region Descriptor n, Word 3 (MPU_RGD9_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D4A0 Region Descriptor n, Word 0 (MPU_RGD10_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D4A4 Region Descriptor n, Word 1 (MPU_RGD10_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D4A8 Region Descriptor n, Word 2 (MPU_RGD10_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D4AC Region Descriptor n, Word 3 (MPU_RGD10_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D4B0 Region Descriptor n, Word 0 (MPU_RGD11_WORD0) 32 R/W 0_0000 _0000h 19.3.4/412 4000_D4B4 Region Descriptor n, Word 1 (MPU_RGD11_WORD1) 32 R/W 00_0000 _1F1Fh 19.3.5/412 4000_D4B8 Region Descriptor n, Word 2 (MPU_RGD11_WORD2) 32 R/W 0_0000 _0000h 19.3.6/413 4000_D4BC Region Descriptor n, Word 3 (MPU_RGD11_WORD3) 32 R/W 0_0000 _0000h 19.3.7/416 4000_D800 Region Descriptor Alternate Access Control n (MPU_RGDAAC0) 32 R/W 0_0000 _0000h 19.3.8/417 4000_D804 Region Descriptor Alternate Access Control n (MPU_RGDAAC1) 32 R/W 0_0000 _0000h 19.3.8/417 4000_D808 Region Descriptor Alternate Access Control n (MPU_RGDAAC2) 32 R/W 0_0000 _0000h 19.3.8/417 4000_D80C Region Descriptor Alternate Access Control n (MPU_RGDAAC3) 32 R/W 0_0000 _0000h 19.3.8/417 4000_D810 Region Descriptor Alternate Access Control n (MPU_RGDAAC4) 32 R/W 0_0000 _0000h 19.3.8/417 4000_D814 Region Descriptor Alternate Access Control n (MPU_RGDAAC5) 32 R/W 0_0000 _0000h 19.3.8/417 4000_D818 Region Descriptor Alternate Access Control n (MPU_RGDAAC6) 32 R/W 0_0000 _0000h 19.3.8/417 4000_D81C Region Descriptor Alternate Access Control n (MPU_RGDAAC7) 32 R/W 0_0000 _0000h 19.3.8/417 4000_D820 Region Descriptor Alternate Access Control n (MPU_RGDAAC8) 32 R/W 0_0000 _0000h 19.3.8/417 4000_D824 Region Descriptor Alternate Access Control n (MPU_RGDAAC9) 32 R/W 0_0000 _0000h 19.3.8/417 4000_D828 Region Descriptor Alternate Access Control n (MPU_RGDAAC10) 32 R/W 0_0000 _0000h 19.3.8/417 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 408 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 409

MPU memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_D82C Region Descriptor Alternate Access Control n (MPU_RGDAAC11) 32 R/W 0_0000 _0000h 19.3.8/417 19.3.1 Control/Error Status Register (MPU_CESR) Address: 4000_D000h base + 0h offset = 4000_D000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SPERR 0 1 0 HRL W w1c Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NSP NRGD 0 VLD W Reset 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 MPU_CESR field descriptions Field Description 31–27 SPERR Slave Port n Error Indicates a captured error in EARn and EDRn. This bit is set when the hardware detects an error and records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can detect the presence of a captured error. The following shows the correspondence between the bit number and slave port number: • Bit 31 corresponds to slave port 0. • Bit 30 corresponds to slave port 1. • Bit 29 corresponds to slave port 2. • Bit 28 corresponds to slave port 3. • Bit 27 corresponds to slave port 4. 0 No error has occurred for slave port n. 1 An error has occurred for slave port n. 26–24 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 23 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 22–20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19–16 HRL Hardware Revision Level Specifies the MPU’s hardware and definition revision level. It can be read by software to determine the functional definition of the module. Table continues on the next page... Chapter 19 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 409 General Business Information

Page 410

MPU_CESR field descriptions (continued) Field Description 15–12 NSP Number Of Slave Ports Specifies the number of slave ports connected to the MPU. 11–8 NRGD Number Of Region Descriptors Indicates the number of region descriptors implemented in the MPU. 0000 8 region descriptors 0001 12 region descriptors 0010 16 region descriptors 7–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 VLD Valid Global enable/disable for the MPU. 0 MPU is disabled. All accesses from all bus masters are allowed. 1 MPU is enabled 19.3.2 Error Address Register, slave port n (MPU_EARn) When the MPU detects an access error on slave port n, the 32-bit reference address is captured in this read-only register and the corresponding bit in CESR[SPERR] set. Additional information about the faulting access is captured in the corresponding EDRn at the same time. This register and the corresponding EDRn contain the most recent access error; there are no hardware interlocks with CESR[SPERR], as the error registers are always loaded upon the occurrence of each protection violation. Address: 4000_D000h base + 10h offset + (8d × i), where i=0d to 4d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EADDR W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • MPU_EARn field descriptions Field Description 31–0 EADDR Error Address Indicates the reference address from slave port n that generated the access error Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 410 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 411

19.3.3 Error Detail Register, slave port n (MPU_EDRn) When the MPU detects an access error on slave port n, 32 bits of error detail are captured in this read-only register and the corresponding bit in CESR[SPERR] is set. Information on the faulting address is captured in the corresponding EARn register at the same time. This register and the corresponding EARn register contain the most recent access error; there are no hardware interlocks with CESR[SPERR] as the error registers are always loaded upon the occurrence of each protection violation. Address: 4000_D000h base + 14h offset + (8d × i), where i=0d to 4d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R EACD W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 EMN EATTR ERW W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • MPU_EDRn field descriptions Field Description 31–16 EACD Error Access Control Detail Indicates the region descriptor with the access error. • If EDRn contains a captured error and EACD is cleared, an access did not hit in any region descriptor. • If only a single EACD bit is set, the protection error was caused by a single non-overlapping region descriptor. • If two or more EACD bits are set, the protection error was caused by an overlapping set of region descriptors. 15–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7–4 EMN Error Master Number Indicates the bus master that generated the access error. 3–1 EATTR Error Attributes Indicates attribute information about the faulting reference. NOTE: All other encodings are reserved. 000 User mode, instruction access 001 User mode, data access Table continues on the next page... Chapter 19 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 411 General Business Information

Page 412

MPU_EDRn field descriptions (continued) Field Description 010 Supervisor mode, instruction access 011 Supervisor mode, data access 0 ERW Error Read/Write Indicates the access type of the faulting reference. 0 Read 1 Write 19.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0) The first word of the region descriptor defines the 0-modulo-32 byte start address of the memory region. Writes to this register clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). Address: 4000_D000h base + 400h offset + (16d × i), where i=0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SRTADDR 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPU_RGDn_WORD0 field descriptions Field Description 31–5 SRTADDR Start Address Defines the most significant bits of the 0-modulo-32 byte start address of the memory region. 4–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1) The second word of the region descriptor defines the 31-modulo-32 byte end address of the memory region. Writes to this register clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). Address: 4000_D000h base + 404h offset + (16d × i), where i=0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ENDADDR Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 412 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 413

MPU_RGDn_WORD1 field descriptions Field Description 31–5 ENDADDR End Address Defines the most significant bits of the 31-modulo-32 byte end address of the memory region. NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR. 4–0 Reserved This field is reserved. 19.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2) The third word of the region descriptor defines the access control rights of the memory region. The access control privileges depend on two broad classifications of bus masters: • Bus masters 0–3 have a 5-bit field defining separate privilege rights for user and supervisor mode accesses. • Bus masters 4–7 are limited to separate read and write permissions. For the privilege rights of bus masters 0–3, there are three flags associated with this function: • Read (r) refers to accessing the referenced memory address using an operand (data) fetch • Write (w) refers to updating the referenced memory address using a store (data) instruction • Execute (x) refers to reading the referenced memory address using an instruction fetch Writes to RGDn_WORD2 clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn instead because stores to these locations do not affect the descriptor’s valid bit. Address: 4000_D000h base + 408h offset + (16d × i), where i=0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R M7RE M7WE M6RE M6WE M5RE M5WE M4RE M4WE Reserved M3SM M3UM Reserved M2S M W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 19 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 413 General Business Information

Page 414

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R M2S M M2UM Reserved M1SM M1UM Reserved M0SM M0UM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPU_RGDn_WORD2 field descriptions Field Description 31 M7RE Bus Master 7 Read Enable 0 Bus master 7 reads terminate with an access error and the read is not performed 1 Bus master 7 reads allowed 30 M7WE Bus Master 7 Write Enable 0 Bus master 7 writes terminate with an access error and the write is not performed 1 Bus master 7 writes allowed 29 M6RE Bus Master 6 Read Enable 0 Bus master 6 reads terminate with an access error and the read is not performed 1 Bus master 6 reads allowed 28 M6WE Bus Master 6 Write Enable 0 Bus master 6 writes terminate with an access error and the write is not performed 1 Bus master 6 writes allowed 27 M5RE Bus Master 5 Read Enable 0 Bus master 5 reads terminate with an access error and the read is not performed 1 Bus master 5 reads allowed 26 M5WE Bus Master 5 Write Enable 0 Bus master 5 writes terminate with an access error and the write is not performed 1 Bus master 5 writes allowed 25 M4RE Bus Master 4 Read Enable 0 Bus master 4 reads terminate with an access error and the read is not performed 1 Bus master 4 reads allowed 24 M4WE Bus Master 4 Write Enable 0 Bus master 4 writes terminate with an access error and the write is not performed 1 Bus master 4 writes allowed 23 Reserved This field is reserved. This bit must be written with a zero. 22–21 M3SM Bus Master 3 Supervisor Mode Access Control Defines the access controls for bus master 3 in Supervisor mode. 00 r/w/x; read, write and execute allowed 01 r/x; read and execute allowed, but no write Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 414 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 415

MPU_RGDn_WORD2 field descriptions (continued) Field Description 10 r/w; read and write allowed, but no execute 11 Same as User mode defined in M3UM 20–18 M3UM Bus Master 3 User Mode Access Control Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits, enabling read (r), write (w), and execute (x) permissions. 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 1 Allows the given access type to occur 17 Reserved This field is reserved. This bit must be written with a zero. 16–15 M2SM Bus Master 2 Supervisor Mode Access Control See M3SM description. 14–12 M2UM Bus Master 2 User Mode Access control See M3UM description. 11 Reserved This field is reserved. This bit must be written with a zero. 10–9 M1SM Bus Master 1 Supervisor Mode Access Control See M3SM description. 8–6 M1UM Bus Master 1 User Mode Access Control See M3UM description. 5 Reserved This field is reserved. This bit must be written with a zero. 4–3 M0SM Bus Master 0 Supervisor Mode Access Control See M3SM description. 2–0 M0UM Bus Master 0 User Mode Access Control See M3UM description. Chapter 19 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 415 General Business Information

Page 416

19.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3) The fourth word of the region descriptor contains the region descriptor’s valid bit. Address: 4000_D000h base + 40Ch offset + (16d × i), where i=0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 VLD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPU_RGDn_WORD3 field descriptions Field Description 31–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 VLD Valid Signals the region descriptor is valid. Any write to RGDn_WORD0–2 clears this bit. 0 Region descriptor is invalid 1 Region descriptor is valid Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 416 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 417

19.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn) Because software may adjust only the access controls within a region descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of this 32- bit entity is available. Writing to this register does not affect the descriptor’s valid bit. Address: 4000_D000h base + 800h offset + (4d × i), where i=0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R M7RE M7WE M6RE M6WE M5RE M5WE M4RE M4WE Reserved M3SM M3UM Reserved M2S M W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R M2S M M2UM Reserved M1SM M1UM Reserved M0SM M0UM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPU_RGDAACn field descriptions Field Description 31 M7RE Bus Master 7 Read Enable 0 Bus master 7 reads terminate with an access error and the read is not performed 1 Bus master 7 reads allowed 30 M7WE Bus Master 7 Write Enable 0 Bus master 7 writes terminate with an access error and the write is not performed 1 Bus master 7 writes allowed 29 M6RE Bus Master 6 Read Enable 0 Bus master 6 reads terminate with an access error and the read is not performed 1 Bus master 6 reads allowed 28 M6WE Bus Master 6 Write Enable 0 Bus master 6 writes terminate with an access error and the write is not performed 1 Bus master 6 writes allowed 27 M5RE Bus Master 5 Read Enable 0 Bus master 5 reads terminate with an access error and the read is not performed 1 Bus master 5 reads allowed Table continues on the next page... Chapter 19 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 417 General Business Information

Page 418

MPU_RGDAACn field descriptions (continued) Field Description 26 M5WE Bus Master 5 Write Enable 0 Bus master 5 writes terminate with an access error and the write is not performed 1 Bus master 5 writes allowed 25 M4RE Bus Master 4 Read Enable 0 Bus master 4 reads terminate with an access error and the read is not performed 1 Bus master 4 reads allowed 24 M4WE Bus Master 4 Write Enable 0 Bus master 4 writes terminate with an access error and the write is not performed 1 Bus master 4 writes allowed 23 Reserved This field is reserved. This bit must be written with a zero. 22–21 M3SM Bus Master 3 Supervisor Mode Access Control Defines the access controls for bus master 3 in Supervisor mode. 00 r/w/x; read, write and execute allowed 01 r/x; read and execute allowed, but no write 10 r/w; read and write allowed, but no execute 11 Same as User mode defined in M3UM 20–18 M3UM Bus Master 3 User Mode Access Control Defines the access controls for bus master 3 in user mode. M3UM consists of three independent bits, enabling read (r), write (w), and execute (x) permissions. 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 1 Allows the given access type to occur 17 Reserved This field is reserved. This bit must be written with a zero. 16–15 M2SM Bus Master 2 Supervisor Mode Access Control See M3SM description. 14–12 M2UM Bus Master 2 User Mode Access Control See M3UM description. 11 Reserved This field is reserved. This bit must be written with a zero. 10–9 M1SM Bus Master 1 Supervisor Mode Access Control See M3SM description. 8–6 M1UM Bus Master 1 User Mode Access Control See M3UM description. 5 Reserved This field is reserved. This bit must be written with a zero. 4–3 M0SM Bus Master 0 Supervisor Mode Access Control Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 418 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 419

MPU_RGDAACn field descriptions (continued) Field Description See M3SM description. 2–0 M0UM Bus Master 0 User Mode Access Control See M3UM description. 19.4 Functional description In this section, the functional operation of the MPU is detailed, including the operation of the access evaluation macro and the handling of error-terminated bus cycles. 19.4.1 Access evaluation macro The basic operation of the MPU is performed in the access evaluation macro, a hardware structure replicated in the two-dimensional connection matrix. As shown in the following figure, the access evaluation macro inputs the crossbar bus address phase signals and the contents of a region descriptor (RGDn) and performs two major functions: • Region hit determination • Detection of an access protection violation The following figure shows a functional block diagram. start end error 8 8 RGDn MPU_EDRn Access not allowed 8 7 hit_b Address (hit AND error) (no hit OR error) r,w,x Figure 19-80. MPU access evaluation macro Chapter 19 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 419 General Business Information

Page 420

19.4.1.1 Hit determination To determine whether the current reference hits in the given region, two magnitude comparators are used with the region's start and end addresses. The boolean equation for this portion of the hit determination is: region_hit = ((addr[31:5] >= RGDn_Word0[SRTADDR]) & (addr[31:5] <= RGDn_Word1[ENDADDR])) & RGDn_Word3[VLD] where addr is the current reference address, RGDn_Word0[SRTADDR] and RGDn_Word1[ENDADDR] are the start and end addresses, and RGDn_Word3[VLD] is the valid bit. NOTE The MPU does not verify that ENDADDR ≥ SRTADDR. 19.4.1.2 Privilege violation determination While the access evaluation macro is determining region hit, the logic is also evaluating if the current access is allowed by the permissions defined in the region descriptor. Using the master and supervisor/user mode signals, a set of effective permissions is generated from the appropriate fields in the region descriptor. The protection violation logic then evaluates the access against the effective permissions using the specification shown below. Table 19-80. Protection violation definition Description MxUM Protection violation? r w x Instruction fetch read — — 0 Yes, no execute permission — — 1 No, access is allowed Data read 0 — — Yes, no read permission 1 — — No, access is allowed Data write — 0 — Yes, no write permission — 1 — No, access is allowed 19.4.2 Putting it all together and error terminations For each slave port monitored, the MPU performs a reduction-AND of all the individual terms from each access evaluation macro. This expression then terminates the bus cycle with an error and reports a protection error for three conditions: Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 420 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 421

• If the access does not hit in any region descriptor, a protection error is reported. • If the access hits in a single region descriptor and that region signals a protection violation, a protection error is reported. • If the access hits in multiple (overlapping) regions and all regions signal protection violations, a protection error is reported. As shown in the third condition, granting permission is a higher priority than denying access for overlapping regions. This approach is more flexible to system software in region descriptor assignments. For an example of the use of overlapping region descriptors, see Application information. 19.4.3 Power management Disabling the MPU by clearing CESR[VLD] minimizes power dissipation. To minimize the power dissipation of an enabled MPU, invalidate unused region descriptors by clearing the associated RGDn_Word3[VLD] bits. 19.5 Initialization information At system startup, load the appropriate number of region descriptors, including setting RGDn_Word3[VLD]. Setting CESR[VLD] enables the module. If the system requires that all the loaded region descriptors be enabled simultaneously, first ensure that the entire MPU is disabled (CESR[VLD]=0). Note A region descriptor must be set to allow access to the MPU registers if further changes are needed. 19.6 Application information In an operational system, interfacing with the MPU is generally classified into the following activities: Chapter 19 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 421 General Business Information

Page 422

• Creating a new memory region—Load the appropriate region descriptor into an available RGDn, using four sequential 32-bit writes. The hardware assists in the maintenance of the valid bit, so if this approach is followed, there are no coherency issues with the multi-cycle descriptor writes. (Clearing RGDn_Word3[VLD] deletes/ removes an existing memory region.) • Altering only access privileges—To not affect the valid bit, write to the alternate version of the access control word (RGDAACn), so there are no coherency issues involved with the update. When the write completes, the memory region's access rights switch instantaneously to the new value. • Changing a region's start and end addresses—Write a minimum of three words to the region descriptor (RGDn_Word{0,1,3}). Word 0 and 1 redefine the start and end addresses, respectively. Word 3 re-enables the region descriptor valid bit. In most situations, all four words of the region descriptor are rewritten. • Accessing the MPU—Allocate a region descriptor to restrict MPU access to supervisor mode from a specific master. • Detecting an access error—The current bus cycle is terminated with an error response and EARn and EDRn capture information on the faulting reference. The error-terminated bus cycle typically initiates an error response in the originating bus master. For example, a processor core may respond with a bus error exception, while a data movement bus master may respond with an error interrupt. The processor can retrieve the captured error address and detail information simply by reading E{A,D}Rn. CESR[SPERR] signals which error registers contain captured fault data. • Overlapping region descriptors—Applying overlapping regions often reduces the number of descriptors required for a given set of access controls. In the overlapping memory space, the protection rights of the corresponding region descriptors are logically summed together (the boolean OR operator). The following dual-core system example contains four bus masters: • The two processors: CP0, CP1 • Two DMA engines: DMA1, a traditional data movement engine transferring data between RAM and peripherals and DMA2, a second engine transferring data to/ from the RAM only Consider the following region descriptor assignments: Application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 422 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 423

Table 19-81. Overlapping region descriptor example Region description RGDn CP0 CP1 DMA1 DMA2 CP0 code 0 rwx r-- — — Flash CP1 code 1 r-- rwx — — CP0 data & stack 2 rw- — — — RAM CP0 → CP1 shared data 2 3 r-- r-- — — CP1 → CP0 shared data 4 CP1 data & stack 4 — rw- — — Shared DMA data 5 rw- rw- rw rw MPU 6 rw- rw- — — Peripheral space Peripherals 7 rw- rw- rw — In this example, there are eight descriptors used to span nine regions in the three main spaces of the system memory map: flash, RAM, and peripheral space. Each region indicates the specific permissions for each of the four bus masters and this definition provides an appropriate set of shared, private and executable memory spaces. Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4. The space defined by RGD2 with no overlap is a private data and stack area that provides read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines a shared data space for passing data from CP0 to CP1 and the access controls are defined by the logical OR of the two region descriptors. Thus, CP0 has (rw- | r--) = (rw-) permissions, while CP1 has (--- | r--) = (r--) permission in this space. Both DMA engines are excluded from this shared processor data region. The overlapping spaces between RGD3 and RGD4 defines another shared data space, this one for passing data from CP1 to CP0. For this overlapping space, CP0 has (r-- | ---) = (r--) permission, while CP1 has (rw- | r--) = (rw-) permission. The non-overlapped space of RGD4 defines a private data and stack area for CP1 only. The space defined by RGD5 is a shared data region, accessible by all four bus masters. Finally, the slave peripheral space mapped onto the IPS bus is partitioned into two regions: • One containing the MPU's programming model accessible only to the two processor cores • The remaining peripheral region accessible to both processors and the traditional DMA1 master This example shows one possible application of the capabilities of the MPU in a typical system. Chapter 19 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 423 General Business Information

Page 424

Application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 424 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 425

Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The peripheral bridge converts the crossbar switch interface to an interface that can access a majority of slave peripherals on the device. The peripheral bridge supports up to 128 peripherals, each with a 4K-byte address space. (Not all peripheral slots might be used. See the chip configuration chapter and memory map chapter for details on slot assignment.) The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals. 20.1.1 Features Key features of the peripheral bridge are: • Supports up to 128 peripherals • Supports peripheral slots with 8-, 16-, and 32-bit datapath width • Dedicated clock enables for independently configurable peripherals allow each on- or off-platform peripheral to operate at any integer-divisible speed less than or equal to the system clock frequency. • Programming model provides memory protection functionality K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 425 General Business Information

Page 426

20.1.2 General operation The slave devices connected to the peripheral bridge are modules which contain a programming model of control and status registers. The system masters read and write these registers through the peripheral bridge. The peripheral bridge performs a bus protocol conversion of the master transactions and generates the following as inputs to the peripherals: • Module enables • Module addresses • Transfer attributes • Byte enables • Write data The peripheral bridge selects and captures read data from the peripheral interface and returns it to the crossbar switch. The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is allocated one or more 4-KB block(s) of the memory map. 20.2 Memory map/register definition The 32-bit peripheral bridge registers can be accessed only in supervisor mode by trusted bus masters. Additionally, these registers must be read from or written to only by a 32-bit aligned access. The peripheral bridge registers are mapped into the PACRA[PACR0] address space. NOTE The number of fields and registers available depends on the device-specific implementation of the peripheral bridge module. See the chip configuration chapter for more information. AIPS memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_0000 Master Privilege Register A (AIPS0_MPRA) 32 R/W Undefined 20.2.1/428 4000_0020 Peripheral Access Control Register (AIPS0_PACRA) 32 R/W 4444_4444 _4444_4444h 20.2.2/431 4000_0024 Peripheral Access Control Register (AIPS0_PACRB) 32 R/W 4444_4444 _4444_4444h 20.2.2/431 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 426 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 427

AIPS memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_0028 Peripheral Access Control Register (AIPS0_PACRC) 32 R/W 4444_4444 _4444_4444h 20.2.2/431 4000_002C Peripheral Access Control Register (AIPS0_PACRD) 32 R/W 4444_4444 _4444_4444h 20.2.2/431 4000_0040 Peripheral Access Control Register (AIPS0_PACRE) 32 R/W Undefined 20.2.3/436 4000_0044 Peripheral Access Control Register (AIPS0_PACRF) 32 R/W Undefined 20.2.3/436 4000_0048 Peripheral Access Control Register (AIPS0_PACRG) 32 R/W Undefined 20.2.3/436 4000_004C Peripheral Access Control Register (AIPS0_PACRH) 32 R/W Undefined 20.2.3/436 4000_0050 Peripheral Access Control Register (AIPS0_PACRI) 32 R/W Undefined 20.2.3/436 4000_0054 Peripheral Access Control Register (AIPS0_PACRJ) 32 R/W Undefined 20.2.3/436 4000_0058 Peripheral Access Control Register (AIPS0_PACRK) 32 R/W Undefined 20.2.3/436 4000_005C Peripheral Access Control Register (AIPS0_PACRL) 32 R/W Undefined 20.2.3/436 4000_0060 Peripheral Access Control Register (AIPS0_PACRM) 32 R/W Undefined 20.2.3/436 4000_0064 Peripheral Access Control Register (AIPS0_PACRN) 32 R/W Undefined 20.2.3/436 4000_0068 Peripheral Access Control Register (AIPS0_PACRO) 32 R/W Undefined 20.2.3/436 4000_006C Peripheral Access Control Register (AIPS0_PACRP) 32 R/W Undefined 20.2.3/436 4008_0000 Master Privilege Register A (AIPS1_MPRA) 32 R/W Undefined 20.2.1/428 4008_0020 Peripheral Access Control Register (AIPS1_PACRA) 32 R/W 4444_4444 _4444_4444h 20.2.2/431 4008_0024 Peripheral Access Control Register (AIPS1_PACRB) 32 R/W 4444_4444 _4444_4444h 20.2.2/431 4008_0028 Peripheral Access Control Register (AIPS1_PACRC) 32 R/W 4444_4444 _4444_4444h 20.2.2/431 4008_002C Peripheral Access Control Register (AIPS1_PACRD) 32 R/W 4444_4444 _4444_4444h 20.2.2/431 4008_0040 Peripheral Access Control Register (AIPS1_PACRE) 32 R/W Undefined 20.2.3/436 4008_0044 Peripheral Access Control Register (AIPS1_PACRF) 32 R/W Undefined 20.2.3/436 4008_0048 Peripheral Access Control Register (AIPS1_PACRG) 32 R/W Undefined 20.2.3/436 4008_004C Peripheral Access Control Register (AIPS1_PACRH) 32 R/W Undefined 20.2.3/436 4008_0050 Peripheral Access Control Register (AIPS1_PACRI) 32 R/W Undefined 20.2.3/436 4008_0054 Peripheral Access Control Register (AIPS1_PACRJ) 32 R/W Undefined 20.2.3/436 4008_0058 Peripheral Access Control Register (AIPS1_PACRK) 32 R/W Undefined 20.2.3/436 4008_005C Peripheral Access Control Register (AIPS1_PACRL) 32 R/W Undefined 20.2.3/436 4008_0060 Peripheral Access Control Register (AIPS1_PACRM) 32 R/W Undefined 20.2.3/436 4008_0064 Peripheral Access Control Register (AIPS1_PACRN) 32 R/W Undefined 20.2.3/436 4008_0068 Peripheral Access Control Register (AIPS1_PACRO) 32 R/W Undefined 20.2.3/436 4008_006C Peripheral Access Control Register (AIPS1_PACRP) 32 R/W Undefined 20.2.3/436 Chapter 20 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 427 General Business Information

Page 428

20.2.1 Master Privilege Register A (AIPSx_MPRA) The MPRA specifies identical 4-bit fields defining the access-privilege level associated with a bus master in the device to various peripherals. The register provides one field per bus master. NOTE At reset, the default value loaded into the MPRA fields is device-specific. See the chip configuration details for the value of a particular device. A register field that maps to an unimplemented master or peripheral behaves as read- only-zero. Each master is assigned depending on its connection to the crossbar switch master ports. See device-specific chip configuration details for information about the master assignments to these registers. Address: Base address + 0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 MTR0 MTW0 MPL0 0 MTR1 MTW1 MPL1 0 MTR2 MTW2 MPL2 0 MTR3 MTW3 MPL3 W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 MTR4 MTW4 MPL4 0 MTR5 MTW5 MPL5 0 0 W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • AIPSx_MPRA field descriptions Field Description 31 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30 MTR0 Master Trusted For Read Determines whether the master is trusted for read accesses. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 428 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 429

AIPSx_MPRA field descriptions (continued) Field Description 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. 29 MTW0 Master Trusted For Writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. 28 MPL0 Master Privilege Level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. 27 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26 MTR1 Master trusted for read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. 25 MTW1 Master trusted for writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. 24 MPL1 Master privilege level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. 23 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 22 MTR2 Master Trusted For Read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. 21 MTW2 Master Trusted For Writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. 20 MPL2 Master Privilege Level Specifies how the privilege level of the master is determined. Table continues on the next page... Chapter 20 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 429 General Business Information

Page 430

AIPSx_MPRA field descriptions (continued) Field Description 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. 19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 MTR3 Master Trusted For Read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. 17 MTW3 Master Trusted For Writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. 16 MPL3 Master Privilege Level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. 15 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 14 MTR4 Master Trusted For Read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. 13 MTW4 Master Trusted For Writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. 12 MPL4 Master Privilege Level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. 11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10 MTR5 Master Trusted For Read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 430 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 431

AIPSx_MPRA field descriptions (continued) Field Description 9 MTW5 Master Trusted For Writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. 8 MPL5 Master Privilege Level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. 7–4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 20.2.2 Peripheral Access Control Register (AIPSx_PACRn) Each of the peripherals has a 4-bit PACR[0: 127 ] field which defines the access levels supported by the given module. Eight PACR fields are grouped together to form a 32-bit PACR[A: P ] register: • PACRA- P define the access levels for the 128 peripherals The peripheral assignments to each PACR are defined by the memory map slot that the peripherals are assigned. See the device's memory map details for the assignments for a particular device. NOTE The reset value of PACR[A:D] is 0x4444_4444. The following table shows the top-level structure of PACRs. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 Reserved 0x3C Reserved Table continues on the next page... Chapter 20 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 431 General Business Information

Page 432

Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 Address: Base address + 20h offset + (4d × i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SP0 WP0 TP0 0 SP1 WP1 TP1 0 SP2 WP2 TP2 0 SP3 WP3 TP3 W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SP4 WP4 TP4 0 SP5 WP5 TP5 0 SP6 WP6 TP6 0 SP7 WP7 TP7 W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 AIPSx_PACRn field descriptions Field Description 31 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30 SP0 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 29 WP0 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 28 TP0 Trusted Protect Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 432 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 433

AIPSx_PACRn field descriptions (continued) Field Description Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 27 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26 SP1 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 25 WP1 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 24 TP1 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 23 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 22 SP2 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 21 WP2 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 20 TP2 Trusted Protect Table continues on the next page... Chapter 20 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 433 General Business Information

Page 434

AIPSx_PACRn field descriptions (continued) Field Description Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 SP3 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 17 WP3 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 16 TP3 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 15 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 14 SP4 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 13 WP4 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 12 TP4 Trusted protect Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 434 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 435

AIPSx_PACRn field descriptions (continued) Field Description Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10 SP5 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 9 WP5 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 8 TP5 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 SP6 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 5 WP6 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 4 TP6 Trusted Protect Table continues on the next page... Chapter 20 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 435 General Business Information

Page 436

AIPSx_PACRn field descriptions (continued) Field Description Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 SP7 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 1 WP7 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 0 TP7 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 20.2.3 Peripheral Access Control Register (AIPSx_PACRn) Each of the peripherals has a 4-bit PACR[0: 127 ] field which defines the access levels supported by this module. Eight PACR fields are grouped together to form a 32-bit PACR[A: P ]: • PACRA- P define the access levels for the 128 peripherals The peripheral assignments to each PACR are defined by the memory map slot that the peripherals are assigned. See the device's memory map details for the assignments for a particular device. NOTE The reset value of the PACRE- P depends on the device's configuration. Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 436 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 437

Address: Base address + 40h offset + (4d × i), where i=0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SP0 WP0 TP0 0 SP1 WP1 TP1 0 SP2 WP2 TP2 0 SP3 WP3 TP3 W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SP4 WP4 TP4 0 SP5 WP5 TP5 0 SP6 WP6 TP6 0 SP7 WP7 TP7 W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • AIPSx_PACRn field descriptions Field Description 31 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30 SP0 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 29 WP0 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 28 TP0 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 27 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26 SP1 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for access. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. Table continues on the next page... Chapter 20 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 437 General Business Information

Page 438

AIPSx_PACRn field descriptions (continued) Field Description 25 WP1 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 24 TP1 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 23 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 22 SP2 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attributeMPR x [MPL n ], and the MPR x [MPL n ] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 21 WP2 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 20 TP2 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 SP3 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 438 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 439

AIPSx_PACRn field descriptions (continued) Field Description 17 WP3 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 16 TP3 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 15 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 14 SP4 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 13 WP4 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 12 TP4 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10 SP5 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. Table continues on the next page... Chapter 20 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 439 General Business Information

Page 440

AIPSx_PACRn field descriptions (continued) Field Description 9 WP5 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 8 TP5 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 SP6 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. 5 WP6 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 4 TP6 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 SP7 Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 440 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 441

AIPSx_PACRn field descriptions (continued) Field Description 1 WP7 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 This peripheral allows write accesses. 1 This peripheral is write protected. 0 TP7 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. 20.3 Functional description The peripheral bridge functions as a bus protocol translator between the crossbar switch and the slave peripheral bus. The peripheral bridge manages all transactions destined for the attached slave devices and generates select signals for modules on the peripheral bus by decoding accesses within the attached address space. By default, reads and writes on the crossbar side of the peripheral bridge take two data- phase cycles. On the IPS side, accesses complete in one cycle. If wait states are inserted by the slave peripheral, access time will be extended accordingly. 20.3.1 Access support All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted which is larger than the targeted port, an error response is generated. Chapter 20 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 441 General Business Information

Page 442

Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 442 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 443

Chapter 21 Direct Memory Access Multiplexer (DMAMUX) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. 21.1.1 Overview The direct memory access multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 16 DMA channels. This process is illustrated in the following figure. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 443 General Business Information

Page 444

DMA Channel #0 Source #1 Source #2 Source #3 Always #1 DMA Channel #n Always #y Source #x Trigger #1 Trigger #z DMA Channel #1 DMAMUX Figure 21-1. DMAMUX block diagram 21.1.2 Features The DMA channel MUX provides these features: • 52 peripheral slots and 10 always-on slots can be routed to 16 channels. • 16 independently selectable DMA channel routers. • The first 4 channels additionally provide a trigger functionality. • Each channel router can be assigned to one of the 52 possible peripheral DMA slots or to one of the 10 always-on slots. 21.1.3 Modes of operation The following operating modes are available: • Disabled mode Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 444 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 445

In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger. • Normal mode In this mode, a DMA source is routed directly to the specified DMA channel. The operation of the DMA MUX in this mode is completely transparent to the system. • Periodic Trigger mode In this mode, a DMA source may only request a DMA transfer, such as when a transmit buffer becomes empty or a receive buffer becomes full, periodically. Configuration of the period is done in the registers of the periodic interrupt timer (PIT). This mode is available only for channels 0-3. 21.2 External signal description The DMA MUX has no external pins. 21.3 Memory map/register definition This section provides a detailed description of all memory-mapped registers in the DMA MUX. DMAMUX memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4002_1000 Channel Configuration register (DMAMUX_CHCFG0) 8 R/W 000h 21.3.1/446 4002_1001 Channel Configuration register (DMAMUX_CHCFG1) 8 R/W 000h 21.3.1/446 4002_1002 Channel Configuration register (DMAMUX_CHCFG2) 8 R/W 000h 21.3.1/446 4002_1003 Channel Configuration register (DMAMUX_CHCFG3) 8 R/W 000h 21.3.1/446 4002_1004 Channel Configuration register (DMAMUX_CHCFG4) 8 R/W 000h 21.3.1/446 4002_1005 Channel Configuration register (DMAMUX_CHCFG5) 8 R/W 000h 21.3.1/446 4002_1006 Channel Configuration register (DMAMUX_CHCFG6) 8 R/W 000h 21.3.1/446 4002_1007 Channel Configuration register (DMAMUX_CHCFG7) 8 R/W 000h 21.3.1/446 4002_1008 Channel Configuration register (DMAMUX_CHCFG8) 8 R/W 000h 21.3.1/446 Table continues on the next page... Chapter 21 Direct Memory Access Multiplexer (DMAMUX) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 445 General Business Information

Page 446

DMAMUX memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4002_1009 Channel Configuration register (DMAMUX_CHCFG9) 8 R/W 000h 21.3.1/446 4002_100A Channel Configuration register (DMAMUX_CHCFG10) 8 R/W 000h 21.3.1/446 4002_100B Channel Configuration register (DMAMUX_CHCFG11) 8 R/W 000h 21.3.1/446 4002_100C Channel Configuration register (DMAMUX_CHCFG12) 8 R/W 000h 21.3.1/446 4002_100D Channel Configuration register (DMAMUX_CHCFG13) 8 R/W 000h 21.3.1/446 4002_100E Channel Configuration register (DMAMUX_CHCFG14) 8 R/W 000h 21.3.1/446 4002_100F Channel Configuration register (DMAMUX_CHCFG15) 8 R/W 000h 21.3.1/446 21.3.1 Channel Configuration register (DMAMUX_CHCFGn) Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA slots (peripheral slots or always-on slots) in the system. NOTE Setting multiple CHCFG registers with the same Source value will result in unpredictable behavior. NOTE Before changing the trigger or source settings a DMA channel must be disabled via the CHCFGn[ENBL] bit. Address: 4002_1000h base + 0h offset + (1d × i), where i=0d to 15d Bit 7 6 5 4 3 2 1 0 Read ENBL TRIG SOURCE Write Reset 0 0 0 0 0 0 0 0 DMAMUX_CHCFGn field descriptions Field Description 7 ENBL DMA Channel Enable Enables the DMA channel. 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. 1 DMA channel is enabled 6 TRIG DMA Channel Trigger Enable Enables the periodic trigger capability for the triggered DMA channel. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 446 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 447

DMAMUX_CHCFGn field descriptions (continued) Field Description 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode. 5–0 SOURCE DMA Channel Source (Slot) Specifies which DMA source, if any, is routed to a particular DMA channel. See your device's chip configuration details for further details about the peripherals and their slot numbers. 21.4 Functional description The primary purpose of the DMA MUX is to provide flexibility in the system's use of the available DMA channels. As such, configuration of the DMA MUX is intended to be a static procedure done during execution of the system boot code. However, if the procedure outlined in Enabling and configuring sources is followed, the configuration of the DMA MUX may be changed during the normal operation of the system. Functionally, the DMA MUX channels may be divided into two classes: • Channels which implement the normal routing functionality plus periodic triggering capability • Channels which implement only the normal routing functionality 21.4.1 DMA channels with periodic triggering capability Besides the normal routing functionality, the first 4 channels of the DMA MUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or packets at fixed intervals without the need for processor intervention. The trigger is generated by the periodic interrupt timer (PIT); as such, the configuration of the periodic triggering interval is done via configuration registers in the PIT. See the section on periodic interrupt timer for more information on this topic. Note Because of the dynamic nature of the system (i.e. DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. Chapter 21 Direct Memory Access Multiplexer (DMAMUX) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 447 General Business Information

Page 448

DMA Channel #0 Trigger #2 Source #1 Source #2 Source #3 Always #1 DMA Channel #3 Always #y Trigger #4 Source #x Trigger #1 DMA Channel #1 Figure 21-19. DMA MUX triggered channels The DMA channel triggering capability allows the system to "schedule" regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in the following figure. DMA Request Peripheral Request Trigger Figure 21-20. DMA MUX channel triggering: normal operation After the DMA request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peripheral re-asserts its request AND the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 448 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 449

DMA Request Peripheral Request Trigger Figure 21-21. DMA MUX channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: • Periodically polling external devices on a particular bus. As an example, the transmit side of an SPI is assigned to a DMA channel with a trigger, as described above. After it has been setup, the SPI will request DMA transfers, presumably from memory, as long as its transmit buffer is empty. By using a trigger on this channel, the SPI transfers can be automatically performed every 5μs (as an example). On the receive side of the SPI, the SPI and DMA can be configured to transfer receive data into memory, effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention. • Using the GPIO ports to drive or sample waveforms. By configuring the DMA to transfer data to one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in on-chip memory. A more detailed description of the capability of each trigger, including resolution, range of values, and so on, may be found in the periodic interrupt timer section. 21.4.2 DMA channels with no triggering capability The other channels of the DMA MUX provide the normal routing functionality as described in Modes of operation. 21.4.3 "Always enabled" DMA sources In addition to the peripherals that can be used as DMA sources, there are 10 additional DMA sources that are "always enabled". Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the "always enabled" sources provide no such "throttling" of the data transfers. These sources are most useful in the following cases: Chapter 21 Direct Memory Access Multiplexer (DMAMUX) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 449 General Business Information

Page 450

• Performing DMA transfers to/from GPIO—Moving data from/to one or more GPIO pins, either unthrottled (that is as fast as possible), or periodically (using the DMA triggering capability). • Performing DMA transfers from memory to memory—Moving data from memory to memory, typically as fast as possible, sometimes with software activation. • Performing DMA transfers from memory to the external bus, or vice-versa—Similar to memory to memory transfers, this is typically done as quickly as possible. • Any DMA transfer that requires software activation—Any DMA transfer that should be explicitly started by software. In cases where software should initiate the start of a DMA transfer, an "always enabled" DMA source can be used to provide maximum flexibility. When activating a DMA channel via software, subsequent executions of the minor loop require a new "start" event be sent. This can either be a new software activation, or a transfer request from the DMA channel MUX. The options for doing this are: • Transfer all data in a single minor loop. By configuring the DMA to transfer all of the data in a single minor loop (that is major loop counter = 1), no reactivation of the channel is necessary. The disadvantage to this option is the reduced granularity in determining the load that the DMA transfer will incur on the system. For this option, the DMA channel must be disabled in the DMA channel MUX. • Use explicit software reactivation. In this option, the DMA is configured to transfer the data using both minor and major loops, but the processor is required to reactivate the channel by writing to the DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. • Use an "always enabled" DMA source. In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMA channel MUX does the channel re-activation. For this option, the DMA channel should be enabled and pointing to an "always enabled" source. Note that the reactivation of the channel can be continuous (DMA triggering is disabled) or can use the DMA triggering capability. In this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention. 21.5 Initialization/application information This section provides instructions for initializing the DMA channel MUX. Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 450 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 451

21.5.1 Reset The reset state of each individual bit is shown in Memory map/register definition. In summary, after reset, all channels are disabled and must be explicitly enabled before use. 21.5.2 Enabling and configuring sources To enable a source with periodic triggering:

Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability.
Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel.
Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point.
Configure the corresponding timer.
Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] bits are set. NOTE The following is an example. See Chip configuration section for the number of this device's DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 2, with periodic triggering capability:
Write 0x00 to CHCFG2 (base address + 0x02).
Configure channel 2 in the DMA, including enabling the channel.
Configure a timer for the desired trigger interval.
Write 0xC5 to CHCFG2 (base address + 0x02). The following code example illustrates steps 1 and 4 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! / / Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCONFIG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCONFIG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCONFIG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCONFIG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCONFIG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCONFIG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCONFIG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCONFIG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCONFIG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); Chapter 21 Direct Memory Access Multiplexer (DMAMUX) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 451 General Business Information

Page 452

volatile unsigned char *CHCONFIG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCONFIG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCONFIG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" : : *CHCONFIG2 = 0x00; *CHCONFIG2 = 0xC5; To enable a source without periodic triggering:

Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability.
Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel.
Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point.
Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] is set while the CHCFG[TRIG] bit is cleared. NOTE The following is an example. See Chip configuration section for the number of this device's DMA channels that have triggering capability. To configure source #5 Transmit for use with DMA channel 2, with no periodic triggering capability:
Write 0x00 to CHCFG2 (base address + 0x02).
Configure channel 2 in the DMA, including enabling the channel.
Write 0x85 to CHCFG2 (base address + 0x02). The following code example illustrates steps 1 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! / / Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCONFIG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCONFIG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCONFIG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCONFIG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCONFIG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCONFIG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCONFIG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCONFIG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCONFIG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCONFIG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCONFIG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCONFIG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 452 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 453

: : *CHCONFIG2 = 0x00; *CHCONFIG2 = 0x85; Disabling a source A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCFG registers. Additionally, some module-specific configuration may be necessary. See the appropriate section for more details. To switch the source of a DMA channel:

Disable the DMA channel in the DMA and re-configure the channel for the new source.
Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel.
Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] bits are set. To switch DMA channel 8 from source #5 transmit to source #7 transmit:
In the DMA configuration registers, disable DMA channel 8 and re-configure it to handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't have triggering capability.
Write 0x00 to CHCFG8 (base address + 0x08).
Write 0x87 to CHCFG8 (base address + 0x08). (In this example, setting the CHCFG[TRIG] bit would have no effect, due to the assumption that channels 8 does not support the periodic triggering functionality). The following code example illustrates steps 2 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! / / Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCONFIG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCONFIG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCONFIG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCONFIG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCONFIG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCONFIG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCONFIG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCONFIG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCONFIG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCONFIG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCONFIG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCONFIG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" : : *CHCONFIG8 = 0x00; *CHCONFIG8 = 0x87; Chapter 21 Direct Memory Access Multiplexer (DMAMUX) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 453 General Business Information

Page 454

Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 454 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 455

Chapter 22 Direct Memory Access Controller (eDMA) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. The hardware microarchitecture includes: • A DMA engine that performs: • Source- and destination-address calculations • Data-movement operations • Local memory containing transfer control descriptors for each of the 16 channels 22.1.1 Block diagram This diagram illustrates the eDMA module. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 455 General Business Information

Page 456

1 Transfer Control Descriptor (TCD) eDMA Engine Data Path eDMA 0 Program Model/ 64 Control n-1 To/From Crossbar Switch 2 Channel Arbitration Address Path Read Data Write Data Address Read Data Write Data Write Address Internal Peripheral Bus eDMA Peripheral Request eDMA Done Figure 22-1. eDMA block diagram 22.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory. The eDMA engine is further partitioned into four submodules: Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 456 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 457

Table 22-1. eDMA engine submodules Submodule Function Address path This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality. This structure allows data transfers associated with one channel to be preempted after the completion of a read/write sequence if a higher priority channel activation is asserted while the first channel is active. After a channel is activated, it runs until the minor loop is completed, unless preempted by a higher priority channel. This provides a mechanism (enabled by DCHPRIn[ECP]) where a large data move operation can be preempted to minimize the time another channel is blocked from execution. When any channel is selected to execute, the contents of its TCD are read from local memory and loaded into the address path channel x registers for a normal start and into channel y registers for a preemption start. After the minor loop completes execution, the address path hardware writes the new values for the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation. Data path This block implements the bus master read/write datapath. It includes 16 bytes of register storage and the necessary multiplex logic to support any required data alignment. The internal read data bus is the primary input, and the internal write data bus is the primary output. The address and data path modules directly support the 2-stage pipelined internal bus. The address path module represents the 1st stage of the bus pipeline (address phase), while the data path module implements the 2nd stage of the pipeline (data phase). Program model/channel arbitration This block implements the first section of the eDMA programming model as well as the channel arbitration logic. The programming model registers are connected to the internal peripheral bus. The eDMA peripheral request inputs and interrupt request outputs are also connected to this block (via control logic). Control This block provides all the control functions for the eDMA engine. For data transfers where the source and destination sizes are equal, the eDMA engine performs a series of source read/ destination write operations until the number of bytes specified in the minor loop byte count has moved. For descriptors where the sizes are not equal, multiple accesses of the smaller size data are required for each reference of the larger size. As an example, if the source size references 16- bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write. The transfer-control descriptor local memory is further partitioned into: Table 22-2. Transfer control descriptor memory Submodule Description Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage is implemented using a single-port, synchronous RAM array. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 457 General Business Information

Page 458

22.1.3 Features The eDMA is a highly-programmable data-transfer engine optimized to minimize the required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known and not defined within the data packet itself. The eDMA module features: • All data movement via dual-address transfers: read from source, write to destination • Programmable source and destination addresses and transfer size • Support for enhanced addressing modes • 16-channel implementation that performs complex data transfers with minimal intervention from a host processor • Internal data buffer, used as temporary storage to support 16-byte transfers • Connections to the crossbar switch for bus mastering the data movement • Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations • 32-byte TCD stored in local memory for each channel • An inner data transfer loop defined by a minor byte transfer count • An outer data transfer loop defined by a major iteration count • Channel activation via one of three methods: • Explicit software initiation • Initiation via a channel-to-channel linking mechanism for continuous transfers • Peripheral-paced hardware requests, one per channel • Fixed-priority and round-robin channel arbitration • Channel completion reported via optional interrupt requests • One interrupt per channel, optionally asserted at completion of major iteration count • Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller • Optional support for scatter/gather DMA processing • Support for complex data structures • Support to cancel transfers via software Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 458 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 459

In the discussion of this module, n is used to reference the channel number. 22.2 Modes of operation The eDMA operates in the following modes: Table 22-3. Modes of operation Mode Description Normal In Normal mode, the eDMA transfers data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that transfers these NBYTES per service request. Each service request executes one iteration of the major loop, which transfers NBYTES of data. Debug DMA operation is configurable in Debug mode via the control register: • If CR[EDBG] is cleared, the DMA continues to operate. • If CR[EDBG] is set, the eDMA stops transferring data. If Debug mode is entered while a channel is active, the eDMA continues operation until the channel retires. Wait Before entering Wait mode, the DMA attempts to complete its current transfer. After the transfer completes, the device enters Wait mode. 22.3 Memory map/register definition The eDMA's programming model is partitioned into two regions: • The first region defines a number of registers providing control functions • The second region corresponds to the local transfer control descriptor memory Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 15 . Each TCDn definition is presented as 11 registers of 16 or 32 bits. Reading reserved bits in a register returns the value of zero. Writes to reserved bits in a register are ignored. Reading or writing a reserved memory location generates a bus error. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 459 General Business Information

Page 460

DMA memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_8000 Control Register (DMA_CR) 32 R/W 0_0000 _0000h 22.3.1/470 4000_8004 Error Status Register (DMA_ES) 32 R 0_0000 _0000h 22.3.2/472 4000_800C Enable Request Register (DMA_ ERQ ) 32 R/W 0_0000 _0000h 22.3.3/474 4000_8014 Enable Error Interrupt Register (DMA_ EEI ) 32 R/W 0_0000 _0000h 22.3.4/476 4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI) 8 W (always reads 0) 000h 22.3.5/479 4000_8019 Set Enable Error Interrupt Register (DMA_SEEI) 8 W (always reads 0) 000h 22.3.6/480 4000_801A Clear Enable Request Register (DMA_CERQ) 8 W (always reads 0) 000h 22.3.7/481 4000_801B Set Enable Request Register (DMA_SERQ) 8 W (always reads 0) 000h 22.3.8/482 4000_801C Clear DONE Status Bit Register (DMA_CDNE) 8 W (always reads 0) 000h 22.3.9/483 4000_801D Set START Bit Register (DMA_SSRT) 8 W (always reads 0) 000h 22.3.10/484 4000_801E Clear Error Register (DMA_CERR) 8 W (always reads 0) 000h 22.3.11/485 4000_801F Clear Interrupt Request Register (DMA_CINT) 8 W (always reads 0) 000h 22.3.12/486 4000_8024 Interrupt Request Register (DMA_ INT ) 32 R/W 0_0000 _0000h 22.3.13/487 4000_802C Error Register (DMA_ ERR ) 32 R/W 0_0000 _0000h 22.3.14/489 4000_8034 Hardware Request Status Register (DMA_ HRS ) 32 R/W 0_0000 _0000h 22.3.15/492 4000_8100 Channel n Priority Register (DMA_DCHPRI3) 8 R/W See section 22.3.16/494 4000_8101 Channel n Priority Register (DMA_DCHPRI2) 8 R/W See section 22.3.16/494 4000_8102 Channel n Priority Register (DMA_DCHPRI1) 8 R/W See section 22.3.16/494 4000_8103 Channel n Priority Register (DMA_DCHPRI0) 8 R/W See section 22.3.16/494 4000_8104 Channel n Priority Register (DMA_DCHPRI7) 8 R/W See section 22.3.16/494 4000_8105 Channel n Priority Register (DMA_DCHPRI6) 8 R/W See section 22.3.16/494 4000_8106 Channel n Priority Register (DMA_DCHPRI5) 8 R/W See section 22.3.16/494 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 460 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 461

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_8107 Channel n Priority Register (DMA_DCHPRI4) 8 R/W See section 22.3.16/494 4000_8108 Channel n Priority Register (DMA_DCHPRI11) 8 R/W See section 22.3.16/494 4000_8109 Channel n Priority Register (DMA_DCHPRI10) 8 R/W See section 22.3.16/494 4000_810A Channel n Priority Register (DMA_DCHPRI9) 8 R/W See section 22.3.16/494 4000_810B Channel n Priority Register (DMA_DCHPRI8) 8 R/W See section 22.3.16/494 4000_810C Channel n Priority Register (DMA_DCHPRI15) 8 R/W See section 22.3.16/494 4000_810D Channel n Priority Register (DMA_DCHPRI14) 8 R/W See section 22.3.16/494 4000_810E Channel n Priority Register (DMA_DCHPRI13) 8 R/W See section 22.3.16/494 4000_810F Channel n Priority Register (DMA_DCHPRI12) 8 R/W See section 22.3.16/494 4000_9000 TCD Source Address (DMA_TCD0_SADDR) 32 R/W Undefined 22.3.17/495 4000_9004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) 16 R/W Undefined 22.3.18/495 4000_9006 TCD Transfer Attributes (DMA_TCD0_ATTR) 16 R/W Undefined 22.3.19/496 4000_9008 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD0_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_9008 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD0_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_9008 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD0_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_900C TCD Last Source Address Adjustment (DMA_TCD0_SLAST) 32 R/W Undefined 22.3.23/500 4000_9010 TCD Destination Address (DMA_TCD0_DADDR) 32 R/W Undefined 22.3.24/500 4000_9014 TCD Signed Destination Address Offset (DMA_TCD0_DOFF) 16 R/W Undefined 22.3.25/501 4000_9016 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD0_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_9016 DMA_TCD0_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_9018 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD0_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_901C TCD Control and Status (DMA_TCD0_CSR) 16 R/W Undefined 22.3.29/504 4000_901E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD0_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_901E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD0_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_9020 TCD Source Address (DMA_TCD1_SADDR) 32 R/W Undefined 22.3.17/495 4000_9024 TCD Signed Source Address Offset (DMA_TCD1_SOFF) 16 R/W Undefined 22.3.18/495 4000_9026 TCD Transfer Attributes (DMA_TCD1_ATTR) 16 R/W Undefined 22.3.19/496 4000_9028 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD1_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_9028 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD1_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 461 General Business Information

Page 462

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_9028 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD1_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_902C TCD Last Source Address Adjustment (DMA_TCD1_SLAST) 32 R/W Undefined 22.3.23/500 4000_9030 TCD Destination Address (DMA_TCD1_DADDR) 32 R/W Undefined 22.3.24/500 4000_9034 TCD Signed Destination Address Offset (DMA_TCD1_DOFF) 16 R/W Undefined 22.3.25/501 4000_9036 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD1_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_9036 DMA_TCD1_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_9038 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD1_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_903C TCD Control and Status (DMA_TCD1_CSR) 16 R/W Undefined 22.3.29/504 4000_903E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD1_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_903E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD1_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_9040 TCD Source Address (DMA_TCD2_SADDR) 32 R/W Undefined 22.3.17/495 4000_9044 TCD Signed Source Address Offset (DMA_TCD2_SOFF) 16 R/W Undefined 22.3.18/495 4000_9046 TCD Transfer Attributes (DMA_TCD2_ATTR) 16 R/W Undefined 22.3.19/496 4000_9048 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD2_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_9048 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD2_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_9048 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD2_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_904C TCD Last Source Address Adjustment (DMA_TCD2_SLAST) 32 R/W Undefined 22.3.23/500 4000_9050 TCD Destination Address (DMA_TCD2_DADDR) 32 R/W Undefined 22.3.24/500 4000_9054 TCD Signed Destination Address Offset (DMA_TCD2_DOFF) 16 R/W Undefined 22.3.25/501 4000_9056 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD2_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_9056 DMA_TCD2_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_9058 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD2_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_905C TCD Control and Status (DMA_TCD2_CSR) 16 R/W Undefined 22.3.29/504 4000_905E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD2_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_905E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD2_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 462 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 463

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_9060 TCD Source Address (DMA_TCD3_SADDR) 32 R/W Undefined 22.3.17/495 4000_9064 TCD Signed Source Address Offset (DMA_TCD3_SOFF) 16 R/W Undefined 22.3.18/495 4000_9066 TCD Transfer Attributes (DMA_TCD3_ATTR) 16 R/W Undefined 22.3.19/496 4000_9068 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD3_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_9068 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD3_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_9068 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD3_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_906C TCD Last Source Address Adjustment (DMA_TCD3_SLAST) 32 R/W Undefined 22.3.23/500 4000_9070 TCD Destination Address (DMA_TCD3_DADDR) 32 R/W Undefined 22.3.24/500 4000_9074 TCD Signed Destination Address Offset (DMA_TCD3_DOFF) 16 R/W Undefined 22.3.25/501 4000_9076 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD3_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_9076 DMA_TCD3_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_9078 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD3_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_907C TCD Control and Status (DMA_TCD3_CSR) 16 R/W Undefined 22.3.29/504 4000_907E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD3_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_907E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD3_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_9080 TCD Source Address (DMA_TCD4_SADDR) 32 R/W Undefined 22.3.17/495 4000_9084 TCD Signed Source Address Offset (DMA_TCD4_SOFF) 16 R/W Undefined 22.3.18/495 4000_9086 TCD Transfer Attributes (DMA_TCD4_ATTR) 16 R/W Undefined 22.3.19/496 4000_9088 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD4_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_9088 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD4_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_9088 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD4_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_908C TCD Last Source Address Adjustment (DMA_TCD4_SLAST) 32 R/W Undefined 22.3.23/500 4000_9090 TCD Destination Address (DMA_TCD4_DADDR) 32 R/W Undefined 22.3.24/500 4000_9094 TCD Signed Destination Address Offset (DMA_TCD4_DOFF) 16 R/W Undefined 22.3.25/501 4000_9096 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD4_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_9096 DMA_TCD4_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 463 General Business Information

Page 464

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_9098 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD4_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_909C TCD Control and Status (DMA_TCD4_CSR) 16 R/W Undefined 22.3.29/504 4000_909E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD4_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_909E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD4_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_90A0 TCD Source Address (DMA_TCD5_SADDR) 32 R/W Undefined 22.3.17/495 4000_90A4 TCD Signed Source Address Offset (DMA_TCD5_SOFF) 16 R/W Undefined 22.3.18/495 4000_90A6 TCD Transfer Attributes (DMA_TCD5_ATTR) 16 R/W Undefined 22.3.19/496 4000_90A8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD5_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_90A8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD5_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_90A8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD5_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_90AC TCD Last Source Address Adjustment (DMA_TCD5_SLAST) 32 R/W Undefined 22.3.23/500 4000_90B0 TCD Destination Address (DMA_TCD5_DADDR) 32 R/W Undefined 22.3.24/500 4000_90B4 TCD Signed Destination Address Offset (DMA_TCD5_DOFF) 16 R/W Undefined 22.3.25/501 4000_90B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD5_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_90B6 DMA_TCD5_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_90B8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD5_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_90BC TCD Control and Status (DMA_TCD5_CSR) 16 R/W Undefined 22.3.29/504 4000_90BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD5_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_90BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD5_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_90C0 TCD Source Address (DMA_TCD6_SADDR) 32 R/W Undefined 22.3.17/495 4000_90C4 TCD Signed Source Address Offset (DMA_TCD6_SOFF) 16 R/W Undefined 22.3.18/495 4000_90C6 TCD Transfer Attributes (DMA_TCD6_ATTR) 16 R/W Undefined 22.3.19/496 4000_90C8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD6_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_90C8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD6_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_90C8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD6_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 464 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 465

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_90CC TCD Last Source Address Adjustment (DMA_TCD6_SLAST) 32 R/W Undefined 22.3.23/500 4000_90D0 TCD Destination Address (DMA_TCD6_DADDR) 32 R/W Undefined 22.3.24/500 4000_90D4 TCD Signed Destination Address Offset (DMA_TCD6_DOFF) 16 R/W Undefined 22.3.25/501 4000_90D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD6_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_90D6 DMA_TCD6_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_90D8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD6_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_90DC TCD Control and Status (DMA_TCD6_CSR) 16 R/W Undefined 22.3.29/504 4000_90DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD6_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_90DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD6_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_90E0 TCD Source Address (DMA_TCD7_SADDR) 32 R/W Undefined 22.3.17/495 4000_90E4 TCD Signed Source Address Offset (DMA_TCD7_SOFF) 16 R/W Undefined 22.3.18/495 4000_90E6 TCD Transfer Attributes (DMA_TCD7_ATTR) 16 R/W Undefined 22.3.19/496 4000_90E8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD7_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_90E8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD7_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_90E8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD7_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_90EC TCD Last Source Address Adjustment (DMA_TCD7_SLAST) 32 R/W Undefined 22.3.23/500 4000_90F0 TCD Destination Address (DMA_TCD7_DADDR) 32 R/W Undefined 22.3.24/500 4000_90F4 TCD Signed Destination Address Offset (DMA_TCD7_DOFF) 16 R/W Undefined 22.3.25/501 4000_90F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD7_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_90F6 DMA_TCD7_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_90F8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD7_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_90FC TCD Control and Status (DMA_TCD7_CSR) 16 R/W Undefined 22.3.29/504 4000_90FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD7_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_90FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD7_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_9100 TCD Source Address (DMA_TCD8_SADDR) 32 R/W Undefined 22.3.17/495 4000_9104 TCD Signed Source Address Offset (DMA_TCD8_SOFF) 16 R/W Undefined 22.3.18/495 Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 465 General Business Information

Page 466

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_9106 TCD Transfer Attributes (DMA_TCD8_ATTR) 16 R/W Undefined 22.3.19/496 4000_9108 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD8_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_9108 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD8_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_9108 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD8_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_910C TCD Last Source Address Adjustment (DMA_TCD8_SLAST) 32 R/W Undefined 22.3.23/500 4000_9110 TCD Destination Address (DMA_TCD8_DADDR) 32 R/W Undefined 22.3.24/500 4000_9114 TCD Signed Destination Address Offset (DMA_TCD8_DOFF) 16 R/W Undefined 22.3.25/501 4000_9116 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD8_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_9116 DMA_TCD8_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_9118 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD8_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_911C TCD Control and Status (DMA_TCD8_CSR) 16 R/W Undefined 22.3.29/504 4000_911E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD8_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_911E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD8_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_9120 TCD Source Address (DMA_TCD9_SADDR) 32 R/W Undefined 22.3.17/495 4000_9124 TCD Signed Source Address Offset (DMA_TCD9_SOFF) 16 R/W Undefined 22.3.18/495 4000_9126 TCD Transfer Attributes (DMA_TCD9_ATTR) 16 R/W Undefined 22.3.19/496 4000_9128 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD9_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_9128 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD9_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_9128 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD9_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_912C TCD Last Source Address Adjustment (DMA_TCD9_SLAST) 32 R/W Undefined 22.3.23/500 4000_9130 TCD Destination Address (DMA_TCD9_DADDR) 32 R/W Undefined 22.3.24/500 4000_9134 TCD Signed Destination Address Offset (DMA_TCD9_DOFF) 16 R/W Undefined 22.3.25/501 4000_9136 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD9_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_9136 DMA_TCD9_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_9138 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD9_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_913C TCD Control and Status (DMA_TCD9_CSR) 16 R/W Undefined 22.3.29/504 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 466 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 467

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_913E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD9_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_913E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD9_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_9140 TCD Source Address (DMA_TCD10_SADDR) 32 R/W Undefined 22.3.17/495 4000_9144 TCD Signed Source Address Offset (DMA_TCD10_SOFF) 16 R/W Undefined 22.3.18/495 4000_9146 TCD Transfer Attributes (DMA_TCD10_ATTR) 16 R/W Undefined 22.3.19/496 4000_9148 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD10_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_9148 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD10_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_9148 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD10_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_914C TCD Last Source Address Adjustment (DMA_TCD10_SLAST) 32 R/W Undefined 22.3.23/500 4000_9150 TCD Destination Address (DMA_TCD10_DADDR) 32 R/W Undefined 22.3.24/500 4000_9154 TCD Signed Destination Address Offset (DMA_TCD10_DOFF) 16 R/W Undefined 22.3.25/501 4000_9156 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD10_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_9156 DMA_TCD10_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_9158 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD10_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_915C TCD Control and Status (DMA_TCD10_CSR) 16 R/W Undefined 22.3.29/504 4000_915E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD10_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_915E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD10_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_9160 TCD Source Address (DMA_TCD11_SADDR) 32 R/W Undefined 22.3.17/495 4000_9164 TCD Signed Source Address Offset (DMA_TCD11_SOFF) 16 R/W Undefined 22.3.18/495 4000_9166 TCD Transfer Attributes (DMA_TCD11_ATTR) 16 R/W Undefined 22.3.19/496 4000_9168 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD11_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_9168 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD11_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_9168 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD11_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_916C TCD Last Source Address Adjustment (DMA_TCD11_SLAST) 32 R/W Undefined 22.3.23/500 4000_9170 TCD Destination Address (DMA_TCD11_DADDR) 32 R/W Undefined 22.3.24/500 Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 467 General Business Information

Page 468

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_9174 TCD Signed Destination Address Offset (DMA_TCD11_DOFF) 16 R/W Undefined 22.3.25/501 4000_9176 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD11_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_9176 DMA_TCD11_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_9178 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD11_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_917C TCD Control and Status (DMA_TCD11_CSR) 16 R/W Undefined 22.3.29/504 4000_917E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD11_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_917E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD11_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_9180 TCD Source Address (DMA_TCD12_SADDR) 32 R/W Undefined 22.3.17/495 4000_9184 TCD Signed Source Address Offset (DMA_TCD12_SOFF) 16 R/W Undefined 22.3.18/495 4000_9186 TCD Transfer Attributes (DMA_TCD12_ATTR) 16 R/W Undefined 22.3.19/496 4000_9188 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD12_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_9188 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD12_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_9188 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD12_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_918C TCD Last Source Address Adjustment (DMA_TCD12_SLAST) 32 R/W Undefined 22.3.23/500 4000_9190 TCD Destination Address (DMA_TCD12_DADDR) 32 R/W Undefined 22.3.24/500 4000_9194 TCD Signed Destination Address Offset (DMA_TCD12_DOFF) 16 R/W Undefined 22.3.25/501 4000_9196 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD12_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_9196 DMA_TCD12_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_9198 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD12_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_919C TCD Control and Status (DMA_TCD12_CSR) 16 R/W Undefined 22.3.29/504 4000_919E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD12_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_919E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD12_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_91A0 TCD Source Address (DMA_TCD13_SADDR) 32 R/W Undefined 22.3.17/495 4000_91A4 TCD Signed Source Address Offset (DMA_TCD13_SOFF) 16 R/W Undefined 22.3.18/495 4000_91A6 TCD Transfer Attributes (DMA_TCD13_ATTR) 16 R/W Undefined 22.3.19/496 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 468 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 469

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_91A8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD13_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_91A8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD13_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_91A8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD13_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_91AC TCD Last Source Address Adjustment (DMA_TCD13_SLAST) 32 R/W Undefined 22.3.23/500 4000_91B0 TCD Destination Address (DMA_TCD13_DADDR) 32 R/W Undefined 22.3.24/500 4000_91B4 TCD Signed Destination Address Offset (DMA_TCD13_DOFF) 16 R/W Undefined 22.3.25/501 4000_91B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD13_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_91B6 DMA_TCD13_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_91B8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD13_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_91BC TCD Control and Status (DMA_TCD13_CSR) 16 R/W Undefined 22.3.29/504 4000_91BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD13_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_91BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD13_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_91C0 TCD Source Address (DMA_TCD14_SADDR) 32 R/W Undefined 22.3.17/495 4000_91C4 TCD Signed Source Address Offset (DMA_TCD14_SOFF) 16 R/W Undefined 22.3.18/495 4000_91C6 TCD Transfer Attributes (DMA_TCD14_ATTR) 16 R/W Undefined 22.3.19/496 4000_91C8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD14_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_91C8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD14_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_91C8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD14_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_91CC TCD Last Source Address Adjustment (DMA_TCD14_SLAST) 32 R/W Undefined 22.3.23/500 4000_91D0 TCD Destination Address (DMA_TCD14_DADDR) 32 R/W Undefined 22.3.24/500 4000_91D4 TCD Signed Destination Address Offset (DMA_TCD14_DOFF) 16 R/W Undefined 22.3.25/501 4000_91D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD14_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_91D6 DMA_TCD14_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_91D8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD14_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_91DC TCD Control and Status (DMA_TCD14_CSR) 16 R/W Undefined 22.3.29/504 Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 469 General Business Information

Page 470

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_91DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD14_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_91DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD14_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 4000_91E0 TCD Source Address (DMA_TCD15_SADDR) 32 R/W Undefined 22.3.17/495 4000_91E4 TCD Signed Source Address Offset (DMA_TCD15_SOFF) 16 R/W Undefined 22.3.18/495 4000_91E6 TCD Transfer Attributes (DMA_TCD15_ATTR) 16 R/W Undefined 22.3.19/496 4000_91E8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD15_NBYTES_MLNO) 32 R/W Undefined 22.3.20/497 4000_91E8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD15_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.21/497 4000_91E8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD15_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.22/498 4000_91EC TCD Last Source Address Adjustment (DMA_TCD15_SLAST) 32 R/W Undefined 22.3.23/500 4000_91F0 TCD Destination Address (DMA_TCD15_DADDR) 32 R/W Undefined 22.3.24/500 4000_91F4 TCD Signed Destination Address Offset (DMA_TCD15_DOFF) 16 R/W Undefined 22.3.25/501 4000_91F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD15_CITER_ELINKYES) 16 R/W Undefined 22.3.26/501 4000_91F6 DMA_TCD15_CITER_ELINKNO 16 R/W Undefined 22.3.27/502 4000_91F8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD15_DLASTSGA) 32 R/W Undefined 22.3.28/503 4000_91FC TCD Control and Status (DMA_TCD15_CSR) 16 R/W Undefined 22.3.29/504 4000_91FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD15_BITER_ELINKYES) 16 R/W Undefined 22.3.30/506 4000_91FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD15_BITER_ELINKNO) 16 R/W Undefined 22.3.31/507 22.3.1 Control Register (DMA_CR) The CR defines the basic operating configuration of the DMA. Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The channel priority registers assign the priorities; see the DCHPRIn registers. For round-robin arbitration, the channel priorities are ignored and channels are cycled through (from high to low channel number) without regard to priority. Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 470 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 471

NOTE For proper operation, writes to the CR register must be performed only when the DMA channels are inactive; that is, when TCDn_CSR[ACTIVE] bits are cleared. Address: 4000_8000h base + 0h offset = 4000_8000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 CX ECX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 EMLM CLM HALT HOE 0 ERCA EDBG 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CR field descriptions Field Description 31–18 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 17 CX Cancel Transfer 0 Normal operation 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. 16 ECX Error Cancel Transfer 0 Normal operation 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt. 15–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7 EMLM Enable Minor Loop Mapping 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. 6 CLM Continuous Link Mode Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 471 General Business Information

Page 472

DMA_CR field descriptions (continued) Field Description 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. 5 HALT Halt DMA Operations 0 Normal operation 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. 4 HOE Halt On Error 0 Normal operation 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 ERCA Enable Round Robin Channel Arbitration 0 Fixed priority arbitration is used for channel selection . 1 Round robin arbitration is used for channel selection . 1 EDBG Enable Debug 0 When in debug mode, the DMA continues to operate. 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 22.3.2 Error Status Register (DMA_ES) The ES provides information concerning the last recorded channel error. Channel errors can be caused by: • A configuration error, that is: • An illegal setting in the transfer-control descriptor, or • An illegal priority register setting in fixed-arbitration • An error termination to a bus master read or write cycle See the Error Reporting and Handling section for more details. Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 472 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 473

Address: 4000_8000h base + 4h offset = 4000_8004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R VLD 0 ECX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CPE 0 ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ES field descriptions Field Description 31 VLD Logical OR of all ERR status bits 0 No ERR bits are set 1 At least one ERR bit is set indicating a valid error exists that has not been cleared 30–17 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 16 ECX Transfer Cancelled 0 No cancelled transfers 1 The last recorded entry was a cancelled transfer by the error cancel transfer input 15 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 14 CPE Channel Priority Error 0 No channel priority error 1 The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. 13–12 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 11–8 ERRCHN Error Channel Number or Cancelled Channel Number The channel number of the last recorded error (excluding CPE errors) or last recorded error cancelled transfer . 7 SAE Source Address Error 0 No source address configuration error. 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. 6 SOE Source Offset Error 0 No source offset configuration error 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. 5 DAE Destination Address Error Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 473 General Business Information

Page 474

DMA_ES field descriptions (continued) Field Description 0 No destination address configuration error 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. 4 DOE Destination Offset Error 0 No destination offset configuration error 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. 3 NCE NBYTES/CITER Configuration Error 0 No NBYTES/CITER configuration error 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. • TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or • TCDn_CITER[CITER] is equal to zero, or • TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] 2 SGE Scatter/Gather Configuration Error 0 No scatter/gather configuration error 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. 1 SBE Source Bus Error 0 No source bus error 1 The last recorded error was a bus error on a source read 0 DBE Destination Bus Error 0 No destination bus error 1 The last recorded error was a bus error on a destination write 22.3.3 Enable Request Register (DMA_ ERQ ) The ERQ register provide s a bit map for the 16 implemented channels to enable the request signal for each channel. The state of any given channel enable is directly affected by writes to this register; it is also affected by writes to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable for a single channel can easily be modified without needing to perform a read-modify-write sequence to the ERQ . DMA request input signals and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request. Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 474 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 475

Address: 4000_8000h base + Ch offset = 4000_800Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ERQ15 ERQ14 ERQ13 ERQ12 ERQ11 ERQ10 ERQ9 ERQ8 ERQ7 ERQ6 ERQ5 ERQ4 ERQ3 ERQ2 ERQ1 ERQ0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ ERQ field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15 ERQ15 Enable DMA Request 15 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 14 ERQ14 Enable DMA Request 14 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 13 ERQ13 Enable DMA Request 13 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 12 ERQ12 Enable DMA Request 12 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 11 ERQ11 Enable DMA Request 11 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 10 ERQ10 Enable DMA Request 10 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 9 ERQ9 Enable DMA Request 9 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 8 ERQ8 Enable DMA Request 8 Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 475 General Business Information

Page 476

DMA_ ERQ field descriptions (continued) Field Description 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 7 ERQ7 Enable DMA Request 7 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 6 ERQ6 Enable DMA Request 6 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 5 ERQ5 Enable DMA Request 5 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 4 ERQ4 Enable DMA Request 4 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 3 ERQ3 Enable DMA Request 3 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 2 ERQ2 Enable DMA Request 2 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 1 ERQ1 Enable DMA Request 1 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 0 ERQ0 Enable DMA Request 0 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 22.3.4 Enable Error Interrupt Register (DMA_ EEI ) The EEI register provides a bit map for the 16 channels to enable the error interrupt signal for each channel. The state of any given channel’s error interrupt enable is directly affected by writes to this register; it is also affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the EEI register . The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 476 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 477

Address: 4000_8000h base + 14h offset = 4000_8014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI9 EEI8 EEI7 EEI6 EEI5 EEI4 EEI3 EEI2 EEI1 EEI0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ EEI field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15 EEI15 Enable Error Interrupt 15 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 14 EEI14 Enable Error Interrupt 14 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 13 EEI13 Enable Error Interrupt 13 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 12 EEI12 Enable Error Interrupt 12 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 11 EEI11 Enable Error Interrupt 11 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 10 EEI10 Enable Error Interrupt 10 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 9 EEI9 Enable Error Interrupt 9 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 8 EEI8 Enable Error Interrupt 8 Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 477 General Business Information

Page 478

DMA_ EEI field descriptions (continued) Field Description 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 7 EEI7 Enable Error Interrupt 7 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 6 EEI6 Enable Error Interrupt 6 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 5 EEI5 Enable Error Interrupt 5 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 4 EEI4 Enable Error Interrupt 4 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 3 EEI3 Enable Error Interrupt 3 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 2 EEI2 Enable Error Interrupt 2 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 1 EEI1 Enable Error Interrupt 1 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 0 EEI0 Enable Error Interrupt 0 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 478 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 479

22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI) The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI to disable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 18h offset = 4000_8018h Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEE 0 CEEI Reset 0 0 0 0 0 0 0 0 DMA_CEEI field descriptions Field Description 7 NOP No Op enable 0 Normal operation 1 No operation, ignore the other bits in this register 6 CAEE Clear All Enable Error Interrupts 0 Clear only the EEI bit specified in the CEEI field 1 Clear all bits in EEI 5–4 Reserved This field is reserved. 3–0 CEEI Clear Enable Error Interrupt Clears the corresponding bit in EEI Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 479 General Business Information

Page 480

22.3.6 Set Enable Error Interrupt Register (DMA_SEEI) The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set function, forcing the entire EEI contents to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 19h offset = 4000_8019h Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAEE 0 SEEI Reset 0 0 0 0 0 0 0 0 DMA_SEEI field descriptions Field Description 7 NOP No Op enable 0 Normal operation 1 No operation, ignore the other bits in this register 6 SAEE Sets All Enable Error Interrupts 0 Set only the EEI bit specified in the SEEI field. 1 Sets all bits in EEI 5–4 Reserved This field is reserved. 3–0 SEEI Set Enable Error Interrupt Sets the corresponding bit in EEI Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 480 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 481

22.3.7 Clear Enable Request Register (DMA_CERQ) The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a global clear function, forcing the entire contents of the ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Ah offset = 4000_801Ah Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAER 0 CERQ Reset 0 0 0 0 0 0 0 0 DMA_CERQ field descriptions Field Description 7 NOP No Op enable 0 Normal operation 1 No operation, ignore the other bits in this register 6 CAER Clear All Enable Requests 0 Clear only the ERQ bit specified in the CERQ field 1 Clear all bits in ERQ 5–4 Reserved This field is reserved. 3–0 CERQ Clear Enable Request Clears the corresponding bit in ERQ Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 481 General Business Information

Page 482

22.3.8 Set Enable Request Register (DMA_SERQ) The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire contents of ERQ to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Bh offset = 4000_801Bh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAER 0 SERQ Reset 0 0 0 0 0 0 0 0 DMA_SERQ field descriptions Field Description 7 NOP No Op enable 0 Normal operation 1 No operation, ignore the other bits in this register 6 SAER Set All Enable Requests 0 Set only the ERQ bit specified in the SERQ field 1 Set all bits in ERQ 5–4 Reserved This field is reserved. 3–0 SERQ Set enable request Sets the corresponding bit in ERQ Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 482 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 483

22.3.9 Clear DONE Status Bit Register (DMA_CDNE) The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a global clear function, forcing all DONE bits to be cleared. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Ch offset = 4000_801Ch Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CADN 0 CDNE Reset 0 0 0 0 0 0 0 0 DMA_CDNE field descriptions Field Description 7 NOP No Op enable 0 Normal operation 1 No operation, ignore the other bits in this register 6 CADN Clears All DONE Bits 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 1 Clears all bits in TCDn_CSR[DONE] 5–4 Reserved This field is reserved. 3–0 CDNE Clear DONE Bit Clears the corresponding bit in TCDn_CSR[DONE] Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 483 General Business Information

Page 484

22.3.10 Set START Bit Register (DMA_SSRT) The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Dh offset = 4000_801Dh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAST 0 SSRT Reset 0 0 0 0 0 0 0 0 DMA_SSRT field descriptions Field Description 7 NOP No Op enable 0 Normal operation 1 No operation, ignore the other bits in this register 6 SAST Set All START Bits (activates all channels) 0 Set only the TCDn_CSR[START] bit specified in the SSRT field 1 Set all bits in TCDn_CSR[START] 5–4 Reserved This field is reserved. 3–0 SSRT Set START Bit Sets the corresponding bit in TCDn_CSR[START] Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 484 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 485

22.3.11 Clear Error Register (DMA_CERR) The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a global clear function, forcing the ERR contents to be cleared, clearing all channel error indicators. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Eh offset = 4000_801Eh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEI 0 CERR Reset 0 0 0 0 0 0 0 0 DMA_CERR field descriptions Field Description 7 NOP No Op enable 0 Normal operation 1 No operation, ignore the other bits in this register 6 CAEI Clear All Error Indicators 0 Clear only the ERR bit specified in the CERR field 1 Clear all bits in ERR 5–4 Reserved This field is reserved. 3–0 CERR Clear Error Indicator Clears the corresponding bit in ERR Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 485 General Business Information

Page 486

22.3.12 Clear Interrupt Request Register (DMA_CINT) The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a global clear function, forcing the entire contents of the INT to be cleared, disabling all DMA interrupt requests. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Fh offset = 4000_801Fh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAIR 0 CINT Reset 0 0 0 0 0 0 0 0 DMA_CINT field descriptions Field Description 7 NOP No Op enable 0 Normal operation 1 No operation, ignore the other bits in this register 6 CAIR Clear All Interrupt Requests 0 Clear only the INT bit specified in the CINT field 1 Clear all bits in INT 5–4 Reserved This field is reserved. 3–0 CINT Clear Interrupt Request Clears the corresponding bit in INT Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 486 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 487

22.3.13 Interrupt Request Register (DMA_ INT ) The INT register provides a bit map for the 16 channels signaling the presence of an interrupt request for each channel. Depending on the appropriate bit setting in the transfer-control descriptors, the eDMA engine generates an interrupt on data transfer completion. The outputs of this register are directly routed to the interrupt controller (INTC). During the interrupt-service routine associated with any given channel, it is the software’s responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the CINT register in the interrupt service routine is used for this purpose. The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit position clears the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding channel’s current interrupt status. The CINT register is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read-modify-write sequence to the INT register. Address: 4000_8000h base + 24h offset = 4000_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ INT field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 487 General Business Information

Page 488

DMA_ INT field descriptions (continued) Field Description 15 INT15 Interrupt Request 15 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 14 INT14 Interrupt Request 14 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 13 INT13 Interrupt Request 13 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 12 INT12 Interrupt Request 12 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 11 INT11 Interrupt Request 11 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 10 INT10 Interrupt Request 10 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 9 INT9 Interrupt Request 9 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 8 INT8 Interrupt Request 8 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 7 INT7 Interrupt Request 7 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 6 INT6 Interrupt Request 6 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 5 INT5 Interrupt Request 5 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 4 INT4 Interrupt Request 4 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 488 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 489

DMA_ INT field descriptions (continued) Field Description 3 INT3 Interrupt Request 3 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 2 INT2 Interrupt Request 2 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 1 INT1 Interrupt Request 1 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 0 INT0 Interrupt Request 0 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active 22.3.14 Error Register (DMA_ ERR ) The ERR provides a bit map for the 16 channels, signaling the presence of an error for each channel. The eDMA engine signals the occurrence of an error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the EEI, and then routed to the interrupt controller. During the execution of the interrupt-service routine associated with any DMA errors, it is software’s responsibility to clear the appropriate bit, negating the error-interrupt request. Typically, a write to the CERR in the interrupt-service routine is used for this purpose. The normal DMA channel completion indicators (setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request) are not affected when an error is detected. The contents of this register can also be polled because a non-zero value indicates the presence of a channel error regardless of the state of the EEI. The state of any given channel’s error indicators is affected by writes to this register; it is also affected by writes to the CERR. On writes to the ERR, a one in any bit position clears the corresponding channel’s error status. A zero in any bit position has no affect on the corresponding channel’s current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 489 General Business Information

Page 490

Address: 4000_8000h base + 2Ch offset = 4000_802Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ERR15 ERR14 ERR13 ERR12 ERR11 ERR10 ERR9 ERR8 ERR7 ERR6 ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ ERR field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15 ERR15 Error In Channel 15 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 14 ERR14 Error In Channel 14 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 13 ERR13 Error In Channel 13 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 12 ERR12 Error In Channel 12 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 11 ERR11 Error In Channel 11 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 10 ERR10 Error In Channel 10 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 490 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 491

DMA_ ERR field descriptions (continued) Field Description 9 ERR9 Error In Channel 9 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 8 ERR8 Error In Channel 8 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 7 ERR7 Error In Channel 7 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 6 ERR6 Error In Channel 6 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 5 ERR5 Error In Channel 5 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 4 ERR4 Error In Channel 4 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 3 ERR3 Error In Channel 3 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 2 ERR2 Error In Channel 2 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 1 ERR1 Error In Channel 1 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 0 ERR0 Error In Channel 0 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 491 General Business Information

Page 492

22.3.15 Hardware Request Status Register (DMA_ HRS ) The HRS provide s a bit map for the DMA channels, signaling the presence of a hardware request for each channel. The hardware request status bits reflect the current state of the register and qualified (via the ERQ fields) DMA request signals as seen by the DMA’s arbitration logic. This view into the hardware request signals may be used for debug purposes. NOTE These bits reflect the state of the request as seen by the arbitration logic. Therefore, this status is affected by the ERQ bits. Address: 4000_8000h base + 34h offset = 4000_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R HRS15 HRS14 HRS13 HRS12 HRS11 HRS10 HRS9 HRS8 HRS7 HRS6 HRS5 HRS4 HRS3 HRS2 HRS1 HRS0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ HRS field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15 HRS15 Hardware Request Status Channel 15 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 14 HRS14 Hardware Request Status Channel 14 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 13 HRS13 Hardware Request Status Channel 13 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 492 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 493

DMA_ HRS field descriptions (continued) Field Description 12 HRS12 Hardware Request Status Channel 12 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 11 HRS11 Hardware Request Status Channel 11 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 10 HRS10 Hardware Request Status Channel 10 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 9 HRS9 Hardware Request Status Channel 9 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 8 HRS8 Hardware Request Status Channel 8 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 7 HRS7 Hardware Request Status Channel 7 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 6 HRS6 Hardware Request Status Channel 6 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 5 HRS5 Hardware Request Status Channel 5 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 4 HRS4 Hardware Request Status Channel 4 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 3 HRS3 Hardware Request Status Channel 3 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 2 HRS2 Hardware Request Status Channel 2 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 1 HRS1 Hardware Request Status Channel 1 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 493 General Business Information

Page 494

DMA_ HRS field descriptions (continued) Field Description 0 HRS0 Hardware Request Status Channel 0 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 22.3.16 Channel n Priority Register (DMA_DCHPRIn) When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel . The channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next priority, then 2, 3, etc. Software must program the channel priorities with unique values; otherwise, a configuration error is reported. The range of the priority value is limited to the values of 0 through 15 . Address: 4000_8000h base + 100h offset + (1d × i), where i=0d to 15d Bit 7 6 5 4 3 2 1 0 Read ECP DPA 0 CHPRI Write Reset 0 0 0 0 * * * *

Notes: CHPRI field: See bit field description • DMA_DCHPRIn field descriptions Field Description 7 ECP Enable Channel Preemption 0 Channel n cannot be suspended by a higher priority channel’s service request 1 Channel n can be temporarily suspended by the service request of a higher priority channel 6 DPA Disable Preempt Ability 0 Channel n can suspend a lower priority channel 1 Channel n cannot suspend any channel, regardless of channel priority 5–4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3–0 CHPRI Channel n Arbitration Priority Channel priority when fixed-priority arbitration is enabled NOTE: Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111. Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 494 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 495

22.3.17 TCD Source Address (DMA_TCDn_SADDR) Address: 4000_8000h base + 1000h offset + (32d × i), where i=0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SADDR W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_SADDR field descriptions Field Description 31–0 SADDR Source Address Memory address pointing to the source data. 22.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF) Address: 4000_8000h base + 1004h offset + (32d × i), where i=0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read SOFF Write Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Notes: x = Undefined at reset. • DMA_TCDn_SOFF field descriptions Field Description 15–0 SOFF Source address signed offset Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 495 General Business Information

Page 496

22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR) Address: 4000_8000h base + 1006h offset + (32d × i), where i=0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read SMOD SSIZE DMOD DSIZE Write Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_ATTR field descriptions Field Description 15–11 SMOD Source Address Modulo. 0 Source address modulo feature is disabled ≠0 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed or the original register value. The setting of this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 10–8 SSIZE Source data transfer size The attempted use of a Reserved encoding causes a configuration error. 000 8-bit 001 16-bit 010 32-bit 011 Reserved 100 16-byte 101 32-byte 110 Reserved 111 Reserved 7–3 DMOD Destination Address Modulo See the SMOD definition 2–0 DSIZE Destination Data Transfer Size See the SSIZE definition Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 496 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 497

22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO) TCD word 2's register definition depends on the status of minor loop mapping. If minor loop mapping is disabled (CR[EMLM] = 0), TCD word 2 is defined as follows. If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions for TCD word 2's register definition. Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NBYTES W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_NBYTES_MLNO field descriptions Field Description 31–0 NBYTES Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. (Although, it may be stalled by using the bandwidth control field, or via preemption.) After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer. 22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO) TCD word 2 is defined as follows if: • Minor loop mapping is enabled (CR[EMLM] = 1) and • SMLOE = 0 and DMLOE = 0 If minor loop mapping is enabled and SMLOE or DMLOE is set then refer to the TCD_NBYTES_MLOFFYES register description. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 497 General Business Information

Page 498

Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SMLOE DMLOE NBYTES W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NBYTES W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_NBYTES_MLOFFNO field descriptions Field Description 31 SMLOE Source Minor Loop Offset Enable Selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 The minor loop offset is not applied to the SADDR 1 The minor loop offset is applied to the SADDR 30 DMLOE Destination Minor Loop Offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 The minor loop offset is not applied to the DADDR 1 The minor loop offset is applied to the DADDR 29–0 NBYTES Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted; although, it may be stalled by using the bandwidth control field, or via preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. 22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES) TCD word 2 is defined as follows if: • Minor loop mapping is enabled (CR[EMLM] = 1) and • Minor loop offset enabled (SMLOE or DMLOE = 1) Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 498 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 499

If minor loop mapping is enabled and SMLOE and DMLOE are cleared then refer to the TCD_NBYTES_MLOFFNO register description. Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SMLOE DMLOE MLOFF W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MLOFF NBYTES W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_NBYTES_MLOFFYES field descriptions Field Description 31 SMLOE Source Minor Loop Offset Enable Selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 The minor loop offset is not applied to the SADDR 1 The minor loop offset is applied to the SADDR 30 DMLOE Destination Minor Loop Offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 The minor loop offset is not applied to the DADDR 1 The minor loop offset is applied to the DADDR 29–10 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 9–0 NBYTES Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. (Although, it may be stalled by using the bandwidth control field, or via preemption.) After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 499 General Business Information

Page 500

22.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST) Address: 4000_8000h base + 100Ch offset + (32d × i), where i=0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SLAST W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_SLAST field descriptions Field Description 31–0 SLAST Last source Address Adjustment Adjustment value added to the source address at the completion of the major iteration count. This value can be applied to restore the source address to the initial value, or adjust the address to reference the next data structure. 22.3.24 TCD Destination Address (DMA_TCDn_DADDR) Address: 4000_8000h base + 1010h offset + (32d × i), where i=0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DADDR W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Notes: x = Undefined at reset. • DMA_TCDn_DADDR field descriptions Field Description 31–0 DADDR Destination Address Memory address pointing to the destination data. Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 500 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 501

22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF) Address: 4000_8000h base + 1014h offset + (32d × i), where i=0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DOFF Write Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_DOFF field descriptions Field Description 15–0 DOFF Destination Address Signed offset Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. 22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_CITER_ELINKYES) If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows. Address: 4000_8000h base + 1016h offset + (32d × i), where i=0d to 15d Bit 15 14 13 12 11 10 9 8 Read ELINK 0 LINKCH CITER Write Reset x* x* x* x* x* x* x* x* Bit 7 6 5 4 3 2 1 0 Read CITER Write Reset x* x* x* x* x* x* x* x*
Notes: x = Undefined at reset. • DMA_TCDn_CITER_ELINKYES field descriptions Field Description 15 ELINK Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 501 General Business Information

Page 502

DMA_TCDn_CITER_ELINKYES field descriptions (continued) Field Description If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported. 0 The channel-to-channel linking is disabled 1 The channel-to-channel linking is enabled 14–13 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12–9 LINKCH Link Channel Number If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request to the channel defined by these four bits by setting that channel’s TCDn_CSR[START] bit. 8–0 CITER Current Major Iteration Count This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations (e.g., final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the CITER field from the beginning iteration count (BITER) field. NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_CITER_ELINKNO) If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as follows. Address: 4000_8000h base + 1016h offset + (32d × i), where i=0d to 15d Bit 15 14 13 12 11 10 9 8 Read ELINK CITER Write Reset x* x* x* x* x* x* x* x* Bit 7 6 5 4 3 2 1 0 Read CITER Write Reset x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 502 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 503

DMA_TCDn_CITER_ELINKNO field descriptions Field Description 15 ELINK Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported. 0 The channel-to-channel linking is disabled 1 The channel-to-channel linking is enabled 14–0 CITER Current Major Iteration Count This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations (e.g., final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the CITER field from the beginning iteration count (BITER) field. NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 22.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA) Address: 4000_8000h base + 1018h offset + (32d × i), where i=0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DLASTSGA W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_DLASTSGA field descriptions Field Description 31–0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather). If (TCDn_CSR[ESG] = 0) then • Adjustment value added to the destination address at the completion of the major iteration count. This value can apply to restore the destination address to the initial value or adjust the address to reference the next data structure. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 503 General Business Information

Page 504

DMA_TCDn_DLASTSGA field descriptions (continued) Field Description else • This address points to the beginning of a 0-modulo-32-byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, else a configuration error is reported. 22.3.29 TCD Control and Status (DMA_TCDn_CSR) Address: 4000_8000h base + 101Ch offset + (32d × i), where i=0d to 15d Bit 15 14 13 12 11 10 9 8 Read BWC 0 MAJORLINKCH Write Reset x* x* x* x* x* x* x* x* Bit 7 6 5 4 3 2 1 0 Read DONE ACTIVE MAJORELI NK ESG DREQ INTHALF INTMAJOR START Write Reset x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_CSR field descriptions Field Description 15–14 BWC Bandwidth Control Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch. NOTE: If the source and destination sizes are equal, this field is ignored between the first and second transfers and after the last write of each minor loop. This behavior is a side effect of reducing start-up latency. 00 No eDMA engine stalls 01 Reserved 10 eDMA engine stalls for 4 cycles after each r/w 11 eDMA engine stalls for 8 cycles after each r/w 13–12 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 11–8 MAJORLINKCH Link Channel Number If (MAJORELINK = 0) then • No channel-to-channel linking (or chaining) is performed after the major loop counter is exhausted. else Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 504 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 505

DMA_TCDn_CSR field descriptions (continued) Field Description • After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by these six bits by setting that channel’s TCDn_CSR[START] bit. 7 DONE Channel Done This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count reaches zero; The software clears it, or the hardware when the channel is activated. NOTE: This bit must be cleared to write the MAJORELINK or ESG bits. 6 ACTIVE Channel Active This flag signals the channel is currently in execution. It is set when channel service begins, and the eDMA clears it as the minor loop completes or if any error condition is detected. This bit resets to zero. 5 MAJORELINK Enable channel-to-channel linking on major loop complete As the channel completes the major loop, this flag enables the linking to another channel, defined by MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. 0 The channel-to-channel linking is disabled 1 The channel-to-channel linking is enabled 4 ESG Enable Scatter/Gather Processing As the channel completes the major loop, this flag enables scatter/gather processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure loaded as the transfer control descriptor into the local memory. NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. 0 The current channel’s TCD is normal format. 1 The current channel’s TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 3 DREQ Disable Request If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current major iteration count reaches zero. 0 The channel’s ERQ bit is not affected 1 The channel’s ERQ bit is cleared when the major loop is complete 2 INTHALF Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT register when the current major iteration count reaches the halfway point. Specifically, the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt request is provided to support double-buffered (aka ping-pong) schemes or other types of data movement where the processor needs an early indication of the transfer’s progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead. 0 The half-point interrupt is disabled 1 The half-point interrupt is enabled Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 505 General Business Information

Page 506

DMA_TCDn_CSR field descriptions (continued) Field Description 1 INTMAJOR Enable an interrupt when major iteration count completes If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. 0 The end-of-major loop interrupt is disabled 1 The end-of-major loop interrupt is enabled 0 START Channel Start If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution. 0 The channel is not explicitly started 1 The channel is explicitly started via a software initiated service request 22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_BITER_ELINKYES) If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as follows. Address: 4000_8000h base + 101Eh offset + (32d × i), where i=0d to 15d Bit 15 14 13 12 11 10 9 8 Read ELINK 0 LINKCH BITER Write Reset x* x* x* x* x* x* x* x* Bit 7 6 5 4 3 2 1 0 Read BITER Write Reset x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_BITER_ELINKYES field descriptions Field Description 15 ELINK Enables channel-to-channel linking on minor loop complete As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking disables, the BITER value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 506 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 507

DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description 0 The channel-to-channel linking is disabled 1 The channel-to-channel linking is enabled 14–13 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12–9 LINKCH Link Channel Number If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request at the channel defined by these four bits by setting that channel’s TCDn_CSR[START] bit. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. 8–0 BITER Starting Major Iteration Count As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO) If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined as follows. Address: 4000_8000h base + 101Eh offset + (32d × i), where i=0d to 15d Bit 15 14 13 12 11 10 9 8 Read ELINK BITER Write Reset x* x* x* x* x* x* x* x* Bit 7 6 5 4 3 2 1 0 Read BITER Write Reset x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • DMA_TCDn_BITER_ELINKNO field descriptions Field Description 15 ELINK Enables channel-to-channel linking on minor loop complete Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 507 General Business Information

Page 508

DMA_TCDn_BITER_ELINKNO field descriptions (continued) Field Description As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the BITER value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. 0 The channel-to-channel linking is disabled 1 The channel-to-channel linking is enabled 14–0 BITER Starting Major Iteration Count As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 22.4 Functional description 22.4.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 508 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 509

1 eDMA Engine Data Path eDMA 0 Program Model/ 64 Control n-1 To/From Crossbar Switch 2 Channel Arbitration Address Path Read Data Write Data Address Read Data Write Data Write Address Internal Peripheral Bus eDMA Peripheral Request eDMA Done Transfer Control Descriptor (TCD) Figure 22-289. eDMA operation, part 1 This example uses the assertion of the eDMA peripheral request signal to request service for channel n. Channel activation via software and the TCDn_CSR[START] bit follows the same basic flow as peripheral requests. The eDMA request input signal is registered internally and then routed through the eDMA engine: first through the control module, then into the program model and channel arbitration. In the next cycle, the channel arbitration performs, using the fixed-priority or round-robin algorithm. After arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the local memory for TCDn. Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded into the eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to minimize the time needed to fetch the activated channel descriptor and load it into the address path channel x or y registers. The following diagram illustrates the second part of the basic data flow: Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 509 General Business Information

Page 510

1 eDMA Engine Data Path eDMA 0 Program Model/ 64 Control n-1 To/From Crossbar Switch 2 Channel Arbitration Address Path Read Data Write Data Address Read Data Write Data Write Address eDMA Peripheral Request eDMA Done Transfer Control Descriptor (TCD) Internal Peripheral Bus Figure 22-290. eDMA operation, part 2 The modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write. This source read/destination write processing continues until the minor byte count has transferred. After the minor byte count has moved, the final phase of the basic data flow is performed. In this segment, the address path logic performs the required updates to certain fields in the appropriate TCD, e.g., SADDR, DADDR, CITER. If the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 510 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 511

1 eDMA Engine Data Path eDMA 0 Program Model/ 64 Control n-1 To/From Crossbar Switch 2 Channel Arbitration Address Path Read Data Write Data Address Read Data Write Data Write Address eDMA Peripheral Request eDMA Done Transfer Control Descriptor (TCD) Internal Peripheral Bus Figure 22-291. eDMA operation, part 3 22.4.2 Error reporting and handling Channel errors are reported in the ES register and can be caused by: • A configuration error, which is an illegal setting in the transfer-control descriptor or an illegal priority register setting in Fixed-Arbitration mode, or • An error termination to a bus master read or write cycle A configuration error is reported when the starting source or destination address, source or destination offsets, minor loop byte count, or the transfer size represent an inconsistent state. Each of these possible causes are detailed below: • The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. • The minor loop byte count must be a multiple of the source and destination transfer sizes. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 511 General Business Information

Page 512

• All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. • In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal. All channel priority levels must be unique when fixed arbitration mode is enabled. • If a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32- byte boundary. • If minor loop channel linking is enabled upon channel completion, a configuration error is reported when the link is attempted if the TCDn_CITER[E_LINK] bit does not equal the TCDn_BITER[E_LINK] bit. If enabled, all configuration error conditions, except the scatter/gather and minor-loop link errors, report as the channel activates and asserts an error interrupt request. A scatter/ gather configuration error is reported when the scatter/gather operation begins at major loop completion when properly enabled. A minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion. If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate bus error flag set. In this case, the state of the channel's transfer control descriptor is updated by the eDMA engine with the current source address, destination address, and current iteration count at the point of the fault. When a system bus error occurs, the channel terminates after the next transfer. Due to pipeline effect, the next transfer is already in progress when the bus error is received by the eDMA. If a bus error occurs on the last read prior to beginning the write sequence, the write executes using the data captured during the bus error. If a bus error occurs on the last write prior to switching to the next read sequence, the read sequence executes before the channel terminates due to the destination bus error. A transfer may be cancelled by software with the CR[CX] bit. When a cancel transfer request is recognized, the DMA engine stops processing the channel. The current read- write sequence is allowed to finish. If the cancel occurs on the last read-write sequence of a major or minor loop, the cancel request is discarded and the channel retires normally. The error cancel transfer is the same as a cancel transfer except the ES register is updated with the cancelled channel number and ECX is set. The TCD of a cancelled channel contains the source and destination addresses of the last transfer saved in the TCD. If the channel needs to be restarted, you must re-initialize the TCD because the aforementioned fields no longer represent the original parameters. When a transfer is cancelled by the error cancel transfer mechanism, the channel number is loaded into DMA_ES[ERRCHN] and ECX and VLD are set. In addition, an error interrupt may be generated if enabled. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 512 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 513

The occurrence of any error causes the eDMA engine to stop normal processing of the active channel immediately (it goes to its error processing states and the transaction to the system bus still has peipeline effect), and the appropriate channel bit in the eDMA error register is asserted. At the same time, the details of the error condition are loaded into the ES register. The major loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. After the error status has been updated, the eDMA engine continues operating by servicing the next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. 22.4.3 Channel preemption Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit. Channel preemption allows the executing channel’s data transfers to temporarily suspend in favor of starting a higher priority channel. After the preempting channel has completed all its minor loop data transfers, the preempted channel is restored and resumes execution. After the restored channel completes one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting service, the restored channel is suspended and the higher priority channel is serviced. Nested preemption, that is, attempting to preempt a preempting channel, is not supported. After a preempting channel begins execution, it cannot be preempted. Preemption is available only when fixed arbitration is selected. A channel’s ability to preempt another channel can be disabled by setting DCHPRIn[DPA]. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority channel’s data transfer, regardless of the lower priority channel’s ECP setting. This allows for a pool of low priority, large data-moving channels to be defined. These low priority channels can be configured to not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally available to a true, high priority channel. 22.4.4 Performance This section addresses the performance of the eDMA module, focusing on two separate metrics: Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 513 General Business Information

Page 514

• In the traditional data movement context, performance is best expressed as the peak data transfer rates achieved using the eDMA. In most implementations, this transfer rate is limited by the speed of the source and destination address spaces. • In a second context where device-paced movement of single data values to/from peripherals is dominant, a measure of the requests that can be serviced in a fixed time is a more relevant metric. In this environment, the speed of the source and destination address spaces remains important. However, the microarchitecture of the eDMA also factors significantly into the resulting metric. 22.4.4.1 Peak transfer rates The peak transfer rates for several different source and destination transfers are shown in the following tables. These tables assume: • Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase • All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states, when viewed from the system bus data phase • All internal peripheral bus accesses are 32-bits in size This table presents a peak transfer rate comparison. Table 22-292. eDMA peak transfer rates (Mbytes/sec) System Speed, Width Internal SRAM-to- Internal SRAM 32b internal peripheral bus- to-Internal SRAM Internal SRAM-to-32b internal peripheral bus 66.7 MHz, 32b 133.3 66.7 53.3 83.3 MHz, 32b 166.7 83.3 66.7 100.0 MHz, 32b 200.0 100.0 80.0 133.3 MHz, 32b 266.7 133.3 106.7 150.0 MHz, 32b 300.0 150.0 120.0 Internal-SRAM-to-internal-SRAM transfers occur at the core's datapath width. For all transfers involving the internal peripheral bus, 32-bit transfer sizes are used. In all cases, the transfer rate includes the time to read the source plus the time to write the destination. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 514 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 515

22.4.4.2 Peak request rates The second performance metric is a measure of the number of DMA requests that can be serviced in a given amount of time. For this metric, assume that the peripheral request causes the channel to move a single internal peripheral bus-mapped operand to/from internal SRAM. The same timing assumptions used in the previous example apply to this calculation. In particular, this metric also reflects the time required to activate the channel. The eDMA design supports the following hardware service request sequence. Note that the exact timing from Cycle 7 is a function of the response times for the channel's read and write accesses. In the case of an internal peripheral bus read and internal SRAM write, the combined data phase time is 4 cycles. For an SRAM read and internal peripheral bus write, it is 5 cycles. Table 22-293. Hardware service request process Cycle Description With internal peripheral bus read and internal SRAM write With SRAM read and internal peripheral bus write 1 eDMA peripheral request is asserted. 2 The eDMA peripheral request is registered locally in the eDMA module and qualified. TCDn_CSR[START] bit initiated requests start at this point with the registering of the user write to TCDn word 7. 3 Channel arbitration begins. 4 Channel arbitration completes. The transfer control descriptor local memory read is initiated. 5–6 The first two parts of the activated channel's TCD is read from the local memory. The memory width to the eDMA engine is 64 bits, so the entire descriptor can be accessed in four cycles 7 The first system bus read cycle is initiated, as the third part of the channel's TCD is read from the local memory. Depending on the state of the crossbar switch, arbitration at the system bus may insert an additional cycle of delay here. 8–11 8–12 The last part of the TCD is read in. This cycle represents the first data phase for the read, and the address phase for the destination write. 12 13 This cycle represents the data phase of the last destination write. 13 14 The eDMA engine completes the execution of the inner minor loop and prepares to write back the required TCDn fields into the local memory. The TCDn word 7 is read and checked for channel linking or scatter/gather requests. 14 15 The appropriate fields in the first part of the TCDn are written back into the local memory. Table continues on the next page... Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 515 General Business Information

Page 516

Table 22-293. Hardware service request process (continued) Cycle Description With internal peripheral bus read and internal SRAM write With SRAM read and internal peripheral bus write 15 16 The fields in the second part of the TCDn are written back into the local memory. This cycle coincides with the next channel arbitration cycle start. 16 17 The next channel to be activated performs the read of the first part of its TCD from the local memory. This is equivalent to Cycle 4 for the first channel's service request. Assuming zero wait states on the system bus, DMA requests can be processed every 9 cycles. Assuming an average of the access times associated with internal peripheral bus- to-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle x +5. The resulting peak request rate, as a function of the system frequency, is shown in the following table. Table 22-294. eDMA peak request rate (MReq/sec) System frequency (MHz) Request rate with zero wait states Request rate with wait states 66.6 7.4 5.8 83.3 9.2 7.2 100.0 11.1 8.7 133.3 14.8 11.6 150.0 16.6 13.0 A general formula to compute the peak request rate with overlapping requests is: PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: Table 22-295. Peak request formula operands Operand Description PEAKreq Peak request rate freq System frequency entry Channel startup (4 cycles) read_ws Wait states seen during the system bus read data phase write_ws Wait states seen during the system bus write data phase exit Channel shutdown (3 cycles) Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 516 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 517

22.4.4.3 eDMA performance example Consider a system with the following characteristics: • Internal SRAM can be accessed with one wait-state when viewed from the system bus data phase • All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states viewed from the system bus data phase • System operates at 150 MHz For an SRAM to internal peripheral bus transfer, PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec For an internal peripheral bus to SRAM transfer, PEAKreq = 150 MHz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec Assuming an even distribution of the two transfer types, the average peak request rate would be: PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/sec The minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a cold start where no channel is executing and eDMA is idle are: • 11 cycles for a software, that is, a TCDn_CSR[START] bit, request • 12 cycles for a hardware, that is, an eDMA peripheral request signal, request Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from the internal registering of the eDMA peripheral request signals. For the peak request rate calculations above, the arbitration and request registering is absorbed in or overlaps the previous executing channel. Note When channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next channel selection and startup. This allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for next channel selection. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 517 General Business Information

Page 518

22.5 Initialization/application information The following sections discuss initialization of the eDMA and programming considerations. 22.5.1 eDMA initialization To initialize the eDMA:

Write to the CR if a configuration other than the default is desired.
Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired.
Enable error interrupts in the EEI register if so desired.
Write the 32-byte TCD for each channel that may request service.
Enable any hardware service requests via the ERQ register.
Request channel service via either: • Software: setting the TCDn_CSR[START] • Hardware: slave device asserting its eDMA peripheral request signal After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The eDMA engine reads the entire TCD, including the TCD control and status fields, as shown in the following table, for the selected channel into its internal address path module. As the TCD is read, the first transfer is initiated on the internal bus, unless a configuration error is detected. Transfers from the source, as defined by TCDn_SADDR, to the destination, as defined by TCDn_DADDR, continue until the number of bytes specified by TCDn_NBYTES are transferred. When the transfer is complete, the eDMA engine's local TCDn_SADDR, TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing executes, such as interrupts, major loop channel linking, and scatter/gather operations, if enabled. Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 518 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 519

Table 22-296. TCD Control and Status fields TCDn_CSR field name Description START Control bit to start channel explicitly when using a software initiated DMA service (Automatically cleared by hardware) ACTIVE Status bit indicating the channel is currently in execution DONE Status bit indicating major loop completion (cleared by software when using a software initiated DMA service) D_REQ Control bit to disable DMA request at end of major loop completion when using a hardware initiated DMA service BWC Control bits for throttling bandwidth control of a channel E_SG Control bit to enable scatter-gather feature INT_HALF Control bit to enable interrupt when major loop is half complete INT_MAJ Control bit to enable interrupt when major loop completes The following figure shows how each DMA request initiates one minor-loop transfer, or iteration, without CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). DMA request DMA request DMA request Minor loop Minor loop Minor loop Major loop Current major loop iteration count (CITER) 3 2 1 Source or destination memory Figure 22-292. Example of multiple loop iterations The following figure lists the memory array terms and how the TCD settings interrelate. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 519 General Business Information

Page 520

xADDR: (Starting address) xLAST: Number of bytes added to current address after major loop (typically used to loop back) Minor loop (NBYTES in minor loop, often the same value as xSIZE) Minor loop Last minor loop Offset (xOFF): number of bytes added to current address after each transfer (often the same value as xSIZE) Each DMA source (S) and destination (D) has its own: Address (xADDR) Size (xSIZE) Offset (xOFF) Modulo (xMOD) Last Address Adjustment (xLAST) where x = S or D Peripheral queues typically have size and offset equal to NBYTES. xSIZE: (size of one data transfer) Figure 22-293. Memory array terms 22.5.2 Programming errors The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). For all error types other than channel priority error, the channel number causing the error is recorded in the ES register. If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again. If priority levels are not unique, when any channel requests service, a channel priority error is reported. The highest channel priority with an active request is selected, but the lowest numbered channel with that priority is selected by arbitration and executed by the eDMA engine. The hardware service request handshake signals, error interrupts, and error reporting is associated with the selected channel. 22.5.3 Arbitration mode considerations 22.5.3.1 Fixed channel arbitration In this mode, the channel service request from the highest priority channel is selected to execute. Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 520 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 521

22.5.3.2 Round-robin channel arbitration Channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels. 22.5.4 Performing DMA transfers (examples) 22.5.4.1 Single request To perform a simple transfer of n bytes of data with one activation, set the major loop to one (TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide memory port located at 0x1000. The destination memory has a 32-bit port located at 0x2000. The address offsets are programmed in increments to match the transfer size: one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values. TCDn_CITER = TCDn_BITER = 1 TCDn_NBYTES = 16 TCDn_SADDR = 0x1000 TCDn_SOFF = 1 TCDn_ATTR[SSIZE] = 0 TCDn_SLAST = -16 TCDn_DADDR = 0x2000 TCDn_DOFF = 4 TCDn_ATTR[DSIZE] = 2 TCDn_DLAST_SGA= –16 TCDn_CSR[INT_MAJ] = 1 TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized) All other TCDn fields = 0 This generates the following event sequence:

User write to the TCDn_CSR[START] bit requests channel service.
The channel is selected by arbitration for servicing.
eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 521 General Business Information

Page 522

eDMA engine reads: channel TCD data from local memory to internal register file.
The source-to-destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. Write 32-bits to location 0x2000 → first iteration of the minor loop. c. Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d. Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. f. Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C → last iteration of the minor loop → major loop complete.
The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 1 (TCDn_BITER).
The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1.
The channel retires and the eDMA goes idle or services the next channel. 22.5.4.2 Multiple requests The following example transfers 32 bytes via two hardware requests, but is otherwise the same as the previous example. The only fields that change are the major loop iteration count and the final address offsets. The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel's hardware requests are enabled in the ERQ register, the slave device initiates channel service requests. TCDn_CITER = TCDn_BITER = 2 TCDn_SLAST = –32 TCDn_DLAST_SGA = –32 This would generate the following sequence of events:
First hardware, that is, eDMA peripheral, request for channel service. Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 522 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 523

The channel is selected by arbitration for servicing.
eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1.
eDMA engine reads: channel TCDn data from local memory to internal register file.
The source to destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. Write 32-bits to location 0x2000 → first iteration of the minor loop. c. Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d. Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. f. Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C → last iteration of the minor loop.
eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010, TCDn_CITER = 1.
eDMA engine writes: TCDn_CSR[ACTIVE] = 0.
The channel retires → one iteration of the major loop. The eDMA goes idle or services the next channel.
Second hardware, that is, eDMA peripheral, requests channel service.
The channel is selected by arbitration for servicing.
eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1.
eDMA engine reads: channel TCD data from local memory to internal register file.
The source to destination transfers are executed as follows: a. Read byte from location 0x1010, read byte from location 0x1011, read byte from 0x1012, read byte from 0x1013. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 523 General Business Information

Page 524

b. Write 32-bits to location 0x2010 → first iteration of the minor loop. c. Read byte from location 0x1014, read byte from location 0x1015, read byte from 0x1016, read byte from 0x1017. d. Write 32-bits to location 0x2014 → second iteration of the minor loop. e. Read byte from location 0x1018, read byte from location 0x1019, read byte from 0x101A, read byte from 0x101B. f. Write 32-bits to location 0x2018 → third iteration of the minor loop. g. Read byte from location 0x101C, read byte from location 0x101D, read byte from 0x101E, read byte from 0x101F. h. Write 32-bits to location 0x201C → last iteration of the minor loop → major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). 15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 16. The channel retires → major loop complete. The eDMA goes idle or services the next channel. 22.5.4.3 Using the modulo feature The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and destination in the TCD, and it specifies which lower address bits increment from their original value after the address+offset calculation. All upper address bits remain the same as in the original value. A setting of 0 for this field disables the modulo feature. The following table shows how the transfer addresses are specified based on the setting of the MOD field. Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits (0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the offset is set to 4 bytes and the MOD field is set to 4, allowing for a 24 byte (16-byte) size queue. Table 22-297. Modulo example Transfer Number Address 1 0x12345670 Table continues on the next page... Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 524 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 525

Table 22-297. Modulo example (continued) Transfer Number Address 2 0x12345674 3 0x12345678 4 0x1234567C 5 0x12345670 6 0x12345674 22.5.5 Monitoring transfer descriptor status 22.5.5.1 Testing for minor loop completion There are two methods to test for minor loop completion when using software initiated service requests. The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is to test the TCDn_CSR[START] bit and the TCDn_CSR[ACTIVE] bit. The minor-loop- complete condition is indicated by both bits reading zero after the TCDn_CSR[START] was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active status may be missed if the channel execution is short in duration. The TCD status bits execute the following sequence for a software activated channel: Stage TCDn_CSR bits State START ACTIVE DONE 1 1 0 0 Channel service request via software 2 0 1 0 Channel is executing 3a 0 0 0 Channel has completed the minor loop and is idle 3b 0 0 1 Channel has completed the major loop and is idle The best method to test for minor-loop completion when using hardware, that is, peripheral, initiated service requests is to read the TCDn_CITER field and test for a change. The hardware request and acknowledge handshake signals are not visible in the programmer's model. The TCD status bits execute the following sequence for a hardware-activated channel: Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 525 General Business Information

Page 526

Stage TCDn_CSR bits State START ACTIVE DONE 1 0 0 0 Channel service request via hardware (peripheral request asserted) 2 0 1 0 Channel is executing 3a 0 0 0 Channel has completed the minor loop and is idle 3b 0 0 1 Channel has completed the major loop and is idle For both activation types, the major-loop-complete status is explicitly indicated via the TCDn_CSR[DONE] bit. The TCDn_CSR[START] bit is cleared automatically when the channel begins execution regardless of how the channel activates. 22.5.5.2 Reading the transfer descriptors of active channels The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES values if read while a channel executes. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and DADDR, and NBYTES, which decrement to zero as the transfer progresses, can give an indication of the progress of the transfer. All other values are read back from the TCD local memory. 22.5.5.3 Checking channel preemption status Preemption is available only when fixed arbitration is selected as the channel arbitration mode. A preemptive situation is one in which a preempt-enabled channel runs and a higher priority request becomes active. When the eDMA engine is not operating in fixed channel arbitration mode, the determination of the actively running relative priority outstanding requests become undefined. Channel priorities are treated as equal, that is, constantly rotating, when Round-Robin Arbitration mode is selected. The TCDn_CSR[ACTIVE] bit for the preempted channel remains asserted throughout the preemption. The preempted channel is temporarily suspended while the preempting channel executes one major loop iteration. If two TCDn_CSR[ACTIVE] bits are set simultaneously in the global TCD map, a higher priority channel is actively preempting a lower priority channel. Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 526 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 527

22.5.6 Channel Linking Channel linking (or chaining) is a mechanism where one channel sets the TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service request for that channel. When properly enabled, the EDMA engine automatically performs this operation at the major or minor loop completion. The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop). The TCDn_CITER[E_LINK] field determines whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the major loop except for the last. When the major loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be made. For example, the initial fields of: TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as:

Minor loop done → set TCD12_CSR[START] bit
Minor loop done → set TCD12_CSR[START] bit
Minor loop done → set TCD12_CSR[START] bit
Minor loop done, major loop done→ set TCD7_CSR[START] bit When minor loop linking is enabled (TCDn_CITER[E_LINK] = 1), the TCDn_CITER[CITER] field uses a nine bit vector to form the current iteration count. When minor loop linking is disabled (TCDn_CITER[E_LINK] = 0), the TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the CITER value to increase the range of the CITER. Note The TCDn_CITER[E_LINK] bit and the TCDn_BITER[E_LINK] bit must equal or a configuration error is reported. The CITER and BITER vector widths must be equal to calculate the major loop, half-way done interrupt point. The following table summarizes how a DMA channel can link to another DMA channel, i.e, use another channel's TCD, at the end of a loop. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 527 General Business Information

Page 528

Table 22-298. Channel Linking Parameters Desired Link Behavior TCD Control Field Name Description Link at end of Minor Loop CITER[E_LINK] Enable channel-to-channel linking on minor loop completion (current iteration) CITER[LINKCH] Link channel number when linking at end of minor loop (current iteration) Link at end of Major Loop CSR[MAJOR_E_LINK] Enable channel-to-channel linking on major loop completion CSR[MAJOR_LINKCH] Link channel number when linking at end of major loop 22.5.7 Dynamic programming 22.5.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels:

Switch to Round-Robin Channel Arbitration mode, change the channel priorities, then switch back to Fixed Arbitration mode,
Disable all the channels, change the channel priorities, then enable the appropriate channels. 22.5.7.2 Dynamic channel linking Dynamic channel linking is the process of setting the TCD.major.e_link bit during channel execution. This bit is read from the TCD local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution. Because the user is allowed to change the configuration during execution, a coherency model is needed. Consider the scenario where the user attempts to execute a dynamic channel link by enabling the TCD.major.e_link bit at the same time the eDMA engine is retiring the channel. The TCD.major.e_link would be set in the programmer’s model, but it would be unclear whether the actual link was made before the channel retired. The following coherency model is recommended when executing a dynamic channel link request. Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 528 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 529

Step Action 1 Write 1b to the TCD.major.e_link bit. 2 Read back the TCD.major.e_link bit. 3 Test the TCD.major.e_link request status: • If TCD.major.e_link = 1b, the dynamic link attempt was successful. • If TCD.major.e_link = 0b, the attempted dynamic link did not succeed (the channel was already retiring). For this request, the TCD local memory controller forces the TCD.major.e_link bit to zero on any writes to a channel’s TCD.word7 after that channel’s TCD.done bit is set, indicating the major loop is complete. NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link bit. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. 22.5.7.3 Dynamic scatter/gather Scatter/gather is the process of automatically loading a new TCD into a channel. It allows a DMA channel to use multiple TCDs; this enables a DMA channel to scatter the DMA data to multiple destinations or gather it from multiple sources.When scatter/gather is enabled and the channel has finished its major loop, a new TCD is fetched from system memory and loaded into that channel’s descriptor location in eDMA programmer’s model, thus replacing the current descriptor. Because the user is allowed to change the configuration during execution, a coherency model is needed. Consider the scenario where the user attempts to execute a dynamic scatter/gather operation by enabling the TCD.e_sg bit at the same time the eDMA engine is retiring the channel. The TCD.e_sg would be set in the programmer’s model, but it would be unclear whether the actual scatter/gather request was honored before the channel retired. Two methods for this coherency model are shown in the following subsections. Method 1 has the advantage of reading the major.linkch field and the e_sg bit with a single read. For both dynamic channel linking and scatter/gather requests, the TCD local memory controller forces the TCD.major.e_link and TCD.e_sg bits to zero on any writes to a channel’s TCD.word7 if that channel’s TCD.done bit is set indicating the major loop is complete. Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 529 General Business Information

Page 530

NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link or TCD.e_sg bits. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. 22.5.7.3.1 Method 1 (channel not using major loop channel linking) For a channel not using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request. When the TCD.major.e_link bit is zero, the TCD.major.linkch field is not used by the eDMA. In this case, the TCD.major.linkch bits may be used for other purposes. This method uses the TCD.major.linkch field as a TCD indentification (ID).

When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for each TCD associated with a channel using dynamic scatter/gather.
Write 1b to the TCD.d_req bit. Should a dynamic scatter/gather attempt fail, setting the TCD.d_req bit will prevent a future hardware activation of this channel. This stops the channel from executing with a destination address (daddr) that was calculated using a scatter/gather address (written in the next step) instead of a dlast final offest value.
Write the TCD.dlast_sga field with the scatter/gather address.
Write 1b to the TCD.e_sg bit.
Read back the 16 bit TCD control/status field.
Test the TCD.e_sg request status and TCD.major.linkch value: If e_sg = 1b, the dynamic link attempt was successful. If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link did not succeed (the channel was already retiring). If e_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 530 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 531

22.5.7.3.2 Method 2 (channel using major loop channel linking) For a channel using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request. This method uses the TCD.dlast_sga field as a TCD indentification (ID).

Write 1b to the TCD.d_req bit. Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future hardware activation of this channel. This stops the channel from executing with a destination address (daddr) that was calculated using a scatter/gather address (written in the next step) instead of a dlast final offest value.
Write theTCD.dlast_sga field with the scatter/gather address.
Write 1b to the TCD.e_sg bit.
Read back the TCD.e_sg bit.
Test the TCD.e_sg request status: If e_sg = 1b, the dynamic link attempt was successful. If e_sg = 0b, read the 32 bit TCD dlast_sga field. If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). Chapter 22 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 531 General Business Information

Page 532

Initialization/application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 532 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 533

Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits. The overflow of the watchdog counter must not occur if the software code works well and services the watchdog to re-start the actual counter. For safety, a redundant watchdog system, External Watchdog Monitor (EWM), is designed to monitor external circuits, as well as the MCU software flow. This provides a back-up mechanism to the internal watchdog that resets the MCU's CPU and peripherals. The EWM differs from the internal watchdog in that it does not reset the MCU's CPU and peripherals. The EWM if allowed to time-out, provides an independent EWM_out pin that when asserted resets or places an external circuit into a safe mode. The CPU resets the EWM counter that is logically ANDed with an external digital input pin. This pin allows an external circuit to influence the reset_out signal. 23.1.1 Features Features of EWM module include: K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 533 General Business Information

Page 534

• Independent LPO clock source • Programmable time-out period specified in terms of number of EWM LPO clock cycles. • Windowed refresh option • Provides robust check that program flow is faster than expected. • Programmable window. • Refresh outside window leads to assertion of EWM_out. • Robust refresh mechanism • Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_service_time) peripheral bus clock cycles. • One output port, EWM_out, when asserted is used to reset or place the external circuit into safe mode. • One Input port, EWM_in, allows an external circuit to control the EWM_out signal. 23.1.2 Modes of Operation This section describes the module's operating modes. 23.1.2.1 Stop Mode When the EWM is in stop mode, the CPU services to the EWM cannot occur. On entry to stop mode, the EWM’s counter freezes. There are two possible ways to exit from Stop mode: • On exit from stop mode through a reset, the EWM remains disabled. • On exit from stop mode by an interrupt, the EWM is re-enabled, and the counter continues to be clocked from the same value prior to entry to stop mode. Note the following if the EWM enters the stop mode during CPU service mechanism: At the exit from stop mode by an interrupt, refresh mechanism state machine starts from the previous state which means, if first service command is written correctly and EWM enters the stop mode immediately, the next command has to be written within the next 15 (EWM_service_time) peripheral bus clocks after exiting from stop mode. User must mask all interrupts prior to executing EWM service instructions. Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 534 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 535

23.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. 23.1.2.3 Debug Mode Entry to debug mode has no effect on the EWM. • If the EWM is enabled prior to entry of debug mode, it remains enabled. • If the EWM is disabled prior to entry of debug mode, it remains disabled. 23.1.3 Block Diagram This figure shows the EWM block diagram. Clock Gating Cell EWM_out EWM Out Logic EWM_out OR Low Power Clock Enable Counter Overflow CPU Reset Reset to Counter EWM refresh EWM enable Counter >Compare High Counter < Compare Low AND ((EWM_in ^ assert_in) || ~EWM_in_enable) Compare High > Counter > Compare Low 1 1 Figure 23-1. EWM Block Diagram Chapter 23 External Watchdog Monitor (EWM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 535 General Business Information

Page 536

23.2 EWM Signal Descriptions The EWM has two external signals, as shown in the following table. Table 23-1. EWM Signal Descriptions Signal Description I/O EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. I EWM_out EWM reset out signal O 23.3 Memory Map/Register Definition This section contains the module memory map and registers. EWM memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4006_1000 Control Register (EWM_CTRL) 8 R/W 000h 23.3.1/536 4006_1001 Service Register (EWM_SERV) 8 W (always reads 0) 000h 23.3.2/537 4006_1002 Compare Low Register (EWM_CMPL) 8 R/W 000h 23.3.3/537 4006_1003 Compare High Register (EWM_CMPH) 8 R/W FFFFh 23.3.4/538 4006_1005 Clock Prescaler Register (EWM_CLKPRESCALER) 8 R/W 000h 23.3.5/539 23.3.1 Control Register (EWM_CTRL) The CTRL register is cleared by any reset. NOTE INEN, ASSIN and EWMEN bits can be written once after a CPU reset. Modifying these bits more than once, generates a bus transfer error. Address: 4006_1000h base + 0h offset = 4006_1000h Bit 7 6 5 4 3 2 1 0 Read 0 INTEN INEN ASSIN EWMEN Write Reset 0 0 0 0 0 0 0 0 EWM Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 536 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 537

EWM_CTRL field descriptions Field Description 7–4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 INTEN Interrupt Enable. This bit when set and EWM_out is asserted, an interrupt request is generated. To de-assert interrupt request, user should clear this bit by writing 0. 2 INEN Input Enable. This bit when set, enables the EWM_in port. 1 ASSIN EWM_in's Assertion State Select. Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit inverts the assert state to a logic one. 0 EWMEN EWM enable. This bit when set, enables the EWM module. This resets the EWM counter to zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and therefore it cannot be enabled until a reset occurs, due to the write-once nature of this bit. 23.3.2 Service Register (EWM_SERV) The SERV register provides the interface from the CPU to the EWM module. It is write- only and reads of this register return zero. Address: 4006_1000h base + 1h offset = 4006_1001h Bit 7 6 5 4 3 2 1 0 Read 0 Write SERVICE Reset 0 0 0 0 0 0 0 0 EWM_SERV field descriptions Field Description 7–0 SERVICE The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The EWM service is illegal if either of the following conditions is true. • The first or second data byte is not written correctly. • The second data byte is not written within a fixed number of peripheral bus cycles of the first data byte. This fixed number of cycles is called EWM_service_time. 23.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to service the EWM counter. Chapter 23 External Watchdog Monitor (EWM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 537 General Business Information

Page 538

NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. Address: 4006_1000h base + 2h offset = 4006_1002h Bit 7 6 5 4 3 2 1 0 Read COMPAREL Write Reset 0 0 0 0 0 0 0 0 EWM_CMPL field descriptions Field Description 7–0 COMPAREL To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum service time is required. 23.3.4 Compare High Register (EWM_CMPH) The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum of 256 clocks time, for the CPU to service the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. NOTE The valid values for CMPH are up to 0xFE because the EWM counter never expires when CMPH = 0xFF. The expiration happens only if EWM counter is greater than CMPH. Address: 4006_1000h base + 3h offset = 4006_1003h Bit 7 6 5 4 3 2 1 0 Read COMPAREH Write Reset 1 1 1 1 1 1 1 1 EWM_CMPH field descriptions Field Description 7–0 COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required. Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 538 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 539

23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER) This CLKPRESCALER register is reset to 0x00 after a CPU reset. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. NOTE Write the required prescaler value before enabling the EWM. NOTE The implementation of this register is chip-specific. See the Chip Configuration details. Address: 4006_1000h base + 5h offset = 4006_1005h Bit 7 6 5 4 3 2 1 0 Read CLK_DIV Write Reset 0 0 0 0 0 0 0 0 EWM_CLKPRESCALER field descriptions Field Description 7–0 CLK_DIV Selected low power source for running the EWM counter can be prescaled as below. • Prescaled clock frequency = low power clock source frequency/ ( 1+ CLK_DIV ) 23.4 Functional Description The following sections describe functional details of the EWM module. 23.4.1 The EWM_out Signal The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance. The EWM_out signal remains deasserted when the EWM is being regularly serviced by the CPU within the programmable service window, indicating that the application code is executed as expected. Chapter 23 External Watchdog Monitor (EWM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 539 General Business Information

Page 540

The EWM_out signal is asserted in any of the following conditions: • Servicing the EWM when the counter value is less than CMPL value. • If the EWM counter value reaches the CMPH value, and no EWM service has occurred. • Servicing the EWM when the counter value is more than CMPL and less than CMPH values and EWM_in signal is asserted. • If functionality of EWM_in pin is enabled and EWM_in pin is asserted while servicing the EWM. • After any reset (by the virtue of the external pull-down mechanism on the EWM_out pin) On a normal reset, the EWM_out is asserted. To deassert the EWM_out, set EWMEN bit in the CTRL register to enable the EWM. If the EWM_out signal shares its pad with a digital I/O pin, on reset this actual pad defers to being an input signal. It takes the EWM_out output condition only after you enable the EWM by the EWMEN bit in the CTRL register. When the EWM_out pin is asserted, it can only be deasserted by forcing a MCU reset. Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset. 23.4.2 The EWM_in Signal The EWM_in is a digital input signal that allows an external circuit to control the EWM_out signal. For example, in the application, an external circuit monitors a critical safety function, and if there is fault with this circuit's behavior, it can then actively initiate the EWM_out signal that controls the gating circuit. The EWM_in signal is ignored if the EWM is disabled, or if INEN bit of CTRL register is cleared, as after any reset. On enabling the EWM (setting the CTRL[EWMEN] bit) and enabling EWM_in functionality (setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU servicing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out pin is asserted. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 540 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 541

Note You must update the CMPH and CMPL registers prior to enabling the EWM. After enabling the EWM, the counter resets to zero, therefore providing a reasonable time after a power-on reset for the external monitoring circuit to stabilize and ensure that the EWM_in pin is deasserted. 23.4.3 EWM Counter It is an 8-bit ripple counter fed from a clock source that is independent of the peripheral bus clock source. As the preferred time-out is between 1 ms and 100 ms the actual clock source should be in the kHz range. The counter is reset to zero, after a CPU reset, or a EWM refresh cycle. The counter value is not accessible to the CPU. 23.4.4 EWM Compare Registers The compare registers CMPL and CMPH are write-once after a CPU reset and cannot be modified until another CPU reset occurs. The EWM compare registers are used to create a service window, which is used by the CPU to service/refresh the EWM module. • If the CPU services the EWM when the counter value lies between CMPL value and CMPH value, the counter is reset to zero. This is a legal service operation. • If the CPU executes a EWM service/refresh action outside the legal service window, EWM_out is asserted. It is illegal to program CMPL and CMPH with same value. In this case, as soon as counter reaches (CMPL + 1), EWM_out is asserted. 23.4.5 EWM Refresh Mechanism Other than the initial configuration of the EWM, the CPU can only access the EWM by the EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers. Therefore, three possible conditions can occur: Chapter 23 External Watchdog Monitor (EWM) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 541 General Business Information

Page 542

Table 23-8. EWM Refresh Mechanisms Condition Mechanism A unique EWM service occurs when CMPL < Counter < CMPH. The software behaves as expected and the counter of the EWM is reset to zero, and EWM_out pin remains in the deasserted state. Note: EWM_in pin is also assumed to be in the deasserted state. A unique EWM service occurs when Counter < CMPL The software services the EWM and therefore resets the counter to zero and asserts the EWM_out pin (irrespective of the EWM_in pin). The EWM_out pin is expected to gate critical safety circuits. Counter value reaches CMPH prior to a unique EWM service The counter value reaches the CMPH value and no service of the EWM resets the counter to zero and assert the EWM_out pin (irrespective of the EWM_in pin). The EWM_out pin is expected to gate critical safety circuits. Any illegal service on EWM has no effect on EWM_out. 23.4.6 EWM Interrupt When EWM_out is asserted, an interrupt request is generated to indicate the assertion of the EWM reset out signal. This interrupt is enabled when CTRL[INTEN] is set. Clearing this bit clears the interrupt request but does not affect EWM_out. The EWM_out signal can be deasserted only by forcing a system reset. 23.4.7 Counter clock prescaler The EWM counter clock source can be prescaled by a clock divider, by programming CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter. NOTE The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 542 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 543

Chapter 24 Watchdog Timer (WDOG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Reasons for failure include run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences. In such cases, the watchdog brings the system into a safe state of operation. The watchdog monitors the operation of the system by expecting periodic communication from the software, generally known as servicing or refreshing the watchdog. If this periodic refreshing does not occur, the watchdog resets the system. 24.2 Features The features of the Watchdog Timer (WDOG) include: • Clock source input independent from CPU/bus clock. Choice between two clock sources: • Low-power oscillator (LPO) • External system clock • Unlock sequence for allowing updates to write-once WDOG control/configuration bits. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 543 General Business Information

Page 544

• All WDOG control/configuration bits are writable once only within 256 bus clock cycles of being unlocked. • You need to always update these bits after unlocking within 256 bus clock cycles. Failure to update these bits resets the system. • Programmable time-out period specified in terms of number of WDOG clock cycles. • Ability to test WDOG timer and reset with a flag indicating watchdog test. • Quick test—Small time-out value programmed for quick test. • Byte test—Individual bytes of timer tested one at a time. • Read-only access to the WDOG timer—Allows dynamic check that WDOG timer is operational. NOTE Reading the watchdog timer counter while running the watchdog on the bus clock might not give the accurate counter value. • Windowed refresh option • Provides robust check that program flow is faster than expected. • Programmable window. • Refresh outside window leads to reset. • Robust refresh mechanism • Write values of 0xA602 and 0xB480 to WDOG Refresh Register within 20 bus clock cycles. • Count of WDOG resets as they occur. • Configurable interrupt on time-out to provide debug breadcrumbs. This is followed by a reset after 256 bus clock cycles. Features K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 544 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 545

24.3 Functional overview 0xC520 0xD928 Fast Fn Test Clock Allow update for N bus clk cycles N bus clk cycles LPO N bus clk cycles Refresh Sequence 2 writes of data within K bus clock cycles of each other Unlock Sequence 2 Writes of data within K bus clock cycles of each other Disable Control/Configuration bit changes N bus clk cycles after unlocking WDOGEN = WDOG Enable WINEN = Windowed Mode Enable WDOGT = WDOG Time-out Value WDOGCLKSRC = WDOG Clock Source WDOG Test = WDOG Test Mode WAIT EN = Enable in wait mode STOP EN = Enable in stop mode Debug EN = Enable in debug mode SRS = System Reset Status Register R = Timer Reload WDOG reset count Alt Clock Osc WDOG Clock Selection WDOG CLK R System reset and SRS register Interrupt IRQ_RST_ EN = = 1? Invalid Unlock Seq 32-bit Timer Timer Time-out Refresh Outside Window Invalid Refresh Seq No config after unlocking No unlock after reset 0xB480 0xA602 System Bus Clock 32-bit Modulus Reg (Time-out Value) DebugEN Window_begin WDOGTEST STOPEN WAITEN WDOGT WDOG CLKSRC WINEN WDOGEN WDOG Y N Figure 24-1. WDOG operation The preceding figure shows the operation of the watchdog. The values for N and K are: • N = 256 • K = 20 The watchdog is a fail safe mechanism that brings the system into a known initial state in case of its failure due to CPU clock stopping or a run-away condition in code execution. In its simplest form, the watchdog timer runs continuously off a clock source and expects Chapter 24 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 545 General Business Information

Page 546

to be serviced periodically, failing which it resets the system. This ensures that the software is executing correctly and has not run away in an unintended direction. Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. You can select a windowed mode of operation that expects the servicing to be done only in a particular window of the time-out period. An attempted servicing of the watchdog outside this window results in a reset. By operating in this mode, you can get an indication of whether the code is running faster than expected. The window length is also user programmable. If a system fails to update/refresh the watchdog due to an unknown and persistent cause, it will be caught in an endless cycle of resets from the watchdog. To analyze the cause of such conditions, you can program the watchdog to first issue an interrupt, followed by a reset. In the interrupt service routine, the software can analyze the system stack to aid debugging. To enhance the independence of watchdog from the system, it runs off an independent LPO oscillator clock. You can also switch over to an alternate clock source if required, through a control register bit. 24.3.1 Unlocking and updating the watchdog As long as ALLOW_UPDATE in the watchdog control register is set, you can unlock and modify the write-once-only control and configuration registers:

Write 0xC520 followed by 0xD928 within 20 bus clock cycles to a specific unlock register (WDOG_UNLOCK).
Wait one bus clock cycle. You cannot update registers on the bus clock cycle immediately following the write of the unlock sequence.
An update window equal in length to the watchdog configuration time (WCT) opens. Within this window, you can update the configuration and control register bits. These register bits can be modified only once after unlocking. If none of the configuration and control registers is updated within the update window, the watchdog issues a reset, that is, interrupt-then-reset, to the system. Trying to unlock the watchdog within the WCT after an initial unlock has no effect. During the update operation, the watchdog timer is not paused and continues running in the background. After the update window closes, the watchdog timer restarts and the watchdog functions according to the new configuration. Functional overview K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 546 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 547

The update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. This means the application coder does not have to frequently service the watchdog. After the critical part of the application begins, the watchdog can be reconfigured as needed. The watchdog issues a reset, that is, interrupt-then-reset if enabled, to the system for any of these invalid unlock sequences: • You write any value other than 0xC520 or 0xD928 to the unlock register. • ALLOW_UPDATE is set and you allow a gap of more than 20 bus clock cycles between the writing of the unlock sequence values. An attempted refresh operation between the two writes of the unlock sequence and in the WCT time following a successful unlock, goes undetected. Also, see Watchdog Operation with 8-bit access for guidelines related to 8-bit accesses to the unlock register. Note A context switch during unlocking and refreshing may lead to a watchdog reset. 24.3.2 Watchdog configuration time (WCT) To prevent unintended modification of the watchdog's control and configuration register bits, you are allowed to update them only within a period of 256 bus clock cycles after unlocking. This period is known as the watchdog configuration time (WCT). In addition, these register bits can be modified only once after unlocking them for editing, even after reset. You must unlock the registers within WCT after system reset, failing which the WDOG issues a reset to the system. In other words, you must write at least the first word of the unlocking sequence within the WCT after reset. After this is done, you have a further 20 bus clock cycles, the maximum allowed gap between the words of the unlock sequence, to complete the unlocking operation. Thereafter, to make sure that you do not forget to configure the watchdog, the watchdog issues a reset if none of the WDOG control and configuration registers is updated in the WCT after unlock. After the close of this window or after the first write, these register bits are locked out from any further changes. The watchdog timer keeps running according to its default configuration through unlocking and update operations that can extend up to a maximum total of 2xWCT + 20 bus clock cycles. Therefore, it must be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles. Chapter 24 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 547 General Business Information

Page 548

Updates in the write-once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately: • Stop, Wait, and Debug mode enable • IRQ_RST_EN The operations of refreshing the watchdog goes undetected during the WCT. 24.3.3 Refreshing the watchdog A robust refreshing mechanism has been chosen for the watchdog. A valid refresh is a write of 0xA602 followed by 0xB480 within 20 bus clock cycles to watchdog refresh register. If these two values are written more than 20 bus cycles apart or if something other than these two values is written to the register, a watchdog reset, or interrupt-then- reset if enabled, is issued to the system. A valid refresh makes the watchdog timer restart on the next bus clock. Also, an attempted unlock operation in between the two writes of the refresh sequence goes undetected. See Watchdog Operation with 8-bit access for guidelines related to 8-bit accesses to the refresh register. 24.3.4 Windowed mode of operation In this mode of operation, a restriction is placed on the point in time within the time-out period at which the watchdog can be refreshed. The refresh is considered valid only when the watchdog timer increments beyond a certain count as specified by the watchdog window register. This is known as refreshing the watchdog within a window of the total time-out period. If a refresh is attempted before the timer reaches the window value, the watchdog generates a reset, or interrupt-then-reset if enabled. If there is no refresh at all, the watchdog times out and generates a reset or interrupt-then-reset if enabled. 24.3.5 Watchdog disabled mode of operation When the watchdog is disabled through the WDOG_EN bit in the watchdog status and control register, the watchdog timer is reset to zero and is disabled from counting until you enable it or it is enabled again by the system reset. In this mode, the watchdog timer cannot be refreshed–there is no requirement to do so while the timer is disabled. However, the watchdog still generates a reset, or interrupt-then-reset if enabled, on a non- Functional overview K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 548 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 549

time-out exception. See Generated Resets and Interrupts. You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. 24.3.6 Low-power modes of operation The low-power modes of operation of the watchdog are described in the following table: Table 24-1. Low-power modes of operation Mode Behavior Wait If the WDOG is enabled (WAIT_EN = 1), it can run on bus clock or low-power oscillator clock (CLK_SRC = x) to generate interrupt (IRQ_RST_EN=1) followed by a reset on time-out. After reset the WDOG reset counter increments by one. Stop Where the bus clock is gated, the WDOG can run only on low-power oscillator clock (CLK_SRC=0) if it is enabled in stop (STOP_EN=1). In this case, the WDOG runs to time-out twice, and then generates a reset from its backup circuitry. Therefore, if you program the watchdog to time-out after 100 ms and then enter such a stop mode, the reset will occur after 200 ms. Also, in this case, no interrupt will be generated irrespective of the value of IRQ_RST_EN bit. After WDOG reset, the WDOG reset counter will also not increment. Power-Down The watchdog is powered off. 24.3.7 Debug modes of operation You can program the watchdog to disable in debug modes through DBG_EN in the watchdog control register. This results in the watchdog timer pausing for the duration of the mode. Register read/writes are still allowed, which means that operations like refresh, unlock, and so on are allowed. Upon exit from the mode, the timer resumes its operation from the point of pausing. The entry of the system into the debug mode does not excuse it from compulsorily configuring the watchdog in the WCT time after unlock, unless the system bus clock is gated off, in which case the internal state machine pauses too. Failing to do so still results in a reset, or interrupt-then-reset, if enabled, to the system. Also, all of the exception conditions that result in a reset to the system, as described in Generated Resets and Interrupts, are still valid in this mode. So, if an exception condition occurs and the system bus clock is on, a reset occurs, or interrupt-then-reset, if enabled. The entry into Debug mode within WCT after reset is treated differently. The WDOG timer is kept reset to zero and there is no need to unlock and configure it within WCT. You must not try to refresh or unlock the WDOG in this state or unknown behavior may result. Upon exit from this mode, the WDOG timer restarts and the WDOG has to be unlocked and configured within WCT. Chapter 24 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 549 General Business Information

Page 550

24.4 Testing the watchdog For IEC 60730 and other safety standards, the expectation is that anything that monitors a safety function must be tested, and this test is required to be fault tolerant. To test the watchdog, its main timer and its associated compare and reset logic must be tested. To this end, two tests are implemented for the watchdog, as described in Quick Test and Byte Test. A control bit is provided to put the watchdog into functional test mode. There is also an overriding test-disable control bit which allows the functional test mode to be disabled permanently. After it is set, this test-disable bit can only be cleared by a reset. These two tests achieve the overall aim of testing the counter functioning and the compare and reset logic. Note Do not enable the watchdog interrupt during these tests. If required, you must ensure that the effective time-out value is greater than WCT time. See Generated Resets and Interrupts for more details. To run a particular test:

Select either quick test or byte test..
Set a certain test mode bit to put the watchdog in the functional test mode. Setting this bit automatically switches the watchdog timer to a fast clock source. The switching of the clock source is done to achieve a faster time-out and hence a faster test. In a successful test, the timer times out after reaching the programmed time-out value and generates a system reset. Note After emerging from a reset due to a watchdog test, unlock and configure the watchdog. The refresh and unlock operations and interrupt are not automatically disabled in the test mode. Testing the watchdog K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 550 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 551

24.4.1 Quick test In this test, the time-out value of watchdog timer is programmed to a very low value to achieve quick time-out. The only difference between the quick test and the normal mode of the watchdog is that TESTWDOG is set for the quick test. This allows for a faster test of the watchdog reset mechanism. 24.4.2 Byte test The byte test is a more thorough a test of the watchdog timer. In this test, the timer is split up into its constituent byte-wide stages that are run independently and tested for time-out against the corresponding byte of the time-out value register. The following figure explains the splitting concept: CLK WDOG en Mod = = Timer? Test 32-bit Timer Modulus Register (Time-out Value) WDOG Reset Nth Stage Overflow Enables N + 1th Stage en en Reset Value (Hardwired) Byte Stage 4 Equality Comparison Byte 4 Byte 2 Byte 1 Byte 3 Byte Stage 3 Byte Stage 2 Byte Stage 1 Figure 24-2. Watchdog timer byte splitting Each stage is an 8-bit synchronous counter followed by combinational logic that generates an overflow signal. The overflow signal acts as an enable to the N + 1th stage. In the test mode, when an individual byte, N, is tested, byte N – 1 is loaded forcefully with 0xFF, and both these bytes are allowed to run off the clock source. By doing so, the overflow signal from stage N – 1 is generated immediately, enabling counter stage N. The Nth stage runs and compares with the Nth byte of the time-out value register. In this way, the byte N is also tested along with the link between it and the preceding stage. No Chapter 24 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 551 General Business Information

Page 552

other stages, N – 2, N – 3... and N + 1, N + 2... are enabled for the test on byte N. These disabled stages, except the most significant stage of the counter, are loaded with a value of 0xFF. 24.5 Backup reset generator The backup reset generator generates the final reset which goes out to the system. It has a backup mechanism which ensures that in case the bus clock stops and prevents the main state machine from generating a reset exception/interrupt, the watchdog timer's time-out is separately routed out as a reset to the system. Two successive timer time-outs without an intervening system reset result in the backup reset generator routing out the time-out signal as a reset to the system. 24.6 Generated resets and interrupts The watchdog generates a reset in the following events, also referred to as exceptions: • A watchdog time-out • Failure to unlock the watchdog within WCT time after system reset deassertion • No update of the control and configuration registers within the WCT window after unlocking. At least one of the following registers must be written to within the WCT window to avoid reset: • WDOG_ST_CTRL_H, WDOG_ST_CTRL_L • WDOG_TO_VAL_H, WDOG_TO_VAL_L • WDOG_WIN_H, WDOG_WIN_L • WDOG_PRESCALER • A value other than the unlock sequence or the refresh sequence is written to the unlock and/or refresh registers, respectively. • A gap of more than 20 bus cycles exists between the writes of two values of the unlock sequence. • A gap of more than 20 bus cycles exists between the writes of two values of the refresh sequence. Backup reset generator K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 552 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 553

The watchdog can also generate an interrupt. If IRQ_RST_EN is set, then on the above mentioned events WDOG_ST_CTRL_L[INT_FLG] is set, generating an interrupt. A watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant. The interrupt can be cleared by writing 1 to INT_FLG. The gap of WCT between interrupt and reset means that the WDOG time-out value must be greater than WCT. Otherwise, if the interrupt was generated due to a time-out, a second consecutive time-out will occur in that WCT gap. This will trigger the backup reset generator to generate a reset to the system, prematurely ending the interrupt service routine execution. Also, jobs such as counting the number of watchdog resets would not be done. 24.7 Memory map and register definition This section consists of the memory map and register descriptions. WDOG memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4005_2000 Watchdog Status and Control Register High (WDOG_STCTRLH) 16 R/W 01D_31D3h 24.7.1/554 4005_2002 Watchdog Status and Control Register Low (WDOG_STCTRLL) 16 R/W 0_0011h 24.7.2/555 4005_2004 Watchdog Time-out Value Register High (WDOG_TOVALH) 16 R/W 00_4C4Ch 24.7.3/556 4005_2006 Watchdog Time-out Value Register Low (WDOG_TOVALL) 16 R/W 4B4C_4B4Ch 24.7.4/556 4005_2008 Watchdog Window Register High (WDOG_WINH) 16 R/W 0_0000h 24.7.5/557 4005_200A Watchdog Window Register Low (WDOG_WINL) 16 R/W 00_1010h 24.7.6/557 4005_200C Watchdog Refresh register (WDOG_REFRESH) 16 R/W B480_B480h 24.7.7/558 4005_200E Watchdog Unlock register (WDOG_UNLOCK) 16 R/W D928_D928h 24.7.8/558 4005_2010 Watchdog Timer Output Register High (WDOG_TMROUTH) 16 R/W 0_0000h 24.7.9/558 4005_2012 Watchdog Timer Output Register Low (WDOG_TMROUTL) 16 R/W 0_0000h 24.7.10/ 559 4005_2014 Watchdog Reset Count register (WDOG_RSTCNT) 16 R/W 0_0000h 24.7.11/ 559 4005_2016 Watchdog Prescaler register (WDOG_PRESC) 16 R/W 040_0400h 24.7.12/ 560 Chapter 24 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 553 General Business Information

Page 554

24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH) Address: 4005_2000h base + 0h offset = 4005_2000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 DISTESTWDO G BYTESEL[1:0] TESTSEL TESTWDOG 0 Reserved WAITEN STOPEN DBGEN ALLOWUPDAT E WINEN IRQRSTEN CLKSRC WDOGEN Write Reset 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 1 WDOG_STCTRLH field descriptions Field Description 15 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 14 DISTESTWDOG Allows the WDOG’s functional test mode to be disabled permanently. After it is set, it can only be cleared by a reset. It cannot be unlocked for editing after it is set. 0 WDOG functional test mode is not disabled. 1 WDOG functional test mode is disabled permanently until reset. 13–12 BYTESEL[1:0] This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. 00 Byte 0 selected 01 Byte 1 selected 10 Byte 2 selected 11 Byte 3 selected 11 TESTSEL Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer. 0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. 1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. 10 TESTWDOG Puts the watchdog in the functional test mode. In this mode, the watchdog timer and the associated compare and reset generation logic is tested for correct operation. The clock for the timer is switched from the main watchdog clock to the fast clock input for watchdog functional test. The TESTSEL bit selects the test to be run. 9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8 Reserved This field is reserved. 7 WAITEN Enables or disables WDOG in Wait mode. 0 WDOG is disabled in CPU Wait mode. 1 WDOG is enabled in CPU Wait mode. 6 STOPEN Enables or disables WDOG in Stop mode. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 554 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 555

WDOG_STCTRLH field descriptions (continued) Field Description 0 WDOG is disabled in CPU Stop mode. 1 WDOG is enabled in CPU Stop mode. 5 DBGEN Enables or disables WDOG in Debug mode. 0 WDOG is disabled in CPU Debug mode. 1 WDOG is enabled in CPU Debug mode. 4 ALLOWUPDATE Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window (WCT) closes, through unlock sequence. 0 No further updates allowed to WDOG write-once registers. 1 WDOG write-once registers can be unlocked for updating. 3 WINEN Enables Windowing mode. 0 Windowing mode is disabled. 1 Windowing mode is enabled. 2 IRQRSTEN Used to enable the debug breadcrumbs feature. A change in this bit is updated immediately, as opposed to updating after WCT. 0 WDOG time-out generates reset only. 1 WDOG time-out initially generates an interrupt. After WCT, it generates a reset. 1 CLKSRC Selects clock source for the WDOG timer and other internal timing operations. 0 WDOG clock sourced from LPO . 1 WDOG clock sourced from alternate clock source. 0 WDOGEN Enables or disables the WDOG’s operation. In the disabled state, the watchdog timer is kept in the reset state, but the other exception conditions can still trigger a reset/interrupt. A change in the value of this bit must be held for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled. 0 WDOG is disabled. 1 WDOG is enabled. 24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL) Address: 4005_2000h base + 2h offset = 4005_2002h Bit 15 14 13 12 11 10 9 8 Read INTFLG Reserved Write Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Read Reserved Write Reset 0 0 0 0 0 0 0 1 Chapter 24 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 555 General Business Information

Page 556

WDOG_STCTRLL field descriptions Field Description 15 INTFLG Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a precondition to set this flag. INTFLG = 1 results in an interrupt being issued followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this bit. It also gets cleared on a system reset. 14–0 Reserved This field is reserved. NOTE: Do not modify this field value. 24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH) Address: 4005_2000h base + 4h offset = 4005_2004h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TOVALHIGH Write Reset 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 WDOG_TOVALH field descriptions Field Description 15–0 TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock. 24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL) The time-out value of the watchdog must be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. Address: 4005_2000h base + 6h offset = 4005_2006h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TOVALLOW Write Reset 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 WDOG_TOVALL field descriptions Field Description 15–0 TOVALLOW Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 556 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 557

24.7.5 Watchdog Window Register High (WDOG_WINH) NOTE You must set the Window Register value lower than the Time- out Value Register. Address: 4005_2000h base + 8h offset = 4005_2008h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WINHIGH Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG_WINH field descriptions Field Description 15–0 WINHIGH Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is defined in terms of cycles of the watchdog clock. In this mode, the watchdog can be refreshed only when the timer has reached a value greater than or equal to this window length. A refresh outside this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. 24.7.6 Watchdog Window Register Low (WDOG_WINL) NOTE You must set the Window Register value lower than the Time- out Value Register. Address: 4005_2000h base + Ah offset = 4005_200Ah Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WINLOW Write Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 WDOG_WINL field descriptions Field Description 15–0 WINLOW Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is defined in terms of cycles of the pre-scaled watchdog clock. In this mode, the watchdog can be refreshed only when the timer reaches a value greater than or equal to this window length value. A refresh outside of this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. Chapter 24 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 557 General Business Information

Page 558

24.7.7 Watchdog Refresh register (WDOG_REFRESH) Address: 4005_2000h base + Ch offset = 4005_200Ch Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WDOGREFRESH Write Reset 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 WDOG_REFRESH field descriptions Field Description 15–0 WDOGREFRESH Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 bus clock cycles written to this register refreshes the WDOG and prevents it from resetting the system. Writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system, or if IRQRSTEN is set, it interrupts and then resets the system. 24.7.8 Watchdog Unlock register (WDOG_UNLOCK) Address: 4005_2000h base + Eh offset = 4005_200Eh Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WDOGUNLOCK Write Reset 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 0 WDOG_UNLOCK field descriptions Field Description 15–0 WDOGUNLOCK Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again. The required unlock sequence is 0xC520 followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a window equal in length to the WCT within which you can update the registers. Writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts and then resets the system. The unlock sequence is effective only if ALLOWUPDATE is set. 24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH) Address: 4005_2000h base + 10h offset = 4005_2010h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TIMEROUTHIGH Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Memory map and register definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 558 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 559

WDOG_TMROUTH field descriptions Field Description 15–0 TIMEROUTHIGH Shows the value of the upper 16 bits of the watchdog timer. 24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL) During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following the watchdog timer. Address: 4005_2000h base + 12h offset = 4005_2012h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TIMEROUTLOW Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG_TMROUTL field descriptions Field Description 15–0 TIMEROUTLOW Shows the value of the lower 16 bits of the watchdog timer. 24.7.11 Watchdog Reset Count register (WDOG_RSTCNT) Address: 4005_2000h base + 14h offset = 4005_2014h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read RSTCNT Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG_RSTCNT field descriptions Field Description 15–0 RSTCNT Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing 1 to the bit to be cleared enables you to clear the contents of this register. Chapter 24 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 559 General Business Information

Page 560

24.7.12 Watchdog Prescaler register (WDOG_PRESC) Address: 4005_2000h base + 16h offset = 4005_2016h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 PRESCVAL 0 Write Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 WDOG_PRESC field descriptions Field Description 15–11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10–8 PRESCVAL 3-bit prescaler for the watchdog clock source. A value of zero indicates no division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL + 1) to provide the prescaled WDOG_CLK. 7–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 24.8 Watchdog operation with 8-bit access 24.8.1 General guideline When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, place the two 8-bit accesses one after the other in your code. 24.8.2 Refresh and unlock operations with 8-bit access One exception condition that generates a reset to the system is the write of any value other than those required for a legal refresh/update sequence to the respective refresh and unlock registers. For an 8-bit access to these registers, writing a correct value requires at least two bus clock cycles, resulting in an invalid value in the registers for one cycle. Therefore, the system is reset even if the intention is to write a correct value to the refresh/unlock register. Keeping this in mind, the exception condition for 8-bit accesses is slightly modified. Watchdog operation with 8-bit access K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 560 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 561

Whereas the match for a correct value for a refresh/unlock sequence is as according to the original definition, the match for an incorrect value is done byte-wise on the refresh/ unlock rather than for the whole 16-bit value. This means that if the high byte of the refresh/unlock register contains any value other than high bytes of the two values that make up the sequence, it is treated as an exception condition, leading to a reset or interrupt-then-reset. The same holds true for the lower byte of the refresh or unlock register. Take the refresh operation that expects a write of 0xA602 followed by 0xB480 to the refresh register, as an example. Table 24-15. Refresh for 8-bit access WDOG_REFRESH[15:8] WDOG_REFRESH[7:0] Sequence value1 or value2 match Mismatch exception Current Value 0xB4 0x80 Value2 match No Write 1 0xB4 0x02 No match No Write 2 0xA6 0x02 Value1 match No Write 3 0xB4 0x02 No match No Write 4 0xB4 0x80 Value2 match. Sequence complete. No Write 5 0x02 0x80 No match Yes As shown in the preceding table, the refresh register holds its reset value initially. Thereafter, two 8-bit accesses are performed on the register to write the first value of the refresh sequence. No mismatch exception is registered on the intermediate write, Write1. The sequence is completed by performing two more 8-bit accesses, writing in the second value of the sequence for a successful refresh. It must be noted that the match of value2 takes place only when the complete 16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock sequence remains unchanged. The difference for 8-bit accesses is that the criterion for detecting a mismatch is less strict. Any 16-bit access still needs to adhere to the original guidelines, mentioned in the sections Refreshing the Watchdog. 24.9 Restrictions on watchdog operation This section mentions some exceptions to the watchdog operation that may not be apparent to you. Chapter 24 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 561 General Business Information

Page 562

• Restriction on unlock/refresh operations—In the period between the closure of the WCT window after unlock and the actual reload of the watchdog timer, unlock and refresh operations need not be attempted. • The update and reload of the watchdog timer happens two to three watchdog clocks after WCT window closes, following a successful configuration on unlock. • Clock Switching Delay—The watchdog uses glitch-free multiplexers at two places – one to choose between the LPO oscillator input and alternate clock input, and the other to choose between the watchdog functional clock and fast clock input for watchdog functional test. A maximum time period of ~2 clock A cycles plus ~2 clock B cycles elapses from the time a switch is requested to the occurrence of the actual clock switch, where clock A and B are the two input clocks to the clock mux. • For the windowed mode, there is a two to three bus clock latency between the watchdog counter going past the window value and the same registering in the bus clock domain. • For proper operation of the watchdog, the watchdog clock must be at least five times slower than the system bus clock at all times. An exception is when the watchdog clock is synchronous to the bus clock wherein the watchdog clock can be as fast as the bus clock. • WCT must be equivalent to at least three watchdog clock cycles. If not ensured, this means that even after the close of the WCT window, you have to wait for the synchronized system reset to deassert in the watchdog clock domain, before expecting the configuration updates to take effect. • The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. • You must take care not only to refresh the watchdog within the watchdog timer's actual time-out period, but also provide enough allowance for the time it takes for the refresh sequence to be detected by the watchdog timer, on the watchdog clock. • Updates cannot be made in the bus clock cycle immediately following the write of the unlock sequence, but one bus clock cycle later. • It should be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles. • An attempted refresh operation, in between the two writes of the unlock sequence and in the WCT time following a successful unlock, will go undetected. Restrictions on watchdog operation K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 562 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 563

• Trying to unlock the watchdog within the WCT time after an initial unlock has no effect. • The refresh and unlock operations and interrupt are not automatically disabled in the watchdog functional test mode. • After emerging from a reset due to a watchdog functional test, you are still expected to go through the mandatory steps of unlocking and configuring the watchdog. The watchdog continues to be in its functional test mode and therefore you should pull the watchdog out of the functional test mode within WCT time of reset. • After emerging from a reset due to a watchdog functional test, you still need to go through the mandatory steps of unlocking and configuring the watchdog. • You must ensure that both the clock inputs to the glitchless clock multiplexers are alive during the switching of clocks. Failure to do so results in a loss of clock at their outputs. • There is a gap of two to three watchdog clock cycles from the point that stop mode is entered to the watchdog timer actually pausing, due to synchronization. The same holds true for an exit from the stop mode, this time resulting in a two to three watchdog clock cycle delay in the timer restarting. In case the duration of the stop mode is less than one watchdog clock cycle, the watchdog timer is not guaranteed to pause. • Consider the case when the first refresh value is written, following which the system enters stop mode with system bus clk still on. If the second refresh value is not written within 20 bus cycles of the first value, the system is reset, or interrupt-then- reset if enabled. Chapter 24 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 563 General Business Information

Page 564

Restrictions on watchdog operation K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 564 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 565

Chapter 25 Multipurpose Clock Generator (MCG) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL). The FLL is controllable by either an internal or an external reference clock. The PLL is controllable by the external reference clock. The module can select either of the FLL or PLL output clocks, or either of the internal or external reference clocks as a source for the MCU system clock. The MCG operates in conjuction with a crystal oscillator, which allows an external crystal, ceramic resonator, or another external clock source to produce the external reference clock. 25.1.1 Features Key features of the MCG module are: • Frequency-locked loop (FLL): • Digitally-controlled oscillator (DCO) • DCO frequency range is programmable for up to four different frequency ranges. • Option to program and maximize DCO output frequency for a low frequency external reference clock source. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 565 General Business Information

Page 566

• Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. • Internal or external reference clock can be used as the FLL source. • Can be used as a clock source for other on-chip peripherals. • Phase-locked loop (PLL): • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source. • Modulo VCO frequency divider • Phase/Frequency detector • Integrated loop filter • Can be used as a clock source for other on-chip peripherals. • Internal reference clock generator: • Slow clock with nine trim bits for accuracy • Fast clock with four trim bits • Can be used as source clock for the FLL. In FEI mode, only the slow Internal Reference Clock (IRC) can be used as the FLL source. • Either the slow or the fast clock can be selected as the clock source for the MCU. • Can be used as a clock source for other on-chip peripherals. • Control signals for the MCG external reference low power oscillator clock generators are provided: • HGO0, RANGE0, EREFS0 • External clock from the Crystal Oscillator : • Can be used as a source for the FLL and/or the PLL. • Can be selected as the clock source for the MCU. • External clock from the Real Time Counter (RTC): • Can only be used as a source for the FLL. • Can be selected as the clock source for the MCU. Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 566 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 567

• External clock monitor with reset and interrupt request capability to check for external clock failure when running in FBE, PEE,, BLPE, or FEE modes • Lock detector with interrupt request capability for use with the PLL • Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference • Reference dividers for both the FLL and the PLL are provided • Reference dividers for the Fast Internal Reference Clock are provided • MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip peripherals • MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals • MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals • MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 567 General Business Information

Page 568

MCGOUTCLK MCGIRCLK MCGFFCLK DCOOUT /(24,25,26,...,55) Phase Detector Charge Pump Internal Filter VCO VCOOUT PLL Multipurpose Clock Generator (MCG) VDIV0 Lock IRCLKEN PLLS LOLS0 LOCK0 Detector / 25 IREFST FLL DMX32 MCGFLLCLK Crystal Oscillator FRDIV n=0-7 / 2n Internal Reference Slow Clock Fast Clock Clock Generator PRDIV0 LOLIE0 Sync Auto Trim Machine IRCST PLLST CLKST ATMS SCTRIM SCFTRIM FCTRIM ATMST IREFSTEN OSCINIT0 EREFS0 HGO0 RANGE0 DRS Clock Valid Peripheral BUSCLK PLLCLKEN0 IRCSCLK IRCS CLKS CLKS DCO LP Filter /(1,2,3,4,5....,25) IREFS STOP CLKS PLLCLKEN0 IREFS PLLS MCG Crystal Oscillator Enable Detect External Reference Clock RTC Oscillator OSCSEL n=0-7 / 2n FLTPRSRV MCGPLLCLK Clock External CME0 LOCRE0 CME1 LOCRE1 LOCS0 LOCS1 Monitor Figure 25-1. Multipurpose Clock Generator (MCG) block diagram Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 568 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 569

25.1.2 Modes of Operation The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 25.2 External Signal Description There are no MCG signals that connect off chip. 25.3 Memory Map/Register Definition This section includes the memory map and register definition. The MCG registers can only be accessed when in supervisor mode. Read or write accesses when in user mode will result in a bus error. MCG memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4006_4000 MCG Control 1 Register (MCG_C1) 8 R/W 044h 25.3.1/570 4006_4001 MCG Control 2 Register (MCG_C2) 8 R/W 8080h 25.3.2/571 4006_4002 MCG Control 3 Register (MCG_C3) 8 R/W Undefined 25.3.3/572 4006_4003 MCG Control 4 Register (MCG_C4) 8 R/W Undefined 25.3.4/573 4006_4004 MCG Control 5 Register (MCG_C5) 8 R/W 000h 25.3.5/574 4006_4005 MCG Control 6 Register (MCG_C6) 8 R/W 000h 25.3.6/575 4006_4006 MCG Status Register (MCG_S) 8 R 1010h 25.3.7/577 4006_4008 MCG Status and Control Register (MCG_SC) 8 R/W 022h 25.3.8/578 4006_400A MCG Auto Trim Compare Value High Register (MCG_ATCVH) 8 R/W 000h 25.3.9/580 4006_400B MCG Auto Trim Compare Value Low Register (MCG_ATCVL) 8 R/W 000h 25.3.10/ 580 4006_400C MCG Control 7 Register (MCG_C7) 8 R/W 000h 25.3.11/ 580 4006_400D MCG Control 8 Register (MCG_C8) 8 R/W 8080h 25.3.12/ 581 4006_400E MCG Control 9 Register (MCG_C9) 8 R/W 000h 25.3.13/ 582 4006_400F MCG Control 10 Register (MCG_C10) 8 R/W 000h 25.3.14/ 582 Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 569 General Business Information

Page 570

25.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Bit 7 6 5 4 3 2 1 0 Read CLKS FRDIV IREFS IRCLKEN IREFSTEN Write Reset 0 0 0 0 0 1 0 0 MCG_C1 field descriptions Field Description 7–6 CLKS Clock Source Select Selects the clock source for MCGOUTCLK . 00 Encoding 0 — Output of FLL or PLL is selected (depends on PLLS control bit). 01 Encoding 1 — Internal reference clock is selected. 10 Encoding 2 — External reference clock is selected. 11 Encoding 3 — Reserved. 5–3 FRDIV FLL External Reference Divider Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is not required to meet this range, but it is recommended in the cases when trying to enter a FLL mode from FBE). 000 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE 0 values, Divide Factor is 32. 001 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE 0 values, Divide Factor is 64. 010 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE 0 values, Divide Factor is 128. 011 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE 0 values, Divide Factor is 256. 100 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE 0 values, Divide Factor is 512. 101 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE 0 values, Divide Factor is 1024. 110 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE 0 values, Divide Factor is 1280 . 111 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE 0 values, Divide Factor is 1536 . 2 IREFS Internal Reference Select Selects the reference clock source for the FLL. 0 External reference clock is selected. 1 The slow internal reference clock is selected. 1 IRCLKEN Internal Reference Clock Enable Enables the internal reference clock for use as MCGIRCLK. Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 570 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 571

MCG_C1 field descriptions (continued) Field Description 0 MCGIRCLK inactive. 1 MCGIRCLK active. 0 IREFSTEN Internal Reference Stop Enable Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. 0 Internal reference clock is disabled in Stop mode. 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. 25.3.2 MCG Control 2 Register (MCG_C2) Address: 4006_4000h base + 1h offset = 4006_4001h Bit 7 6 5 4 3 2 1 0 Read LOCRE0 0 RANGE0 HGO0 EREFS0 LP IRCS Write Reset 1 0 0 0 0 0 0 0 MCG_C2 field descriptions Field Description 7 LOCRE0 Loss of Clock Reset Enable Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set. 0 Interrupt request is generated on a loss of OSC0 external reference clock. 1 Generate a reset request on a loss of OSC0 external reference clock. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5–4 RANGE0 Frequency Range Select Selects the frequency range for the crystal oscillator or external clock source. See the Oscillator (OSC) chapter for more details and the device data sheet for the frequency ranges used. 00 Encoding 0 — Low frequency range selected for the crystal oscillator . 01 Encoding 1 — High frequency range selected for the crystal oscillator . 1X Encoding 2 — Very high frequency range selected for the crystal oscillator . 3 HGO0 High Gain Oscillator Select Controls the crystal oscillator mode of operation. See the Oscillator (OSC) chapter for more details. 0 Configure crystal oscillator for low-power operation. 1 Configure crystal oscillator for high-gain operation. 2 EREFS0 External Reference Select Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details. Table continues on the next page... Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 571 General Business Information

Page 572

MCG_C2 field descriptions (continued) Field Description 0 External reference clock requested. 1 Oscillator requested. 1 LP Low Power Select Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode, LP bit has no affect. 0 FLL or PLL is not disabled in bypass modes. 1 FLL or PLL is disabled in bypass modes (lower power) 0 IRCS Internal Reference Clock Select Selects between the fast or slow internal reference clock source. 0 Slow internal reference clock selected. 1 Fast internal reference clock selected. 25.3.3 MCG Control 3 Register (MCG_C3) Address: 4006_4000h base + 2h offset = 4006_4002h Bit 7 6 5 4 3 2 1 0 Read SCTRIM Write Reset x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • MCG_C3 field descriptions Field Description 7–0 SCTRIM Slow Internal Reference Clock Trim Setting SCTRIM 1 controls the slow internal reference clock frequency by controlling the slow internal reference clock period. The SCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period. An additional fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset, this value is loaded with a factory trim value. If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register.

A value for SCTRIM is loaded during reset from a factory programmed location . Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 572 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 573

25.3.4 MCG Control 4 Register (MCG_C4) NOTE Reset values for DRST and DMX32 bits are 0. Address: 4006_4000h base + 3h offset = 4006_4003h Bit 7 6 5 4 3 2 1 0 Read DMX32 DRST_DRS FCTRIM SCFTRIM Write Reset 0 0 0 x* x* x* x* x*

Notes: x = Undefined at reset. • A value for FCTRIM is loaded during reset from a factory programmed location . x = Undefined at reset. • MCG_C4 field descriptions Field Description 7 DMX32 DCO Maximum Frequency with 32.768 kHz Reference The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. The following table identifies settings for the DCO frequency range. NOTE: The system clocks derived from this source should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL Factor DCO Range 00 0 31.25–39.0625 kHz 640 20–25 MHz 1 32.768 kHz 732 24 MHz 01 0 31.25–39.0625 kHz 1280 40–50 MHz 1 32.768 kHz 1464 48 MHz 10 0 31.25–39.0625 kHz 1920 60–75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25–39.0625 kHz 2560 80–100 MHz 1 32.768 kHz 2929 96 MHz 0 DCO has a default range of 25%. 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. 6–5 DRST_DRS DCO Range Select The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains. See the DCO Frequency Range table for more details. 00 Encoding 0 — Low range (reset default). Table continues on the next page... Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 573 General Business Information

Page 574

MCG_C4 field descriptions (continued) Field Description 01 Encoding 1 — Mid range. 10 Encoding 2 — Mid-high range. 11 Encoding 3 — High range. 4–1 FCTRIM Fast Internal Reference Clock Trim Setting FCTRIM 1 controls the fast internal reference clock frequency by controlling the fast internal reference clock period. The FCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period. If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 0 SCFTRIM Slow Internal Reference Clock Fine Trim SCFTRIM 2 controls the smallest adjustment of the slow internal reference clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount possible. If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this bit.

A value for FCTRIM is loaded during reset from a factory programmed location .
A value for SCFTRIM is loaded during reset from a factory programmed location . 25.3.5 MCG Control 5 Register (MCG_C5) Address: 4006_4000h base + 4h offset = 4006_4004h Bit 7 6 5 4 3 2 1 0 Read 0 PLLCLKEN0 PLLSTEN0 PRDIV0 Write Reset 0 0 0 0 0 0 0 0 MCG_C5 field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 PLLCLKEN0 PLL Clock Enable Enables the PLL independent of PLLS and enables the PLL clock for use as MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz range prior to setting the PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit, and the external oscillator is being used as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set. 0 MCGPLLCLK is inactive. 1 MCGPLLCLK is active. 5 PLLSTEN0 PLL Stop Enable Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 574 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 575

MCG_C5 field descriptions (continued) Field Description Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit has no affect and does not enable the PLL Clock to run if it is written to 1. 0 MCGPLLCLK is disabled in any of the Stop modes. 1 MCGPLLCLK is enabled if system is in Normal Stop mode. 4–0 PRDIV0 PLL External Reference Divider Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not be changed when LOCK 0 is zero. Table 25-7. PLL External Reference Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserve d 00010 3 01010 11 10010 19 11010 Reserve d 00011 4 01011 12 10011 20 11011 Reserve d 00100 5 01100 13 10100 21 11100 Reserve d 00101 6 01101 14 10101 22 11101 Reserve d 00110 7 01110 15 10110 23 11110 Reserve d 00111 8 01111 16 10111 24 11111 Reserve d 25.3.6 MCG Control 6 Register (MCG_C6) Address: 4006_4000h base + 5h offset = 4006_4005h Bit 7 6 5 4 3 2 1 0 Read LOLIE0 PLLS CME0 VDIV0 Write Reset 0 0 0 0 0 0 0 0 MCG_C6 field descriptions Field Description 7 LOLIE0 Loss of Lock Interrrupt Enable Table continues on the next page... Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 575 General Business Information

Page 576

MCG_C6 field descriptions (continued) Field Description Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS 0 is set. 0 No interrupt request is generated on loss of lock. 1 Generate an interrupt request on loss of lock. 6 PLLS PLL Select Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is disabled in all modes. 0 FLL is selected. 1 PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2–4 MHz prior to setting the PLLS bit). 5 CME0 Clock Monitor Enable Enables the loss of clock monitoring circuit for the OSC0 external reference mux select. The LOCRE0 bit will determine if a interrupt or a reset request is generated following a loss of OSC0 indication. The CME0 bit should only be set to a logic 1 when the MCG is in an operational mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, the value of the RANGE0 bits in the C2 register should not be changed. CME0 bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur while in Stop mode. CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. 0 External clock monitor is disabled for OSC0. 1 External clock monitor is enabled for OSC0. 4–0 VDIV0 VCO 0 Divider Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits establish the multiplication factor (M) applied to the reference clock frequency. After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0 value must not be changed when LOCK 0 is zero. Table 25-9. PLL VCO Divide Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55 Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 576 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 577

25.3.7 MCG Status Register (MCG_S) Address: 4006_4000h base + 6h offset = 4006_4006h Bit 7 6 5 4 3 2 1 0 Read LOLS LOCK0 PLLST IREFST CLKST OSCINIT0 IRCST Write Reset 0 0 0 1 0 0 0 0 MCG_S field descriptions Field Description 7 LOLS Loss of Lock Status This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL output frequency has fallen outside the lock exit frequency tolerance, D unl . LOLIE determines whether an interrupt request is made when LOLS is set. LOLRE determines whether a reset request is made when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to this bit has no effect. 0 PLL has not lost lock since LOLS 0 was last cleared. 1 PLL has lost lock since LOLS 0 was last cleared. 6 LOCK0 Lock Status This bit indicates whether the PLL has acquired lock. Lock detection is disabled when not operating in either PBE or PEE mode unless PLLCLKEN=1 and the MCG is not configured in BLPI or BLPE mode. While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted. If the lock status bit is set, changing the value of the PRDIV 0 [4:0] bits in the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL1 reference clock will also cause the LOCK bit to clear until PLL has reacquired lock Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes the lock status bit to clear and stay cleared until the Stop mode is exited and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK bit is cleared, the MCGPLLCLK will be gated off until the LOCK bit is asserted again. 0 PLL is currently unlocked. 1 PLL is currently locked. 5 PLLST PLL Select Status This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a write to the PLLS bit due to internal synchronization between clock domains. 0 Source of PLLS clock is FLL clock. 1 Source of PLLS clock is PLL output clock. 4 IREFST Internal Reference Status This bit indicates the current source for the FLL reference clock. The IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. 0 Source of FLL reference clock is the external reference clock. 1 Source of FLL reference clock is the internal reference clock. Table continues on the next page... Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 577 General Business Information

Page 578

MCG_S field descriptions (continued) Field Description 3–2 CLKST Clock Mode Status These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Encoding 0 — Output of the FLL is selected (reset default). 01 Encoding 1 — Internal reference clock is selected. 10 Encoding 2 — External reference clock is selected. 11 Encoding 3 — Output of the PLL is selected. 1 OSCINIT0 OSC Initialization This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed description for more information. 0 IRCST Internal Reference Clock Status The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The IRCST bit does not update immediately after a write to the IRCS bit due to internal synchronization between clock domains. The IRCST bit will only be updated if the internal reference clock is enabled, either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit . 0 Source of internal reference clock is the slow clock (32 kHz IRC). 1 Source of internal reference clock is the fast clock (4 MHz IRC). 25.3.8 MCG Status and Control Register (MCG_SC) Address: 4006_4000h base + 8h offset = 4006_4008h Bit 7 6 5 4 3 2 1 0 Read ATME ATMS ATMF FLTPRSRV FCRDIV LOCS0 Write Reset 0 0 0 0 0 0 1 0 MCG_SC field descriptions Field Description 7 ATME Automatic Trim Machine Enable Enables the Auto Trim Machine to start automatically trimming the selected Internal Reference Clock. NOTE: ATME deasserts after the Auto Trim Machine has completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit. 0 Auto Trim Machine disabled. 1 Auto Trim Machine enabled. Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 578 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 579

MCG_SC field descriptions (continued) Field Description 6 ATMS Automatic Trim Machine Select Selects the IRCS clock for Auto Trim Test. 0 32 kHz Internal Reference Clock selected. 1 4 MHz Internal Reference Clock selected. 5 ATMF Automatic Trim Machine Fail Flag Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC registers is detected or the MCG enters into any Stop mode. A write to ATMF clears the flag. 0 Automatic Trim Machine completed normally. 1 Automatic Trim Machine failed. 4 FLTPRSRV FLL Filter Preserve Enable This bit will prevent the FLL filter values from resetting allowing the FLL output frequency to remain the same during clock mode changes where the FLL/DCO output is still valid. (Note: This requires that the FLL reference frequency to remain the same as what it was prior to the new clock mode switch. Otherwise FLL filter and frequency values will change.) 0 FLL filter and FLL frequency will reset on changes to currect clock mode. 1 Fll filter and FLL frequency retain their previous values during new clock mode change. 3–1 FCRDIV Fast Clock Internal Reference Divider Selects the amount to divide down the fast internal reference clock. The resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the divider when the Fast IRC is enabled is not supported). 000 Divide Factor is 1 001 Divide Factor is 2. 010 Divide Factor is 4. 011 Divide Factor is 8. 100 Divide Factor is 16 101 Divide Factor is 32 110 Divide Factor is 64 111 Divide Factor is 128. 0 LOCS0 OSC0 Loss of Clock Status The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a logic 1 to it when set. 0 Loss of OSC0 has not occurred. 1 Loss of OSC0 has occurred. Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 579 General Business Information

Page 580

25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH) Address: 4006_4000h base + Ah offset = 4006_400Ah Bit 7 6 5 4 3 2 1 0 Read ATCVH Write Reset 0 0 0 0 0 0 0 0 MCG_ATCVH field descriptions Field Description 7–0 ATCVH ATM Compare Value High Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 25.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL) Address: 4006_4000h base + Bh offset = 4006_400Bh Bit 7 6 5 4 3 2 1 0 Read ATCVL Write Reset 0 0 0 0 0 0 0 0 MCG_ATCVL field descriptions Field Description 7–0 ATCVL ATM Compare Value Low Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 25.3.11 MCG Control 7 Register (MCG_C7) Address: 4006_4000h base + Ch offset = 4006_400Ch Bit 7 6 5 4 3 2 1 0 Read 0 0 OSCSEL Write Reset 0 0 0 0 0 0 0 0 Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 580 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 581

MCG_C7 field descriptions Field Description 7–6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5–1 Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 OSCSEL MCG OSC Clock Select Selects the MCG FLL external reference clock 0 Selects System Oscillator (OSCCLK). 1 Selects 32 kHz RTC Oscillator. 25.3.12 MCG Control 8 Register (MCG_C8) Address: 4006_4000h base + Dh offset = 4006_400Dh Bit 7 6 5 4 3 2 1 0 Read LOCRE1 LOLRE CME1 0 LOCS1 Write Reset 1 0 0 0 0 0 0 0 MCG_C8 field descriptions Field Description 7 LOCRE1 Loss of Clock Reset Enable Determines if a interrupt or a reset request is made following a loss of RTC external reference clock. The LOCRE1 only has an affect when CME1 is set. 0 Interrupt request is generated on a loss of RTC external reference clock. 1 Generate a reset request on a loss of RTC external reference clock 6 LOLRE 0 Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. 1 Generate a reset request on a PLL loss of lock indication. 5 CME1 Clock Monitor Enable1 Enables the loss of clock monitoring circuit for the output of the RTC external reference clock. The LOCRE1 bit will determine whether an interrupt or a reset request is generated following a loss of RTC clock indication. The CME1 bit should be set to a logic 1 when the MCG is in an operational mode that uses the RTC as its external reference clock or if the RTC is operational. CME1 bit must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur when in Stop mode. CME1 should also be set to a logic 0 before entering VLPR or VLPW power modes. 0 External clock monitor is disabled for RTC clock. 1 External clock monitor is enabled for RTC clock. 4–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 581 General Business Information

Page 582

MCG_C8 field descriptions (continued) Field Description 0 LOCS1 RTC Loss of Clock Status This bit indicates when a loss of clock has occurred. This bit is cleared by writing a logic 1 to it when set. 0 Loss of RTC has not occur. 1 Loss of RTC has occur 25.3.13 MCG Control 9 Register (MCG_C9) Address: 4006_4000h base + Eh offset = 4006_400Eh Bit 7 6 5 4 3 2 1 0 Read 0 0 Write Reset 0 0 0 0 0 0 0 0 MCG_C9 field descriptions Field Description 7–4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 25.3.14 MCG Control 10 Register (MCG_C10) Address: 4006_4000h base + Fh offset = 4006_400Fh Bit 7 6 5 4 3 2 1 0 Read 0 0 Write Reset 0 0 0 0 0 0 0 0 MCG_C10 field descriptions Field Description 7–4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 582 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 583

Functional Description 25.4.1 MCG mode state diagram The nine states of the MCG are shown in the following figure and are described in Table 25-18. The arrows indicate the permitted MCG mode transitions. FEE FEI Reset BLPI FBI FBE BLPE PBE PEE Stop Returns to the state that was active before the MCU entered Stop mode, unless a reset occurs while in Stop mode. Entered from any state when the MCU enters Stop mode Figure 25-16. MCG mode state diagram NOTE • During exits from LLS or VLPS when the MCG is in PEE mode, the MCG will reset to PBE clock mode and the C1[CLKS] and S[CLKST] will automatically be set to 2’b10. • If entering Normal Stop mode when the MCG is in PEE mode with C5[PLLSTEN]=0, the MCG will reset to PBE clock mode and C1[CLKS] and S[CLKST] will automatically be set to 2’b10. 25.4 Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 583 General Business Information

Page 584

25.4.1.1 MCG modes of operation The MCG operates in one of the following modes. Note The MCG restricts transitions between modes. For the permitted transitions, see Figure 25-16. Table 25-18. MCG modes of operation Mode Description FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following condtions occur: • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 1 • C6[PLLS] bit is written to 0 In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32 kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. In FEI mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN0] is set. FLL Engaged External (FEE) FLL engaged external (FEE) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 • C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz • C6[PLLS] bit is written to 0 In FEE mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the external reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the external reference frequency, as specified by C1[FRDIV] and C2[RANGE0]. See the C4[DMX32] bit description for more details. In FEE mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN0] is set. FLL Bypassed Internal (FBI) FLL bypassed internal (FBI) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 01 • C1[IREFS] bit is written to 1 • C6[PLLS] is written to 0 • C2[LP] is written to 0 In FBI mode, the MCGOUTCLK is derived either from the slow (32 kHz IRC) or fast (2 MHz IRC) internal reference clock, as selected by the C2[IRCS] bit. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the C2[IRCS] selected internal reference clock. The FLL clock (DCOCLK) is controlled by the slow internal reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. In FBI mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN0] is set. Table continues on the next page... Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 584 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 585

Table 25-18. MCG modes of operation (continued) Mode Description FLL Bypassed External (FBE) FLL bypassed external (FBE) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 10 • C1[IREFS] bit is written to 0 • C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz. • C6[PLLS] bit is written to 0 • C2[LP] is written to 0 In FBE mode, the MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the external reference clock. The FLL clock (DCOCLK) is controlled by the external reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the divided external reference frequency. See the C4[DMX32] bit description for more details. In FBI mode the PLL is disabled in a low-power state unless C5[PLLCLKEN0] is set. PLL Engaged External (PEE) PLL Engaged External (PEE) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 • C6[PLLS] bit is written to 1 In PEE mode, the MCGOUTCLK is derived from the PLL clock, which is controlled by the external reference clock. The PLL clock frequency locks to a multiplication factor, as specified by C6[VDIV0], times the external reference frequency, as specified by C5[PRDIV0]. The PLL's programmable reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low-power state. PLL Bypassed External (PBE) PLL Bypassed External (PBE) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 10 • C1[IREFS] bit is written to 0 • C6[PLLS] bit is written to 1 • C2[LP] bit is written to 0 In PBE mode, MCGOUTCLK is derived from the OSCSEL external reference clock; the PLL is operational, but its output clock is not used. This mode is useful to allow the PLL to acquire its target frequency while MCGOUTCLK is driven from the external reference clock. The PLL clock frequency locks to a multiplication factor, as specified by its [VDIV], times the PLL reference frequency, as specified by its [PRDIV]. In preparation for transition to PEE, the PLL's programmable reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low- power state. Table continues on the next page... Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 585 General Business Information

Page 586

Table 25-18. MCG modes of operation (continued) Mode Description Bypassed Low Power Internal (BLPI)1 Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 01 • C1[IREFS] bit is written to 1 • C6[PLLS] bit is written to 0 • C2[LP] bit is written to 1 In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled and PLL is disabled even if the C5[PLLCLKEN0] is set to 1. Bypassed Low Power External (BLPE) Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 10 • C1[IREFS] bit is written to 0 • C2[LP] bit is written to 1 In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is disabled and PLL is disabled even if the C5[PLLCLKEN0] is set to 1. Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static except in the following case: MCGPLLCLK is active in Normal Stop mode when PLLSTEN=1 MCGIRCLK is active in Normal Stop mode when all the following conditions become true: • C1[IRCLKEN] = 1 • C1[IREFSTEN] = 1 NOTE: • When entering Low Power Stop modes (LLS or VLPS) from PEE mode, on exit the MCG clock mode is forced to PBE clock mode. C1[CLKS] and S[CLKST] will be configured to 2’b10 and S[LOCK0] bit will be cleared without setting S[LOLS0]. • When entering Normal Stop mode from PEE mode and if C5[PLLSTEN0]=0, on exit the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will be configured to 2’b10 and S[LOCK0] bit will clear without setting S[LOLS0]. If C5[PLLSTEN0]=1, the S[LOCK0] bit will not get cleared and on exit the MCG will continue to run in PEE mode. 1. If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the Fast IRC clock selected (C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG clock mode switch to a non low power clock mode must be avoided. NOTE For the chip-specific modes of operation, see the power management chapter of this MCU. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 586 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 587

25.4.1.2 MCG mode switching The C1[IREFS] bit can be changed at any time, but the actual switch to the newly selected reference clocks is shown by the S[IREFST] bit. When switching between engaged internal and engaged external modes, the FLL will begin locking again after the switch is completed. The C1[CLKS] bits can also be changed at any time, but the actual switch to the newly selected clock is shown by the S[CLKST] bits. If the newly selected clock is not available, the previous clock will remain selected. The C4[DRST_DRS] write bits can be changed at any time except when C2[LP] bit is 1. If the C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or FLL engaged external (FEE), the MCGOUTCLK will switch to the new selected DCO range within three clocks of the selected DCO clock. After switching to the new DCO, the FLL remains unlocked for several reference cycles. DCO startup time is equal to the FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the C4[DRST_DRS] read bits. 25.4.2 Low Power Bit Usage The C2[LP] bit is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used. The C4[DRST_DRS] can not be written while C2[LP] bit is 1. However, in some applications, it may be desirable to enable the FLL or PLL and allow it to lock for maximum accuracy before switching to an engaged mode. Do this by writing C2[LP] to 0. 25.4.3 MCG Internal Reference Clocks This module supports two internal reference clocks with nominal frequencies of 32 kHz (slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz. 25.4.3.1 MCG Internal Reference Clock The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other on- chip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is driven by either the fast internal reference clock (4 MHz IRC which can be divided down by the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS clock frequency can be re-targeted by trimming the period of its IRCS selected internal Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 587 General Business Information

Page 588

reference clock. This can be done by writing a new trim value to the C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is selected or by writing a new trim value to the C4[FCTRIM] bits when the fast IRC clock is selected. The internal reference clock period is proportional to the trim value written. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM] (if C2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the MCGOUTCLK frequency if the MCG is in FEI mode. Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and C1[IREFSTEN], otherwise this clock is disabled in Stop mode. 25.4.4 External Reference Clock The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL or PLL. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support. If any of the CME bits are asserted the slow internal reference clock is enabled along with the enabled external clock monitor. For the case when C6[CME0]=1, a loss of clock is detected if the OSC0 external reference falls below a minimum frequency (floc_high or floc_low depending on C2[RANGE0]). For the case when C8[CME1]=1, a loss of clock is detected if the RTC external reference falls below a minimum frequency (floc_low). All clock monitors must be disabled before VLPR or VLPW power modes are entered. Upon detect of a loss of clock event, the MCU generates a system reset if the respective LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG generates a LOCS interrupt request. In the case where a OSC0 loss of clock is detected, the PLL LOCK status bit is cleared if the OSC clock that is lost was selected as the PLL reference clock. 25.4.5 MCG Fixed frequency clock The MCG Fixed Frequency Clock (MCGFFCLK) provides a fixed frequency clock source for other on-chip peripherals; see the block diagram. This clock is driven by either the slow clock from the internal reference clock generator or the external reference clock from the Crystal Oscillator, divided by the FLL reference clock divider. The source of MCGFFCLK is selected by C1[IREFS]. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 588 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 589

This clock is synchronized to the peripheral bus clock and is valid only when its frequency is not more than 1/8 of the MCGOUTCLK frequency. When it is not valid, it is disabled and held high. The MCGFFCLK is not available when the MCG is in BLPI mode. This clock is also disabled in Stop mode. The FLL reference clock must be set within the valid frequency range for the MCGFFCLK. 25.4.6 MCG PLL clock The MCG PLL Clock (MCGPLLCLK) is available depending on the device's configuration of the MCG module. For more details, see the clock distribution chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK0] is set. 25.4.7 MCG Auto TRIM (ATM) The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz IRC and ATC[ATMS]=1 selects the 4 MHz IRC). If 4 MHz IRC is selected for the ATM, a divide by 128 is enabled to divide down the 4 MHz IRC to a range of 31.250 kHz. When MCG ATM is enabled by writing ATC[ATME] bit to 1, The ATM machine will start auto trimming the selected IRC clock. During the autotrim process, ATC[ATME] will remain asserted and will deassert after ATM is completed or an abort occurs. The MCG ATM is aborted if a write to any of the following control registers is detected : C1, C3, C4, or ATC or if Stop mode is entered. If an abort occurs, ATC[ATMF] fail flag is asserted. The ATM machine uses the bus clock as the external reference clock to perform the IRC auto-trim. Therefore, it is required that the MCG is configured in a clock mode where the reference clock used to generate the system clock is the external reference clock such as FBE clock mode. The MCG must not be configured in a clock mode where selected IRC ATM clock is used to generate the system clock. The bus clock is also required to be running with in the range of 8–16 MHz. To perform the ATM on the selected IRC, the ATM machine uses the successive approximation technique to adjust the IRC trim bits to generate the desired IRC trimmed frequency. The ATM SARs each of the ATM IRC trim bits starting with the MSB. For each trim bit test, the ATM uses a pulse that is generated by the ATM selected IRC clock to enable a counter that counts number of ATM external clocks. At end of each trim bit, Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 589 General Business Information

Page 590

the ATM external counter value is compared to the ATCV[15:0] register value. Based on the comparison result, the ATM trim bit under test will get cleared or stay asserted. This is done until all trim bits have been tested by ATM SAR machine. Before the ATM can be enabled, the ATM expected count needs to be derived and stored into the ATCV register. The ATCV expected count is derived based on the required target Internal Reference Clock (IRC) frequency, and the frequency of the external reference clock using the following formula: ATCV • Fr = Target Internal Reference Clock (IRC) Trimmed Frequency • Fe = External Clock Frequency If the auto trim is being performed on the 4 MHz IRC, the calculated expected count value must be multiplied by 128 before storing it in the ATCV register. Therefore, the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula. (128) 25.5 Initialization / Application information This section describes how to initialize and configure the MCG module in an application. The following sections include examples on how to initialize the MCG and properly switch between the various available modes. 25.5.1 MCG module initialization sequence The MCG comes out of reset configured for FEI mode. The internal reference will stabilize in tirefsts microseconds before the FLL can acquire lock. As soon as the internal reference is stable, the FLL will acquire lock in tfll_acquire milliseconds. 25.5.1.1 Initializing the MCG Because the MCG comes out of reset in FEI mode, the only MCG modes that can be directly switched to upon reset are FEE, FBE, and FBI modes (see Figure 25-16). Reaching any of the other modes requires first configuring the MCG for one of these three intermediate modes. Care must be taken to check relevant status bits in the MCG status register reflecting all configuration changes within each mode. Initialization / Application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 590 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 591

To change from FEI mode to FEE or FBE modes, follow this procedure:

Enable the external clock source by setting the appropriate bits in C2 register.
Write to C1 register to select the clock mode. • If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit to switch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that the output of the FLL is selected as the system clock source. • If entering FBE, clear the C1[IREFS] bit to switch to the external reference and change the C1[CLKS] bits to 2'b10 so that the external reference clock is selected as the system clock source. The C1[FRDIV] bits should also be set appropriately here according to the external reference frequency to keep the FLL reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is bypassed, it is still on in FBE mode. • The internal reference can optionally be kept running by setting the C1[IRCLKEN] bit. This is useful if the application will switch back and forth between internal and external modes. For minimum power consumption, leave the internal reference disabled while in an external clock mode.
Once the proper configuration bits have been set, wait for the affected bits in the MCG status register to be changed appropriately, reflecting that the MCG has moved into the proper mode. • If the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and C2[EREFS0] was also set in step 1, wait here for S[OSCINIT0] bit to become set indicating that the external clock source has finished its initialization cycles and stabilized. • If in FEE mode, check to make sure the S[IREFST] bit is cleared before moving on. • If in FBE mode, check to make sure the S[IREFST] bit is cleared and S[CLKST] bits have changed to 2'b10 indicating the external reference clock has been appropriately selected. Although the FLL is bypassed, it is still on in FBE mode.
Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency range. • By default, with C4[DMX32] cleared to 0, the FLL multiplier for the DCO output is 640. For greater flexibility, if a mid-low-range FLL multiplier of 1280 is desired instead, set C4[DRST_DRS] bits to 2'b01 for a DCO output frequency of 40 MHz. If a mid high-range FLL multiplier of 1920 is desired instead, set the Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 591 General Business Information

Page 592

C4[DRST_DRS] bits to 2'b10 for a DCO output frequency of 60 MHz. If a high- range FLL multiplier of 2560 is desired instead, set the C4[DRST_DRS] bits to 2'b11 for a DCO output frequency of 80 MHz. • When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz. • When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 MHz. • When using a 32.768 kHz external reference, if the maximum mid high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b10 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2197 will be 72 MHz. • When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b11 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2929 will be 96 MHz. 5. Wait for the FLL lock time to guarantee FLL is running at new C4[DRST_DRS] and C4[DMX32] programmed frequency. To change from FEI clock mode to FBI clock mode, follow this procedure:

Change C1[CLKS] bits in C1 register to 2'b01 so that the internal reference clock is selected as the system clock source.
Wait for S[CLKST] bits in the MCG status register to change to 2'b01, indicating that the internal reference clock has been appropriately selected.
Write to the C2 register to determine the IRCS output (IRCSCLK) frequency range. • By default, with C2[IRCS] cleared to 0, the IRCS selected output clock is the slow internal reference clock (32 kHz IRC). If the faster IRC is desired, set C2[IRCS] bit to 1 for a IRCS clock derived from the 4 MHz IRC source. Initialization / Application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 592 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 593

25.5.2 Using a 32.768 kHz reference In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range. If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 MHz at mid-low-range. If C4[DRST_DRS] bits are set to 2'b10, the multiplication factor is set to 1920, and the resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89 MHz at high-range. In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the microcontroller system clock out of specification and damage the part. 25.5.3 MCG mode switching When switching between operational modes of the MCG, certain configuration bits must be changed in order to properly move from one mode to another. Each time any of these bits are changed (C6[PLLS], C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS0]), the corresponding bits in the MCG status register (PLLST, IREFST, CLKST, IRCST, or OSCINIT) must be checked before moving on in the application software. Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV] and C5[PRDIV0]) is set properly for the mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, C5[PRDIV0] must be set to 5'b000 (divide-by-1) or 5'b001 (divide -by-2) to divide the external reference down to the required frequency between 2 and 4 MHz. In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits. Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1. The table below shows MCGOUTCLK frequency calculations using C1[FRDIV], C5[PRDIV0], and C6[VDIV0] settings for each clock mode. Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 593 General Business Information

Page 594

Table 25-19. MCGOUTCLK Frequency Calculation Options Clock Mode fMCGOUTCLK1 Note FEI (FLL engaged internal) (fint * F) Typical fMCGOUTCLK = 20 MHz immediately after reset. FEE (FLL engaged external) (fext / FLL_R) *F fext / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBE (FLL bypassed external) fext fext / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBI (FLL bypassed internal) fint Typical fint = 32 kHz PEE (PLL engaged external) (fext / PLL_R) * M fext / PLL_R must be in the range of 2 – 4 MHz PBE (PLL bypassed external) fext fext / PLL_R must be in the range of 2 – 4 MHz BLPI (Bypassed low power internal) fint BLPE (Bypassed low power external) fext 1. FLL_R is the reference divider selected by the C1[FRDIV] bits, PLL_R is the reference divider selected by C5[PRDIV0] bits, F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits, and M is the multiplier selected by C6[VDIV0] bits. This section will include three mode switching examples using an 4 MHz external crystal. If using an external clock source less than 2 MHz, the MCG must not be configured for any of the PLL modes (PEE and PBE). 25.5.3.1 Example 1: Moving from FEI to PEE mode: External Crystal = 4 MHz, MCGOUTCLK frequency = 48 MHz In this example, the MCG will move through the proper operational modes from FEI to PEE to achieve 48 MHz MCGOUTCLK frequency from 4 MHz external crystal reference. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence.

First, FEI must transition to FBE mode: a. C2 = 0x1C • C2[RANGE0] set to 2'b01 because the frequency of 4 MHz is within the high frequency range. • C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation. • C2[EREFS0] set to 1, because a crystal is being used. b. C1 = 0x90 Initialization / Application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 594 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 595

• C1[CLKS] set to 2'b10 to select external reference clock as system clock source • C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL • C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator. c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by C2[EREFS0] has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference is the current source for the reference clock. e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK. 2. Then configure C5[PRDIV0] to generate correct PLL reference frequency. a. C5 = 0x01 • C5[PRDIV0] set to 5'b001, or divide-by-2 resulting in a pll reference frequency of 4 MHz/2 = 2 MHz. 3. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to PBE mode: a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1. b. BLPE/PBE: C6 = 0x40 • C6[PLLS] set to 1, selects the PLL. At this time, with a C1[PRDIV] value of 2'b001, the PLL reference divider is 2 (see PLL External Reference Divide Factor table), resulting in a reference frequency of 4 MHz/ 2 = 2 MHz. In BLPE mode, changing the C6[PLLS] bit only prepares the MCG for PLL usage in PBE mode. • C6[VDIV0] set to 5'b0000, or multiply-by-24 because 2 MHz reference * 24 = 48 MHz. In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is disabled. Changing them only sets up the multiply value for PLL usage in PBE mode. c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to PBE mode. d. PBE: Loop until S[PLLST] is set, indicating that the current source for the PLLS clock is the PLL. Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 595 General Business Information

Page 596

e. PBE: Then loop until S[LOCK0] is set, indicating that the PLL has acquired lock. 4. Lastly, PBE mode transitions into PEE mode: a. C1 = 0x10 • C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock source. b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. • Now, with PRDIV0 of divide-by-2, and C6[VDIV0] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz. Initialization / Application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 596 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 597

C2 = 0x1C (S[LP]=0) IN BLPE MODE ? C6 = 0x40 C2 = 0x1C START IN FEI MODE NO NO NO NO NO NO NO NO YES YES YES YES YES YES YES YES CHECK C1 = 0x90 CHECK CHECK ENTER BLPE MODE ? C2 = 0x1E (C2[LP] = 1) CHECK CHECK C1 = 0x10 CHECK CONTINUE IN PEE MODE S[PLLST] = 1? S[LOCK] = 1? S[CLKST] = %10? S[CLKST] = %11? (S[LP]=1) S[IREFST] = 0? S[OSCINIT] = 1? C5 = 0x01 (C5[VDIV] = 1) Figure 25-17. Flowchart of FEI to PEE mode transition using an 4 MHz crystal Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 597 General Business Information

Page 598

25.5.3.2 Example 2: Moving from PEE to BLPI mode: MCGOUTCLK frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence.

First, PEE must transition to PBE mode: a. C1 = 0x90 • C1[CLKS] set to 2'b10 to switch the system clock source to the external reference clock. b. Loop until S[CLKST] are 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK.
Then, PBE must transition either directly to FBE mode or first through BLPE mode and then to FBE mode: a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1. b. BLPE/FBE: C6 = 0x00 • C6[PLLS] clear to 0 to select the FLL. At this time, with C1[FRDIV] value of 3'b010, the FLL divider is set to 128, resulting in a reference frequency of 4 MHz / 128 = 31.25 kHz. If C1[FRDIV] was not previously set to 3'b010 (necessary to achieve required 31.25–39.06 kHz FLL reference frequency with an 4 MHz external source frequency), it must be changed prior to clearing C6[PLLS] bit. In BLPE mode,changing this bit only prepares the MCG for FLL usage in FBE mode. With C6[PLLS] = 0, the C6[VDIV0] value does not matter. c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to FBE mode. d. FBE: Loop until S[PLLST] is cleared, indicating that the current source for the PLLS clock is the FLL.
Next, FBE mode transitions into FBI mode: a. C1 = 0x54 • C1[CLKS] set to 2'b01 to switch the system clock to the internal reference clock. Initialization / Application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 598 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 599

• C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. • C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source. c. Loop until S[CLKST] are 2'b01, indicating that the internal reference clock is selected to feed MCGOUTCLK. 4. Lastly, FBI transitions into BLPI mode. a. C2 = 0x02 • C2[LP] is 1 • C2[RANGE0], C2[HGO0], C2[EREFS0], C1[IRCLKEN], and C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point. Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 599 General Business Information

Page 600

START IN PEE MODE C1 = 0x90 CHECK S[CLKST] = %10 ? NO NO NO NO YES C2 = 0x02 CONTINUE IN BLPI MODE YES YES CHECK S[PLLST] = 0? C1 = 0x54 CHECK S[IREFST] = 0? CHECK S[CLKST] = %01? YES NO YES (C2[LP] = 1) C6 = 0x00 IN BLPE MODE ? IN BLPE MODE ? NO YES C2 = 0x1C (C2[LP] = 0) C2 = 0x1E ENTER BLPE MODE ? (C2[LP]=1) Figure 25-18. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal Initialization / Application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 600 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 601

25.5.3.3 Example 3: Moving from BLPI to FEE mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence.

First, BLPI must transition to FBI mode. a. C2 = 0x00 • C2[LP] is 0
Next, FBI will transition to FEE mode. a. C2 = 0x1C • C2[RANGE0] set to 2'b01 because the frequency of 4 MHz is within the high frequency range. • C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation. • C2[EREFS0] set to 1, because a crystal is being used. b. C1 = 0x10 • C1[CLKS] set to 2'b00 to select the output of the FLL as system clock source. • C1[FRDIV] remain at 3'b010, or divide-by-128 for a reference of 4 MHz / 128 = 31.25 kHz. • C1[IREFS] cleared to 0, selecting the external reference clock. c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by the C2[EREFS0] bit has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference clock is the current source for the reference clock. e. Loop until S[CLKST] are 2'b00, indicating that the output of the FLL is selected to feed MCGOUTCLK. f. Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 640, MCGOUTCLK = 31.25 kHz * 640 / 1 = 20 MHz. g. At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL Chapter 25 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 601 General Business Information

Page 602

multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. C1 = 0x10 C2 = 0x00 C2 = 0x1C CHECK CHECK CHECK S[OSCINIT] = 1 ? CONTINUE IN FEE MODE NO NO NO YES YES YES START IN BLPI MODE S[IREFST] = 0? S[CLKST] = %00? Figure 25-19. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal Initialization / Application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 602 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 603

Chapter 26 Oscillator (OSC) 26.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 26.2 Features and Modes Key features of the module are: • Supports 32 kHz crystals (Low Range mode) • Supports 3–8 MHz, 8–32 MHz crystals and resonators (High Range mode) • Automatic Gain Control (AGC) to optimize power consumption in high frequency ranges 3–8 MHz, 8–32 MHz using low-power mode • High gain option in frequency ranges: 32 kHz, 3–8 MHz, and 8–32 MHz • Voltage and frequency filtering to guarantee clock frequency and stability • Optionally external input bypass clock from EXTAL signal directly • One clock for MCU clock system • Two clocks for on-chip peripherals that can work in Stop modes K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 603 General Business Information

Page 604

Functional Description describes the module's operation in more detail. 26.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode. OSCERCLK and OSC32KCLK can work in low power modes. For the clock source assignments, refer to the clock distribution information of this MCU. Refer to the chip configuration chapter for the external reference clock source in this MCU. The following figure shows the block diagram of the OSC module. XTAL EXTAL XTL_CLK CNT_DONE_4096 OSC_CLK_OUT Mux 4096 Counter OSC Clock Enable STOP OSC clock selection OSCERCLK ERCLKEN OSCCLK Range selections Low Power config OSC32KCLK Oscillator Circuits <0A>’ <20>0 Control and Decoding logic ERCLKEN EREFSTEN OSC_EN Figure 26-1. OSC Module Block Diagram 26.4 OSC Signal Descriptions The following table shows the user-accessible signals available for the OSC module. Refer to signal multiplexing information for this MCU for more details. Block Diagram K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 604 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 605

Table 26-1. OSC Signal Descriptions Signal Description I/O EXTAL External clock/Oscillator input I XTAL Oscillator output O 26.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself. In the other oscillator modes, load capacitors (Cx, Cy) and feedback resistor (RF) are required. The following table shows all possible connections. Table 26-2. External Caystal/Resonator Connections Oscillator Mode Connections Low-frequency (32 kHz), low-power Connection 1 Low-frequency (32 kHz), high-gain Connection 2/Connection 31 High-frequency (3~~32 MHz), low-power Connection 1/Connection 32,2 High-frequency (3~~32 MHz), high-gain Connection 2/Connection 32 1. When the load capacitors (Cx, Cy) are greater than 30 pF, use Connection 3. 2. With the low-power mode, the oscillator has the internal feedback resistor RF. Therefore, the feedback resistor must not be externally with the Connection 3. OSC EXTAL Crystal or Resonator VSS XTAL Figure 26-2. Crystal/Ceramic Resonator Connections - Connection 1 Chapter 26 Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 605 General Business Information

Page 606

OSC VSS RF Crystal or Resonator XTAL EXTAL Figure 26-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. OSC VSS Cx Cy RF Crystal or Resonator XTAL EXTAL Figure 26-4. Crystal/Ceramic Resonator Connections - Connection 3 26.6 External Clock Connections In external clock mode, the pins can be connected as shown below. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. External Clock Connections K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 606 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 607

OSC VSS Clock Input I/O XTAL EXTAL Figure 26-5. External Clock Connections 26.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. OSC Memory Map/Register Definition OSC memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4006_5000 OSC Control Register (OSC_CR) 8 R/W 000h 26.71.1/ 607 26.71.1 OSC Control Register (OSC_CR) NOTE After OSC is enabled and starts generating the clocks, the configurations such as low power and frequency range, must not be changed. Address: 4006_5000h base + 0h offset = 4006_5000h Bit 7 6 5 4 3 2 1 0 Read ERCLKEN 0 EREFSTEN 0 SC2P SC4P SC8P SC16P Write Reset 0 0 0 0 0 0 0 0 26.7.1 Chapter 26 Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 607 General Business Information

Page 608

OSC_CR field descriptions Field Description 7 ERCLKEN External Reference Enable Enables external reference clock (OSCERCLK). 0 External reference clock is inactive. 1 External reference clock is enabled. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 EREFSTEN External Reference Stop Enable Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. 0 External reference clock is disabled in Stop mode. 1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load. 0 Disable the selection. 1 Add 2 pF capacitor to the oscillator load. 2 SC4P Oscillator 4 pF Capacitor Load Configure Configures the oscillator load. 0 Disable the selection. 1 Add 4 pF capacitor to the oscillator load. 1 SC8P Oscillator 8 pF Capacitor Load Configure Configures the oscillator load. 0 Disable the selection. 1 Add 8 pF capacitor to the oscillator load. 0 SC16P Oscillator 16 pF Capacitor Load Configure Configures the oscillator load. 0 Disable the selection. 1 Add 16 pF capacitor to the oscillator load. 26.8 Functional Description This following sections provide functional details of the module. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 608 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 609

26.8.1 OSC Module States The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. Stable Off OSCCLK CNT_DONE_4096 Start-Up OSCCLK requested External Clock Mode Oscillator ON, Stable Oscillator OFF Oscillator ON, not yet stable Oscillator ON OSC_CLK_OUT = Static OSC_CLK_OUT = Static OSC_CLK_OUT = EXTAL OSC_CLK_OUT = XTL_CLK not requested && Select OSC internal clock OSCCLK requested && Select clock from EXTAL signal Figure 26-7. OSC Module State Diagram NOTE XTL_CLK is the clock generated internally from OSC circuits. 26.8.1.1 Off The OSC enters the Off state when the system does not require OSC clocks. Upon entering this state, XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad by clearing the external reference clock selection bit. For details regarding the external reference clock source in this MCU, refer to the chip configuration chapter. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. Chapter 26 Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 609 General Business Information

Page 610

26.8.1.2 Oscillator Start-Up The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized. When the oscillation amplitude becomes large enough to pass through the input buffer, XTL_CLK begins clocking the counter. When the counter reaches 4096 cycles of XTL_CLK, the oscillator is considered stable and XTL_CLK is passed to the output clock OSC_CLK_OUT. 26.8.1.3 Oscillator Stable The OSC enters stable state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit and the counter reaches 4096 cycles of XTL_CLK (when CNT_DONE_4096 is high). In this state, the OSC module is producing a stable output clock on OSC_CLK_OUT. Its frequency is determined by the external components being used. 26.8.1.4 External Clock Mode The OSC enters external clock state when it is enabled and external reference clock selection bit is cleared. For details regarding external reference clock source in this MCU, refer to the chip configuration chapter. In this state, the OSC module is set to buffer (with hysteresis) a clock from EXTAL onto the OSC_CLK_OUT. Its frequency is determined by the external clock being supplied. 26.8.2 OSC Module Modes The OSC is a Pierce-type oscillator that supports external crystals or resonators operating over the frequency ranges shown in Table 26-5. These modes assume the following conditions: OSC is enabled to generate clocks (OSC_EN=1), configured to generate clocks internally (MCG_C2[EREFS] = 1), and some or one of the other peripherals (MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 610 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 611

Table 26-5. Oscillator Modes Mode Frequency Range Low-frequency, high-gain fosc_lo (1 kHz) up to fosc_lo (32.768 kHz) Low-frequency, low-power (VLP) High-frequency mode1, high-gain fosc_hi_1 (3 MHz) up to fosc_hi_1 (8 MHz) High-frequency mode1, low-power High-frequency mode2, high-gain fosc_hi_2 (8 MHz) up to fosc_hi_2 (32 MHz) High-frequency mode2, low-power NOTE For information about low power modes of operation used in this chip and their alignment with some OSC modes, refer to the chip's Power Management details. 26.8.2.1 Low-Frequency, High-Gain Mode In Low-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. The oscillator input buffer in this mode is single-ended. It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used. 26.8.2.2 Low-Frequency, Low-Power Mode In low-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. In this mode, the amplifier inputs, gain-control input, and input buffer input are all capacitively coupled for leakage tolerance (not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. Chapter 26 Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 611 General Business Information

Page 612

26.8.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used. 26.8.2.4 High-Frequency, Low-Power Mode In high-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. In this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. The oscillator input buffer in this mode is differential. It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. 26.8.3 Counter The oscillator output clock (OSC_CLK_OUT) is gated off until the counter has detected 4096 cycles of its input clock (XTL_CLK). After 4096 cycles are completed, the counter passes XTL_CLK onto OSC_CLK_OUT. This counting time-out is used to guarantee output clock stability. 26.8.4 Reference Clock Pin Requirements The OSC module requires use of both the EXTAL and XTAL pins to generate an output clock in Oscillator mode, but requires only the EXTAL pin in External clock mode. The EXTAL and XTAL pins are available for I/O. For the implementation of these pins on this device, refer to the Signal Multiplexing chapter. 26.9 Reset There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. Reset K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 612 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 613

26.10 Low Power Modes Operation When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 26.11 Interrupts The OSC module does not generate any interrupts. Chapter 26 Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 613 General Business Information

Page 614

Interrupts K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 614 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 615

Chapter 27 RTC Oscillator 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The RTC oscillator module provides the clock source for the RTC. The RTC oscillator module, in conjunction with an external crystal, generates a reference clock for the RTC. 27.1.1 Features and Modes The key features of the RTC oscillator are as follows: • Supports 32 kHz crystals with very low power • Consists of internal feed back resistor • Consists of internal programmable capacitors as the Cload of the oscillator • Automatic Gain Control (AGC) to optimize power consumption The RTC oscillator operations are described in detail in Functional Description . 27.1.2 Block Diagram The following is the block diagram of the RTC oscillator. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 615 General Business Information

Page 616

gm control clk out for RTC PAD PAD XTAL32 C2 Amplitude EXTAL32 Rf C1 detector Figure 27-1. RTC Oscillator Block Diagram 27.2 RTC Signal Descriptions The following table shows the user-accessible signals available for the RTC oscillator. See the chip-level specification to find out which signals are actually connected to the external pins. Table 27-1. RTC Signal Descriptions Signal Description I/O EXTAL32 Oscillator Input I XTAL32 Oscillator Output O 27.2.1 EXTAL32 — Oscillator Input This signal is the analog input of the RTC oscillator. 27.2.2 XTAL32 — Oscillator Output This signal is the analog output of the RTC oscillator module. RTC Signal Descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 616 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 617

27.3 External Crystal Connections The connections with a crystal is shown in the following figure. External load capacitors and feedback resistor are not required. RTC Oscillator Module EXTAL32 Crystal or Resonator XTAL32 VSS Figure 27-2. Crystal Connections 27.4 Memory Map/Register Descriptions RTC oscillator control bits are part of the RTC registers. Refer to RTC_CR for more details. 27.5 Functional Description As shown in Figure 27-1, the module includes an amplifier which supplies the negative resistor for the RTC oscillator. The gain of the amplifier is controlled by the amplitude detector, which optimizes the power consumption. A schmitt trigger is used to translate the sine-wave generated by this oscillator to a pulse clock out, which is a reference clock for the RTC digital core. The oscillator includes an internal feedback resistor of approximately 100 MΩ between EXTAL32 and XTAL32. In addition, there are two programmable capacitors with this oscillator, which can be used as the Cload of the oscillator. The programmable range is from 0pF to 30pF. Chapter 27 RTC Oscillator K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 617 General Business Information

Page 618

27.6 Reset Overview There is no reset state associated with the RTC oscillator. 27.7 Interrupts The RTC oscillator does not generate any interrupts. Reset Overview K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 618 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 619

Chapter 28 Flash Memory Controller (FMC) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The Flash Memory Controller (FMC) is a memory acceleration unit that provides: • an interface between the device and the dual-bank nonvolatile memory. Bank 0 consists of program flash memory, and bank 1 consists of FlexNVM. • buffers that can accelerate flash memory and FlexNVM data transfers. 28.1.1 Overview The Flash Memory Controller manages the interface between the device and the dual- bank flash memory. The FMC receives status information detailing the configuration of the memory and uses this information to ensure a proper interface. The following table shows the supported read/write operations. Flash memory type Read Write Program flash memory 8-bit, 16-bit, and 32-bit reads —1 FlexNVM used as Data flash memory 8-bit, 16-bit, and 32-bit reads —1 FlexNVM and FlexRAM used as EEPROM 8-bit, 16-bit, and 32-bit reads 8-bit, 16-bit, and 32-bit writes 1. A write operation to program flash memory or to FlexNVM used as data flash memory results in a bus error. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 619 General Business Information

Page 620

In addition, for bank 0 and bank 1, the FMC provides three separate mechanisms for accelerating the interface between the device and the flash memory. A 64-bit speculation buffer can prefetch the next 64-bit flash memory location, and both a 4-way, 8-set cache and a single-entry 64-bit buffer can store previously accessed flash memory or FlexNVM data for quick access times. 28.1.2 Features The FMC's features include: • Interface between the device and the dual-bank flash memory and FlexMemory: • 8-bit, 16-bit, and 32-bit read operations to program flash memory and FlexNVM used as data flash memory. • 8-bit, 16-bit, and 32-bit read and write operations to FlexNVM and FlexRAM used as EEPROM. • For bank 0 and bank 1: Read accesses to consecutive 32-bit spaces in memory return the second read data with no wait states. The memory returns 64 bits via the 32-bit bus access. • Crossbar master access protection for setting no access, read-only access, write- only access, or read/write access for each crossbar master. • For bank 0 and bank 1: Acceleration of data transfer from program flash memory and FlexMemory to the device: • 64-bit prefetch speculation buffer with controls for instruction/data access per master and bank • 4-way, 8-set, 64-bit line size cache for a total of thirty-two 64-bit entries with controls for replacement algorithm and lock per way for each bank • Single-entry buffer with enable per bank • Invalidation control for the speculation buffer and the single-entry buffer 28.2 Modes of operation The FMC only operates when the device accesses the flash memory or FlexMemory. In terms of device power modes, the FMC only operates in run and wait modes, including VLPR and VLPW modes. For any device power mode where the flash memory or FlexMemory cannot be accessed, the FMC is disabled. Modes of operation K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 620 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 621

28.3 External signal description The FMC has no external signals. 28.4 Memory map and register descriptions The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings while a flash access is in progress can lead to non-deterministic behavior. Table 28-2. FMC register access Registers Read access Write access Mode Length Mode Length Control registers: PFAPR, PFB0CR, PFB1CR Supervisor (privileged) mode or user mode 32 bits Supervisor (privileged) mode only 32 bits Cache registers Supervisor (privileged) mode or user mode 32 bits Supervisor (privileged) mode only 32 bits NOTE Accesses to unimplemented registers within the FMC's 4 KB address space return a bus error. The cache entries, both data and tag/valid, can be read at any time. NOTE System software is required to maintain memory coherence when any segment of the flash cache is programmed. For example, all buffer data associated with the reprogrammed flash should be invalidated. Accordingly, cache program visible writes must occur after a programming or erase event is completed and before the new memory image is accessed. Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 621 General Business Information

Page 622

The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. The following table elaborates on the tag/valid and data entries. Table 28-3. Program visible cache registers Cache storage Based at offset Contents of 32-bit read Nomenclature Nomenclature example Tag 100h 13'h0, tag[18:6], 5'h0, valid In TAGVDWxSy, x denotes the way and y denotes the set. TAGVDW2S0 is the 13-bit tag and 1-bit valid for cache entry way 2, set 0. Data 200h Upper or lower longword of data In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. DATAW1S0U represents bits [63:32] of data entry way 1, set 0, and DATAW1S0L represents bits [31:0] of data entry way 1, set 0. FMC memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F000 Flash Access Protection Register (FMC_PFAPR) 32 R/W 00_F800 _3FF8 _003Fh 28.4.1/627 4001_F004 Flash Bank 0 Control Register (FMC_PFB0CR) 32 R/W 3002_001F _3002_001Fh 28.4.2/630 4001_F008 Flash Bank 1 Control Register (FMC_PFB1CR) 32 R/W 3002_001F _3002_001Fh 28.4.3/633 4001_F100 Cache Tag Storage (FMC_TAGVDW0S0) 32 R/W 0_0000 _0000h 28.4.4/635 4001_F104 Cache Tag Storage (FMC_TAGVDW0S1) 32 R/W 0_0000 _0000h 28.4.4/635 4001_F108 Cache Tag Storage (FMC_TAGVDW0S2) 32 R/W 0_0000 _0000h 28.4.4/635 4001_F10C Cache Tag Storage (FMC_TAGVDW0S3) 32 R/W 0_0000 _0000h 28.4.4/635 4001_F110 Cache Tag Storage (FMC_TAGVDW0S4) 32 R/W 0_0000 _0000h 28.4.4/635 4001_F114 Cache Tag Storage (FMC_TAGVDW0S5) 32 R/W 0_0000 _0000h 28.4.4/635 4001_F118 Cache Tag Storage (FMC_TAGVDW0S6) 32 R/W 0_0000 _0000h 28.4.4/635 4001_F11C Cache Tag Storage (FMC_TAGVDW0S7) 32 R/W 0_0000 _0000h 28.4.4/635 4001_F120 Cache Tag Storage (FMC_TAGVDW1S0) 32 R/W 0_0000 _0000h 28.4.5/636 4001_F124 Cache Tag Storage (FMC_TAGVDW1S1) 32 R/W 0_0000 _0000h 28.4.5/636 Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 622 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 623

FMC memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F128 Cache Tag Storage (FMC_TAGVDW1S2) 32 R/W 0_0000 _0000h 28.4.5/636 4001_F12C Cache Tag Storage (FMC_TAGVDW1S3) 32 R/W 0_0000 _0000h 28.4.5/636 4001_F130 Cache Tag Storage (FMC_TAGVDW1S4) 32 R/W 0_0000 _0000h 28.4.5/636 4001_F134 Cache Tag Storage (FMC_TAGVDW1S5) 32 R/W 0_0000 _0000h 28.4.5/636 4001_F138 Cache Tag Storage (FMC_TAGVDW1S6) 32 R/W 0_0000 _0000h 28.4.5/636 4001_F13C Cache Tag Storage (FMC_TAGVDW1S7) 32 R/W 0_0000 _0000h 28.4.5/636 4001_F140 Cache Tag Storage (FMC_TAGVDW2S0) 32 R/W 0_0000 _0000h 28.4.6/637 4001_F144 Cache Tag Storage (FMC_TAGVDW2S1) 32 R/W 0_0000 _0000h 28.4.6/637 4001_F148 Cache Tag Storage (FMC_TAGVDW2S2) 32 R/W 0_0000 _0000h 28.4.6/637 4001_F14C Cache Tag Storage (FMC_TAGVDW2S3) 32 R/W 0_0000 _0000h 28.4.6/637 4001_F150 Cache Tag Storage (FMC_TAGVDW2S4) 32 R/W 0_0000 _0000h 28.4.6/637 4001_F154 Cache Tag Storage (FMC_TAGVDW2S5) 32 R/W 0_0000 _0000h 28.4.6/637 4001_F158 Cache Tag Storage (FMC_TAGVDW2S6) 32 R/W 0_0000 _0000h 28.4.6/637 4001_F15C Cache Tag Storage (FMC_TAGVDW2S7) 32 R/W 0_0000 _0000h 28.4.6/637 4001_F160 Cache Tag Storage (FMC_TAGVDW3S0) 32 R/W 0_0000 _0000h 28.4.7/638 4001_F164 Cache Tag Storage (FMC_TAGVDW3S1) 32 R/W 0_0000 _0000h 28.4.7/638 4001_F168 Cache Tag Storage (FMC_TAGVDW3S2) 32 R/W 0_0000 _0000h 28.4.7/638 4001_F16C Cache Tag Storage (FMC_TAGVDW3S3) 32 R/W 0_0000 _0000h 28.4.7/638 4001_F170 Cache Tag Storage (FMC_TAGVDW3S4) 32 R/W 0_0000 _0000h 28.4.7/638 4001_F174 Cache Tag Storage (FMC_TAGVDW3S5) 32 R/W 0_0000 _0000h 28.4.7/638 4001_F178 Cache Tag Storage (FMC_TAGVDW3S6) 32 R/W 0_0000 _0000h 28.4.7/638 4001_F17C Cache Tag Storage (FMC_TAGVDW3S7) 32 R/W 0_0000 _0000h 28.4.7/638 Table continues on the next page... Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 623 General Business Information

Page 624

FMC memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F200 Cache Data Storage (upper word) (FMC_DATAW0S0U) 32 R/W 0_0000 _0000h 28.4.8/638 4001_F204 Cache Data Storage (lower word) (FMC_DATAW0S0L) 32 R/W 0_0000 _0000h 28.4.9/639 4001_F208 Cache Data Storage (upper word) (FMC_DATAW0S1U) 32 R/W 0_0000 _0000h 28.4.8/638 4001_F20C Cache Data Storage (lower word) (FMC_DATAW0S1L) 32 R/W 0_0000 _0000h 28.4.9/639 4001_F210 Cache Data Storage (upper word) (FMC_DATAW0S2U) 32 R/W 0_0000 _0000h 28.4.8/638 4001_F214 Cache Data Storage (lower word) (FMC_DATAW0S2L) 32 R/W 0_0000 _0000h 28.4.9/639 4001_F218 Cache Data Storage (upper word) (FMC_DATAW0S3U) 32 R/W 0_0000 _0000h 28.4.8/638 4001_F21C Cache Data Storage (lower word) (FMC_DATAW0S3L) 32 R/W 0_0000 _0000h 28.4.9/639 4001_F220 Cache Data Storage (upper word) (FMC_DATAW0S4U) 32 R/W 0_0000 _0000h 28.4.8/638 4001_F224 Cache Data Storage (lower word) (FMC_DATAW0S4L) 32 R/W 0_0000 _0000h 28.4.9/639 4001_F228 Cache Data Storage (upper word) (FMC_DATAW0S5U) 32 R/W 0_0000 _0000h 28.4.8/638 4001_F22C Cache Data Storage (lower word) (FMC_DATAW0S5L) 32 R/W 0_0000 _0000h 28.4.9/639 4001_F230 Cache Data Storage (upper word) (FMC_DATAW0S6U) 32 R/W 0_0000 _0000h 28.4.8/638 4001_F234 Cache Data Storage (lower word) (FMC_DATAW0S6L) 32 R/W 0_0000 _0000h 28.4.9/639 4001_F238 Cache Data Storage (upper word) (FMC_DATAW0S7U) 32 R/W 0_0000 _0000h 28.4.8/638 4001_F23C Cache Data Storage (lower word) (FMC_DATAW0S7L) 32 R/W 0_0000 _0000h 28.4.9/639 4001_F240 Cache Data Storage (upper word) (FMC_DATAW1S0U) 32 R/W 0_0000 _0000h 28.4.10/ 639 4001_F244 Cache Data Storage (lower word) (FMC_DATAW1S0L) 32 R/W 0_0000 _0000h 28.4.11/ 640 4001_F248 Cache Data Storage (upper word) (FMC_DATAW1S1U) 32 R/W 0_0000 _0000h 28.4.10/ 639 4001_F24C Cache Data Storage (lower word) (FMC_DATAW1S1L) 32 R/W 0_0000 _0000h 28.4.11/ 640 4001_F250 Cache Data Storage (upper word) (FMC_DATAW1S2U) 32 R/W 0_0000 _0000h 28.4.10/ 639 4001_F254 Cache Data Storage (lower word) (FMC_DATAW1S2L) 32 R/W 0_0000 _0000h 28.4.11/ 640 Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 624 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 625

FMC memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F258 Cache Data Storage (upper word) (FMC_DATAW1S3U) 32 R/W 0_0000 _0000h 28.4.10/ 639 4001_F25C Cache Data Storage (lower word) (FMC_DATAW1S3L) 32 R/W 0_0000 _0000h 28.4.11/ 640 4001_F260 Cache Data Storage (upper word) (FMC_DATAW1S4U) 32 R/W 0_0000 _0000h 28.4.10/ 639 4001_F264 Cache Data Storage (lower word) (FMC_DATAW1S4L) 32 R/W 0_0000 _0000h 28.4.11/ 640 4001_F268 Cache Data Storage (upper word) (FMC_DATAW1S5U) 32 R/W 0_0000 _0000h 28.4.10/ 639 4001_F26C Cache Data Storage (lower word) (FMC_DATAW1S5L) 32 R/W 0_0000 _0000h 28.4.11/ 640 4001_F270 Cache Data Storage (upper word) (FMC_DATAW1S6U) 32 R/W 0_0000 _0000h 28.4.10/ 639 4001_F274 Cache Data Storage (lower word) (FMC_DATAW1S6L) 32 R/W 0_0000 _0000h 28.4.11/ 640 4001_F278 Cache Data Storage (upper word) (FMC_DATAW1S7U) 32 R/W 0_0000 _0000h 28.4.10/ 639 4001_F27C Cache Data Storage (lower word) (FMC_DATAW1S7L) 32 R/W 0_0000 _0000h 28.4.11/ 640 4001_F280 Cache Data Storage (upper word) (FMC_DATAW2S0U) 32 R/W 0_0000 _0000h 28.4.12/ 640 4001_F284 Cache Data Storage (lower word) (FMC_DATAW2S0L) 32 R/W 0_0000 _0000h 28.4.13/ 641 4001_F288 Cache Data Storage (upper word) (FMC_DATAW2S1U) 32 R/W 0_0000 _0000h 28.4.12/ 640 4001_F28C Cache Data Storage (lower word) (FMC_DATAW2S1L) 32 R/W 0_0000 _0000h 28.4.13/ 641 4001_F290 Cache Data Storage (upper word) (FMC_DATAW2S2U) 32 R/W 0_0000 _0000h 28.4.12/ 640 4001_F294 Cache Data Storage (lower word) (FMC_DATAW2S2L) 32 R/W 0_0000 _0000h 28.4.13/ 641 4001_F298 Cache Data Storage (upper word) (FMC_DATAW2S3U) 32 R/W 0_0000 _0000h 28.4.12/ 640 4001_F29C Cache Data Storage (lower word) (FMC_DATAW2S3L) 32 R/W 0_0000 _0000h 28.4.13/ 641 4001_F2A0 Cache Data Storage (upper word) (FMC_DATAW2S4U) 32 R/W 0_0000 _0000h 28.4.12/ 640 4001_F2A4 Cache Data Storage (lower word) (FMC_DATAW2S4L) 32 R/W 0_0000 _0000h 28.4.13/ 641 4001_F2A8 Cache Data Storage (upper word) (FMC_DATAW2S5U) 32 R/W 0_0000 _0000h 28.4.12/ 640 4001_F2AC Cache Data Storage (lower word) (FMC_DATAW2S5L) 32 R/W 0_0000 _0000h 28.4.13/ 641 Table continues on the next page... Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 625 General Business Information

Page 626

FMC memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F2B0 Cache Data Storage (upper word) (FMC_DATAW2S6U) 32 R/W 0_0000 _0000h 28.4.12/ 640 4001_F2B4 Cache Data Storage (lower word) (FMC_DATAW2S6L) 32 R/W 0_0000 _0000h 28.4.13/ 641 4001_F2B8 Cache Data Storage (upper word) (FMC_DATAW2S7U) 32 R/W 0_0000 _0000h 28.4.12/ 640 4001_F2BC Cache Data Storage (lower word) (FMC_DATAW2S7L) 32 R/W 0_0000 _0000h 28.4.13/ 641 4001_F2C0 Cache Data Storage (upper word) (FMC_DATAW3S0U) 32 R/W 0_0000 _0000h 28.4.14/ 641 4001_F2C4 Cache Data Storage (lower word) (FMC_DATAW3S0L) 32 R/W 0_0000 _0000h 28.4.15/ 642 4001_F2C8 Cache Data Storage (upper word) (FMC_DATAW3S1U) 32 R/W 0_0000 _0000h 28.4.14/ 641 4001_F2CC Cache Data Storage (lower word) (FMC_DATAW3S1L) 32 R/W 0_0000 _0000h 28.4.15/ 642 4001_F2D0 Cache Data Storage (upper word) (FMC_DATAW3S2U) 32 R/W 0_0000 _0000h 28.4.14/ 641 4001_F2D4 Cache Data Storage (lower word) (FMC_DATAW3S2L) 32 R/W 0_0000 _0000h 28.4.15/ 642 4001_F2D8 Cache Data Storage (upper word) (FMC_DATAW3S3U) 32 R/W 0_0000 _0000h 28.4.14/ 641 4001_F2DC Cache Data Storage (lower word) (FMC_DATAW3S3L) 32 R/W 0_0000 _0000h 28.4.15/ 642 4001_F2E0 Cache Data Storage (upper word) (FMC_DATAW3S4U) 32 R/W 0_0000 _0000h 28.4.14/ 641 4001_F2E4 Cache Data Storage (lower word) (FMC_DATAW3S4L) 32 R/W 0_0000 _0000h 28.4.15/ 642 4001_F2E8 Cache Data Storage (upper word) (FMC_DATAW3S5U) 32 R/W 0_0000 _0000h 28.4.14/ 641 4001_F2EC Cache Data Storage (lower word) (FMC_DATAW3S5L) 32 R/W 0_0000 _0000h 28.4.15/ 642 4001_F2F0 Cache Data Storage (upper word) (FMC_DATAW3S6U) 32 R/W 0_0000 _0000h 28.4.14/ 641 4001_F2F4 Cache Data Storage (lower word) (FMC_DATAW3S6L) 32 R/W 0_0000 _0000h 28.4.15/ 642 4001_F2F8 Cache Data Storage (upper word) (FMC_DATAW3S7U) 32 R/W 0_0000 _0000h 28.4.14/ 641 4001_F2FC Cache Data Storage (lower word) (FMC_DATAW3S7L) 32 R/W 0_0000 _0000h 28.4.15/ 642 Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 626 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 627

28.4.1 Flash Access Protection Register (FMC_PFAPR) Address: 4001_F000h base + 0h offset = 4001_F000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 M7PFD M6PFD M5PFD M4PFD M3PFD M2PFD M1PFD M0PFD W Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R M7AP[1:0] M6AP[1:0] M5AP[1:0] M4AP[1:0] M3AP[1:0] M2AP[1:0] M1AP[1:0] M0AP[1:0] W Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 FMC_PFAPR field descriptions Field Description 31–24 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 23 M7PFD Master 7 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. 22 M6PFD Master 6 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. 21 M5PFD Master 5 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. 20 M4PFD Master 4 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. Table continues on the next page... Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 627 General Business Information

Page 628

FMC_PFAPR field descriptions (continued) Field Description 19 M3PFD Master 3 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. 18 M2PFD Master 2 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. 17 M1PFD Master 1 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. 16 M0PFD Master 0 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. 15–14 M7AP[1:0] Master 7 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 No access may be performed by this master. 01 Only read accesses may be performed by this master. 10 Only write accesses may be performed by this master. 11 Both read and write accesses may be performed by this master. 13–12 M6AP[1:0] Master 6 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 No access may be performed by this master 01 Only read accesses may be performed by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses may be performed by this master 11–10 M5AP[1:0] Master 5 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 No access may be performed by this master Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 628 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 629

FMC_PFAPR field descriptions (continued) Field Description 01 Only read accesses may be performed by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses may be performed by this master 9–8 M4AP[1:0] Master 4 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 No access may be performed by this master 01 Only read accesses may be performed by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses may be performed by this master 7–6 M3AP[1:0] Master 3 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 No access may be performed by this master 01 Only read accesses may be performed by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses may be performed by this master 5–4 M2AP[1:0] Master 2 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 No access may be performed by this master 01 Only read accesses may be performed by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses may be performed by this master 3–2 M1AP[1:0] Master 1 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 No access may be performed by this master 01 Only read accesses may be performed by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses may be performed by this master 1–0 M0AP[1:0] Master 0 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 No access may be performed by this master 01 Only read accesses may be performed by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses may be performed by this master Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 629 General Business Information

Page 630

28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR) Address: 4001_F000h base + 4h offset = 4001_F004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R B0RWSC[3:0] CLCK_WAY[3:0] 0 0 B0MW[1:0] 0 W CINV_WAY[3:0] S_B_ INV Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CRC[2:0] B0DCE B0ICE B0DPE B0IPE B0SEBE W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 FMC_PFB0CR field descriptions Field Description 31–28 B0RWSC[3:0] Bank 0 Read Wait State Control This read-only field defines the number of wait states required to access the bank 0 flash memory. The relationship between the read access time of the flash array (expressed in system clock cycles) and RWSC is defined as: Access time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates this value based on the ratio of the system clock speed to the flash clock speed. For example, when this ratio is 4:1, the field's value is 3h. 27–24 CLCK_WAY[3:0] Cache Lock Way x These bits determine if the given cache way is locked such that its contents will not be displaced by future misses. The bit setting definitions are for each bit in the field. 0 Cache way is unlocked and may be displaced 1 Cache way is locked and its contents are not displaced 23–20 CINV_WAY[3:0] Cache Invalidate Way x Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 630 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 631

FMC_PFB0CR field descriptions (continued) Field Description These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents are cleared. This field always reads as zero. Cache invalidation takes precedence over locking. The cache is invalidated by system reset. System software is required to maintain memory coherency when any segment of the flash memory is programmed or erased. Accordingly, cache invalidations must occur after a programming or erase event is completed and before the new memory image is accessed. The bit setting definitions are for each bit in the field. 0 No cache way invalidation for the corresponding cache 1 Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected 19 S_B_INV Invalidate Prefetch Speculation Buffer This bit determines if the FMC's prefetch speculation buffer and the single entry page buffer are to be invalidated (cleared). When this bit is written, the speculation buffer and single entry buffer are immediately cleared. This bit always reads as zero. 0 Speculation buffer and single entry buffer are not affected. 1 Invalidate (clear) speculation buffer and single entry buffer. 18–17 B0MW[1:0] Bank 0 Memory Width This read-only field defines the width of the bank 0 memory. 00 32 bits 01 64 bits 10 Reserved 11 Reserved 16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7–5 CRC[2:0] Cache Replacement Control This 3-bit field defines the replacement algorithm for accesses that are cached. 000 LRU replacement algorithm per set across all four ways 001 Reserved 010 Independent LRU with ways [0-1] for ifetches, [2-3] for data 011 Independent LRU with ways [0-2] for ifetches, [3] for data 1xx Reserved 4 B0DCE Bank 0 Data Cache Enable This bit controls whether data references are loaded into the cache. 0 Do not cache data references. 1 Cache data references. 3 B0ICE Bank 0 Instruction Cache Enable This bit controls whether instruction fetches are loaded into the cache. Table continues on the next page... Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 631 General Business Information

Page 632

FMC_PFB0CR field descriptions (continued) Field Description 0 Do not cache instruction fetches. 1 Cache instruction fetches. 2 B0DPE Bank 0 Data Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. 0 Do not prefetch in response to data references. 1 Enable prefetches in response to data references. 1 B0IPE Bank 0 Instruction Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches. 0 Do not prefetch in response to instruction fetches. 1 Enable prefetches in response to instruction fetches. 0 B0SEBE Bank 0 Single Entry Buffer Enable This bit controls whether the single entry page buffer is enabled in response to flash read accesses. Its operation is independent from bank 1's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. 0 Single entry buffer is disabled. 1 Single entry buffer is enabled. Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 632 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 633

28.4.3 Flash Bank 1 Control Register (FMC_PFB1CR) This register has a format similar to that for PFB0CR, except it controls the operation of flash bank 1, and the "global" cache control fields are empty. Address: 4001_F000h base + 8h offset = 4001_F008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R B1RWSC[3:0] 0 B1MW[1:0] 0 W Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 B1DCE B1ICE B1DPE B1IPE B1SEBE W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 FMC_PFB1CR field descriptions Field Description 31–28 B1RWSC[3:0] Bank 1 Read Wait State Control This read-only field defines the number of wait states required to access the bank 1 flash memory. The relationship between the read access time of the flash array (expressed in system clock cycles) and RWSC is defined as: Access time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates this value based on the ratio of the system clock speed to the flash clock speed. For example, when this ratio is 4:1, the field's value is 3h. 27–19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18–17 B1MW[1:0] Bank 1 Memory Width This read-only field defines the width of the bank 1 memory. Table continues on the next page... Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 633 General Business Information

Page 634

FMC_PFB1CR field descriptions (continued) Field Description 00 32 bits 01 64 bits 10 Reserved 11 Reserved 16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7–5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 B1DCE Bank 1 Data Cache Enable This bit controls whether data references are loaded into the cache. 0 Do not cache data references. 1 Cache data references. 3 B1ICE Bank 1 Instruction Cache Enable This bit controls whether instruction fetches are loaded into the cache. 0 Do not cache instruction fetches. 1 Cache instruction fetches. 2 B1DPE Bank 1 Data Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. 0 Do not prefetch in response to data references. 1 Enable prefetches in response to data references. 1 B1IPE Bank 1 Instruction Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches. 0 Do not prefetch in response to instruction fetches. 1 Enable prefetches in response to instruction fetches. 0 B1SEBE Bank 1 Single Entry Buffer Enable This bit controls whether the single entry buffer is enabled in response to flash read accesses. Its operation is independent from bank 0's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. 0 Single entry buffer is disabled. 1 Single entry buffer is enabled. Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 634 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 635

28.4.4 Cache Tag Storage (FMC_TAGVDW0Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 100h offset + (4d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 tag[18:6] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R tag[18:6] 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW0Sn field descriptions Field Description 31–19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18–6 tag[18:6] 13-bit tag for cache entry 5–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 635 General Business Information

Page 636

28.4.5 Cache Tag Storage (FMC_TAGVDW1Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 120h offset + (4d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 tag[18:6] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R tag[18:6] 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW1Sn field descriptions Field Description 31–19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18–6 tag[18:6] 13-bit tag for cache entry 5–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 636 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 637

28.4.6 Cache Tag Storage (FMC_TAGVDW2Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 140h offset + (4d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 tag[18:6] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R tag[18:6] 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW2Sn field descriptions Field Description 31–19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18–6 tag[18:6] 13-bit tag for cache entry 5–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 637 General Business Information

Page 638

28.4.7 Cache Tag Storage (FMC_TAGVDW3Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 160h offset + (4d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 tag[18:6] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R tag[18:6] 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW3Sn field descriptions Field Description 31–19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18–6 tag[18:6] 13-bit tag for cache entry 5–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry 28.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 200h offset + (8d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[63:32] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 638 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 639

FMC_DATAW0SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry 28.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 204h offset + (8d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[31:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW0SnL field descriptions Field Description 31–0 data[31:0] Bits [31:0] of data entry 28.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 240h offset + (8d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[63:32] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 639 General Business Information

Page 640

FMC_DATAW1SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry 28.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 244h offset + (8d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[31:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW1SnL field descriptions Field Description 31–0 data[31:0] Bits [31:0] of data entry 28.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 280h offset + (8d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[63:32] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 640 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 641

FMC_DATAW2SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry 28.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 284h offset + (8d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[31:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW2SnL field descriptions Field Description 31–0 data[31:0] Bits [31:0] of data entry 28.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 2C0h offset + (8d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[63:32] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 641 General Business Information

Page 642

FMC_DATAW3SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry 28.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 2C4h offset + (8d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[31:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW3SnL field descriptions Field Description 31–0 data[31:0] Bits [31:0] of data entry 28.5 Functional description The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides managing the interface between the device and the flash memory and FlexMemory, the FMC can be used to restrict access from crossbar switch masters and customize the cache and buffers to provide single-cycle system-clock data-access times. Whenever a hit occurs for the prefetch speculation buffer, the cache, or the single-entry buffer, the requested data is transferred within a single system clock. 28.5.1 Default configuration Upon system reset, the FMC is configured to provide a significant level of buffering for transfers from the flash memory or FlexMemory: • Crossbar masters 0, 1, 2 have read access to bank 0 and bank 1. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 642 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 643

• These masters have write access to a portion of bank 1 when FlexNVM is used with FlexRAM as EEPROM. • For bank 0 and bank 1: • Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2. • The cache is configured for least recently used (LRU) replacement for all four ways. • The cache is configured for data or instruction replacement. • The single-entry buffer is enabled. 28.5.2 Configuration options Though the default configuration provides a high degree of flash acceleration, advanced users may desire to customize the FMC buffer configurations to maximize throughput for their use cases. When reconfiguring the FMC for custom use cases, do not program the FMC's control registers while the flash memory or FlexMemory is being accessed. Instead, change the control registers with a routine executing from RAM in supervisor mode. The FMC's cache and buffering controls within PFB0CR and PFB1CR allow the tuning of resources to suit particular applications' needs. The cache and two buffers are each controlled individually. The register controls enable buffering and prefetching per memory bank and access type (instruction fetch or data reference). The cache also supports three types of LRU replacement algorithms: • LRU per set across all four ways, • LRU with ways [0-1] for instruction fetches and ways [2-3] for data fetches, and • LRU with ways [0-2] for instruction fetches and way [3] for data fetches. As an application example: if both instruction fetches and data references are accessing bank 0, control is available to send instruction fetches, data references, or both to the cache or the single-entry buffer. Likewise, speculation can be enabled or disabled for either type of access. If both instruction fetches and data references are cached, the cache's way resources may be divided in several ways between the instruction fetches and data references. In another application example, the cache can be configured for replacement from bank 0, while the single-entry buffer can be enabled for bank 1 only. This configuration is ideal for applications that use bank 0 for program space and bank 1 for data space. Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 643 General Business Information

Page 644

28.5.3 Wait states Because the core, crossbar switch, and bus masters can be clocked at a higher frequency than the flash clock, flash memory accesses that do not hit in the speculation buffer or cache usually require wait states. The number of wait states depends on both of the following:

the ratio of the core clock to the flash clock, and
the phase relationship of the core clock and flash clock at the time the read is requested. The ratio of the core clock to the flash clock is equal to the value of PFB0CR[B0RWSC]

1 for bank 0 and to the value of PFB1CR[B1RWSC] + 1 for bank 1. For example, in a system with a 4:1 core-to-flash clock ratio, a read that does not hit in the speculation buffer or the cache can take between 4 and 7 core clock cycles to complete. • The best-case scenario is a period of 4 core clock cycles because a read from the flash memory takes 1 flash clock, which translates to 4 core clocks. • The worst-case scenario is a period of 7 core clock cycles, consisting of 4 cycles for the read operation and 3 cycles of delay to align the core and flash clocks. • A delay to align the core and flash clocks might occur because you can request a read cycle on any core clock edge, but that edge does not necessarily align with a flash clock edge where the read can start. • In this case, the read operation is delayed by a number of core clocks equal to the core-to-flash clock ratio minus one: 4 - 1 = 3. That is, 3 additional core clock cycles are required to synchronize the clocks before the read operation can start. All wait states and synchronization delays are handled automatically by the Flash Memory Controller. No direct user configuration is required or even allowed to set up the flash wait states. 28.5.4 Speculative reads The FMC has a single buffer that reads ahead to the next word in the flash memory if there is an idle cycle. Speculative prefetching is programmable for each bank for instruction and/or data accesses using the B0DPE and B0IPE fields of PFB0CR and the B1DPE and B1IPE fields of PFB1CR. Because many code accesses are sequential, using the speculative prefetch buffer improves performance in most cases. When speculative reads are enabled, the FMC immediately requests the next sequential address after a read completes. By requesting the next word immediately, speculative reads can help to reduce or even eliminate wait states when accessing sequential code and/or data. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 644 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 645

For example, consider the following scenario: • Assume a system with a 4:1 core-to-flash clock ratio and with speculative reads enabled. • The core requests four sequential longwords in back-to-back requests, meaning there are no core cycle delays except for stalls waiting for flash memory data to be returned. • None of the data is already stored in the cache or speculation buffer. In this scenario, the sequence of events for accessing the four longwords is as follows:

The first longword read requires 4 to 7 core clocks. See Wait states for more information.
Due to the 64-bit data bus of the flash memory, the second longword read takes only 1 core clock because the data is already available inside the FMC. While the data for the second longword is being returned to the core, the FMC also starts reading the third and fourth longwords from the flash memory.
Accessing the third longword requires 3 core clock cycles. The flash memory read itself takes 4 clocks, but the first clock overlaps with the second longword read.
Reading the fourth longword, like the second longword, takes only 1 clock due to the 64-bit flash memory data bus. 28.6 Initialization and application information The FMC does not require user initialization. Flash acceleration features are enabled by default. The FMC has no visibility into flash memory erase and program cycles because the Flash Memory module manages them directly. As a result, if an application is executing flash memory commands, the FMC's cache might need to be disabled and/or flushed to prevent the possibility of returning stale data. Use the PFB0CR[CINV_WAY] field to invalidate the cache in this manner. Chapter 28 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 645 General Business Information

Page 646

Initialization and application information K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 646 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 647

Chapter 29 Flash Memory Module (FTFL) 29.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. The flash memory module includes the following accessible memory regions: • Program flash memory for vector space and code store • For FlexNVM devices: FlexNVM for data store and additional code store • For FlexNVM devices: FlexRAM for high-endurance data store or traditional RAM • For program flash only devices: Programming acceleration RAM to speed flash programming Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources. The flash memory module includes a memory controller that executes commands to modify flash memory contents. An erased bit reads '1' and a programmed bit reads '0'. The programming operation is unidirectional; it can only move bits from the '1' state (erased) to the '0' state (programmed). Only the erase operation restores bits from '0' to '1'; bits cannot be programmed from a '0' to a '1'. K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 647 General Business Information

Page 648

CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. The standard shipping condition for flash memory is erased with security disabled. Data loss over time may occur due to degradation of the erased ('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. 29.1.1 Features The flash memory module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. 29.1.1.1 Program Flash Memory Features • Sector size of 2 Kbytes • Program flash protection scheme prevents accidental program or erase of stored data • Automated, built-in, program and erase algorithms with verify • Section programming for faster bulk programming times • For devices containing only program flash memory: Read access to one logical program flash block is possible while programming or erasing data in the other logical program flash block • For devices containing FlexNVM memory: Read access to program flash memory possible while programming or erasing data in the data flash memory or FlexRAM Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 648 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 649

29.1.1.2 FlexNVM Memory Features When FlexNVM is partitioned for data flash memory (on devices that contain FlexNVM memory): • Sector size of 2 Kbytes • Protection scheme prevents accidental program or erase of stored data • Automated, built-in program and erase algorithms with verify • Section programming for faster bulk programming times • Read access to data flash memory possible while programming or erasing data in the program flash memory 29.1.1.3 Programming Acceleration RAM Features • For devices with only program flash memory: RAM to support section programming 29.1.1.4 FlexRAM Features For devices with FlexNVM memory: • Memory that can be used as traditional RAM or as high-endurance EEPROM storage • Up to 4 Kbytes of FlexRAM configured for EEPROM or traditional RAM operations • When configured for EEPROM: • Protection scheme prevents accidental program or erase of data written for EEPROM • Built-in hardware emulation scheme to automate EEPROM record maintenance functions • Programmable EEPROM data set size and FlexNVM partition code facilitating EEPROM memory endurance trade-offs • Supports FlexRAM aligned writes of 1, 2, or 4 bytes at a time • Read access to FlexRAM possible while programming or erasing data in the program or data flash memory • When configured for traditional RAM: Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 649 General Business Information

Page 650

• Read and write access possible to the FlexRAM while programming or erasing data in the program or data flash memory 29.1.1.5 Other Flash Memory Module Features • Internal high-voltage supply generator for flash memory program and erase operations • Optional interrupt generation upon flash command completion • Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 29.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. For devices with FlexNVM feature: FlexNVM FlexRAM Program flash EEPROM backup To MCU's flash controller Interrupt Control registers Status registers Register access Data flash Memory controller Figure 29-1. Flash Block Diagram For devices that contain only program flash: Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 650 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 651

Program flash 1 Programming acceleration RAM Program flash 0 To MCU's flash controller Interrupt Control registers Status registers Register access Memory controller Figure 29-2. Flash Block Diagram 29.1.3 Glossary Command write sequence — A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module. Data flash memory — Partitioned from the FlexNVM block, the data flash memory provides nonvolatile storage for user data, boot code, and additional code store. Data flash sector — The data flash sector is the smallest portion of the data flash memory that can be erased. EEPROM — Using a built-in filing system, the flash memory module emulates the characteristics of an EEPROM by effectively providing a high-endurance, byte-writeable (program and erase) NVM. EEPROM backup data header — The EEPROM backup data header is comprised of a 32-bit field found in EEPROM backup data memory which contains information used by the EEPROM filing system to determine the status of a specific EEPROM backup flash sector. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 651 General Business Information

Page 652

EEPROM backup data record — The EEPROM backup data record is comprised of a 2-bit status field, a 14-bit address field, and a 16-bit data field found in EEPROM backup data memory which is used by the EEPROM filing system. If the status field indicates a record is valid, the data field is mirrored in the FlexRAM at a location determined by the address field. EEPROM backup data memory — Partitioned from the FlexNVM block, EEPROM backup data memory provides nonvolatile storage for the EEPROM filing system representing data written to the FlexRAM requiring highest endurance. EEPROM backup data sector — The EEPROM backup data sector contains one EEPROM backup data header and up to 255 EEPROM backup data records, which are used by the EEPROM filing system. Endurance — The number of times that a flash memory location can be erased and reprogrammed. FCCOB (Flash Common Command Object) — A group of flash registers that are used to pass command, address, data, and any associated parameters to the memory controller in the flash memory module. Flash block — A macro within the flash memory module which provides the nonvolatile memory storage. FlexMemory — Flash configuration that supports data flash, EEPROM, and FlexRAM. FlexNVM Block — The FlexNVM block can be configured to be used as data flash memory, EEPROM backup flash memory, or a combination of both. FlexRAM — The FlexRAM refers to a RAM, dedicated to the flash memory module, that can be configured to store EEPROM data or as traditional RAM. When configured for EEPROM, valid writes to the FlexRAM generate new EEPROM backup data records stored in the EEPROM backup flash memory. Flash Memory Module — All flash blocks plus a flash management unit providing high-level control and an interface to MCU buses. IFR — Nonvolatile information register found in each flash block, separate from the main memory array. NVM — Nonvolatile memory. A memory technology that maintains stored data during power-off. The flash array is an NVM using NOR-type flash memory technology. NVM Normal Mode — An NVM mode that provides basic user access to flash memory module resources. The CPU or other bus masters initiate flash program and erase operations (or other flash commands) using writes to the FCCOB register group in the flash memory module. Introduction K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 652 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 653

NVM Special Mode — An NVM mode enabling external, off-chip access to the memory resources in the flash memory module. A reduced flash command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used. Phrase — 64 bits of data with an aligned phrase having byte-address[2:0] = 000. Longword — 32 bits of data with an aligned longword having byte-address[1:0] = 00. Word — 16 bits of data with an aligned word having byte-address[0] = 0. Program flash — The program flash memory provides nonvolatile storage for vectors and code store. Program flash Sector — The smallest portion of the program flash memory (consecutive addresses) that can be erased. Retention — The length of time that data can be kept in the NVM without experiencing errors upon readout. Since erased (1) states are subject to degradation just like programmed (0) states, the data retention limit may be reached from the last erase operation (not from the programming time). RWW— Read-While-Write. The ability to simultaneously read from one memory resource while commanded operations are active in another memory resource. Section Program Buffer — Lower half of the programming acceleration RAM or FlexRAM allocated for storing large amounts of data for programming via the Program Section command. Secure — An MCU state conveyed to the flash memory module as described in the Chip Configuration details for this device. In the secure state, reading and changing NVM contents is restricted. 29.2 External Signal Description The flash memory module contains no signals that connect off-chip. 29.3 Memory Map and Registers This section describes the memory map and registers for the flash memory module. Data read from unimplemented memory space in the flash memory module is undefined. Writes to unimplemented or reserved memory space (registers) in the flash memory module are ignored. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 653 General Business Information

Page 654

29.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module. Flash Configuration Field Byte Address Size (Bytes) Field Description 0x0_0400 - 0x0_0407 8 Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access. 0x0_0408 - 0x0_040B 4 Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3). 0x0_040F 1 Program flash only devices: Reserved FlexNVM devices: Data flash protection byte. Refer to the description of the Data Flash Protection Register (FDPROT). 0x0_040E 1 Program flash only devices: Reserved FlexNVM devices: EEPROM protection byte. Refer to the description of the EEPROM Protection Register (FEPROT). 0x0_040D 1 Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT). 0x0_040C 1 Flash security byte. Refer to the description of the Flash Security Register (FSEC). 29.3.2 Program Flash IFR Map The program flash IFR is nonvolatile information memory that can be read freely, but the user has no erase and limited program capabilities (see the Read Once, Program Once, and Read Resource commands in Read Once Command, Program Once Command and Read Resource Command). The contents of the program flash IFR are summarized in the following table and further described in the subsequent paragraphs. The program flash IFR is located within the program flash 0 memory block for devices that only contain program flash. Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 654 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 655

Address Range Size (Bytes) Field Description 0x00 – 0xBF 192 Reserved 0xC0 – 0xFF 64 Program Once Field 29.3.2.1 Program Once Field The Program Once Field in the program flash IFR provides 64 bytes of user data storage separate from the program flash main array. The user can program the Program Once Field one time only as there is no program flash IFR erase mechanism available to the user. The Program Once Field can be read any number of times. This section of the program flash IFR is accessed in 4-Byte records using the Read Once and Program Once commands (see Read Once Command and Program Once Command). 29.3.3 Data Flash IFR Map The following only applies to devices with FlexNVM. The data flash IFR is a 256 byte nonvolatile information memory that can be read and erased, but the user has limited program capabilities in the data flash IFR (see the Program Partition command in Program Partition Command, the Erase All Blocks command in Erase All Blocks Command, and the Read Resource command in Read Resource Command). The contents of the data flash IFR are summarized in the following table and further described in the subsequent paragraphs. Address Range Size (Bytes) Field Description 0x00 – 0xFB, 0xFE – 0xFF 254 Reserved 0xFD 1 EEPROM data set size 0xFC 1 FlexNVM partition code 29.3.3.1 EEPROM Data Set Size The EEPROM data set size byte in the data flash IFR supplies information which determines the amount of FlexRAM used in each of the available EEPROM subsystems. To program the EEESPLIT and EEESIZE values, see the Program Partition command described in Program Partition Command. Table 29-1. EEPROM Data Set Size Data flash IFR: 0x00FD Table continues on the next page... Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 655 General Business Information

Page 656

Table 29-1. EEPROM Data Set Size (continued) 7 6 5 4 3 2 1 0 1 1 EEESPLIT EEESIZE = Unimplemented or Reserved Table 29-2. EEPROM Data Set Size Field Description Field Description 7-6 Reserved This read-only bitfield is reserved and must always be written as one. 5-4 EEESPLIT EEPROM Split Factor — Determines the relative sizes of the two EEPROM subsystems. ‘00’ = Subsystem A: EEESIZE*1/8, subsystem B: EEESIZE*7/8 ‘01’ = Subsystem A: EEESIZE*1/4, subsystem B: EEESIZE*3/4 ‘10’ = Subsystem A: EEESIZE*1/2, subsystem B: EEESIZE*1/2 ‘11’ = Subsystem A: EEESIZE*1/2, subsystem B: EEESIZE*1/2 3-0 EEESIZE EEPROM Size — Encoding of the total available FlexRAM for EEPROM use. NOTE: EEESIZE must be 0 bytes (1111b) when the FlexNVM partition code (FlexNVM Partition Code) is set to 'No EEPROM'. '0000' = Reserved '0001' = Reserved '0010' = 4,096 Bytes '0011' = 2,048 Bytes '0100' = 1,024 Bytes '0101' = 512 Bytes '0110' = 256 Bytes '0111' = 128 Bytes '1000' = 64 Bytes '1001' = 32 Bytes '1010' = Reserved '1011' = Reserved '1100' = Reserved '1101' = Reserved '1110' = Reserved '1111' = 0 Bytes Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 656 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 657

29.3.3.2 FlexNVM Partition Code The FlexNVM Partition Code byte in the data flash IFR supplies a code which specifies how to split the FlexNVM block between data flash memory and EEPROM backup memory supporting EEPROM functions. To program the DEPART value, see the Program Partition command described in Program Partition Command. Table 29-3. FlexNVM Partition Code Data Flash IFR: 0x00FC 7 6 5 4 3 2 1 0 1 1 1 1 DEPART = Unimplemented or Reserved Table 29-4. FlexNVM Partition Code Field Description Field Description 7-4 Reserved This read-only bitfield is reserved and must always be written as one. 3-0 DEPART FlexNVM Partition Code — Encoding of the data flash / EEPROM backup split within the FlexNVM memory block. FlexNVM memory not partitioned for data flash will be used to store EEPROM records. DEPART Data flash (KByte) EEPROM backup (KByte) 0000 256 0 0001 Reserved Reserved 0010 Reserved Reserved 0011 224 32 0100 192 64 0101 128 128 0110 0 256 0111 Reserved Reserved 1000 0 256 1001 Reserved Reserved 1010 Reserved Reserved 1011 32 224 1100 64 192 1101 128 128 1110 256 0 1111 Reserved (defaults to 256) Reserved (defaults to 0) Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 657 General Business Information

Page 658

29.3.4 Register Descriptions The flash memory module contains a set of memory-mapped control and status registers. NOTE While a command is running (FSTAT[CCIF]=0), register writes are not accepted to any register except FCNFG and FSTAT. The no-write rule is relaxed during the start-up reset sequence, prior to the initial rise of CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). FTFL memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4002_0000 Flash Status Register (FTFL_FSTAT) 8 R/W 000h 29.34.1/ 659 4002_0001 Flash Configuration Register (FTFL_FCNFG) 8 R/W 000h 29.34.2/ 661 4002_0002 Flash Security Register (FTFL_FSEC) 8 R Undefined 29.34.3/ 663 4002_0003 Flash Option Register (FTFL_FOPT) 8 R Undefined 29.34.4/ 664 4002_0004 Flash Common Command Object Registers (FTFL_FCCOB3) 8 R/W 000h 29.34.5/ 665 4002_0005 Flash Common Command Object Registers (FTFL_FCCOB2) 8 R/W 000h 29.34.5/ 665 4002_0006 Flash Common Command Object Registers (FTFL_FCCOB1) 8 R/W 000h 29.34.5/ 665 4002_0007 Flash Common Command Object Registers (FTFL_FCCOB0) 8 R/W 000h 29.34.5/ 665 4002_0008 Flash Common Command Object Registers (FTFL_FCCOB7) 8 R/W 000h 29.34.5/ 665 4002_0009 Flash Common Command Object Registers (FTFL_FCCOB6) 8 R/W 000h 29.34.5/ 665 4002_000A Flash Common Command Object Registers (FTFL_FCCOB5) 8 R/W 000h 29.34.5/ 665 4002_000B Flash Common Command Object Registers (FTFL_FCCOB4) 8 R/W 000h 29.34.5/ 665 4002_000C Flash Common Command Object Registers (FTFL_FCCOBB) 8 R/W 000h 29.34.5/ 665 4002_000D Flash Common Command Object Registers (FTFL_FCCOBA) 8 R/W 000h 29.34.5/ 665 Table continues on the next page... Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 658 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 659

FTFL memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4002_000E Flash Common Command Object Registers (FTFL_FCCOB9) 8 R/W 000h 29.34.5/ 665 4002_000F Flash Common Command Object Registers (FTFL_FCCOB8) 8 R/W 000h 29.34.5/ 665 4002_0010 Program Flash Protection Registers (FTFL_FPROT3) 8 R/W Undefined 29.34.6/ 666 4002_0011 Program Flash Protection Registers (FTFL_FPROT2) 8 R/W Undefined 29.34.6/ 666 4002_0012 Program Flash Protection Registers (FTFL_FPROT1) 8 R/W Undefined 29.34.6/ 666 4002_0013 Program Flash Protection Registers (FTFL_FPROT0) 8 R/W Undefined 29.34.6/ 666 4002_0016 EEPROM Protection Register (FTFL_FEPROT) 8 R/W Undefined 29.34.7/ 667 4002_0017 Data Flash Protection Register (FTFL_FDPROT) 8 R/W Undefined 29.34.8/ 669 29.34.1 Flash Status Register (FTFL_FSTAT) The FSTAT register reports the operational status of the flash memory module. The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. NOTE When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of any more commands or writes to the FlexRAM (when EEERDY is set) until the flag is cleared (by writing a one to it). Address: 4002_0000h base + 0h offset = 4002_0000h Bit 7 6 5 4 3 2 1 0 Read CCIF RDCOLERR ACCERR FPVIOL 0 MGSTAT0 Write w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 FTFL_FSTAT field descriptions Field Description 7 CCIF Command Complete Interrupt Flag The CCIF flag indicates that a flash command or EEPROM file system operation has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command, and CCIF stays low until command Table continues on the next page... Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 659 General Business Information

Page 660

FTFL_FSTAT field descriptions (continued) Field Description completion or command violation. The CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE, and CCIF stays low until the EEPROM file system has created the associated EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory controller at the end of the reset initialization sequence. Depending on how quickly the read occurs after reset release, the user may or may not see the 0 hardware reset value. 0 Flash command or EEPROM file system operation in progress 1 Flash command or EEPROM file system operation has completed 6 RDCOLERR Flash Read Collision Error Flag The RDCOLERR error bit indicates that the MCU attempted a read from a flash memory resource that was being manipulated by a flash command (CCIF=0). Any simultaneous access is detected as a collision error by the block arbitration logic. The read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to it. Writing a 0 to RDCOLERR has no effect. 0 No collision error detected 1 Collision error detected 5 ACCERR Flash Access Error Flag The ACCERR error bit indicates an illegal access has occurred to a flash memory resource caused by a violation of the command write sequence or issuing an illegal flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the ACCERR bit has no effect. 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag The FPVIOL error bit indicates an attempt was made to program or erase an address in a protected area of program flash or data flash memory during a command write sequence or a write was attempted to a protected area of the FlexRAM while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a 0 to the FPVIOL bit has no effect. 0 No protection violation detected 1 Protection violation detected 3–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 MGSTAT0 Memory Controller Command Completion Status Flag The MGSTAT0 status flag is set if an error is detected during execution of a flash command or during the flash reset sequence. As a status flag, this bit cannot (and need not) be cleared by the user like the other error flags in this register. The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution when CCIF=1 and before the next command has been launched. At some point during the execution of "command-N+1," the previous result is discarded and any previous error is cleared. Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 660 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 661

29.34.2 Flash Configuration Register (FTFL_FCNFG) This register provides information on the current functional state of the flash memory module. The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. SWAP,PFLSH, RAMRDY, and EEERDY are read-only status bits . The unassigned bits read as noted and are not writable. The reset values for the SWAP, PFLASH, RAMRDY , and EEERDY bits are determined during the reset sequence. Address: 4002_0000h base + 1h offset = 4002_0001h Bit 7 6 5 4 3 2 1 0 Read CCIE RDCOLLIE ERSAREQ ERSSUSP SWAP PFLSH RAMRDY EEERDY Write Reset 0 0 0 0 0 0 0 0 FTFL_FCNFG field descriptions Field Description 7 CCIE Command Complete Interrupt Enable The CCIE bit controls interrupt generation when a flash command completes. 0 Command complete interrupt disabled 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. 6 RDCOLLIE Read Collision Error Interrupt Enable The RDCOLLIE bit controls interrupt generation when a flash memory read collision error occurs. 0 Read collision error interrupt disabled 1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). 5 ERSAREQ Erase All Request This bit issues a request to the memory controller to execute the Erase All Blocks command and release security. ERSAREQ is not directly writable but is under indirect user control. Refer to the device's Chip Configuration details on how to request this command. The ERSAREQ bit sets when an erase all request is triggered external to the flash memory module and CCIF is set (no command is currently being executed). ERSAREQ is cleared by the flash memory module when the operation completes. 0 No request or request complete 1 Request to:

run the Erase All Blocks command,
verify the erased state,
program the security byte in the Flash Configuration Field to the unsecure state, and
release MCU security by setting the FSEC[SEC] field to the unsecure state. Table continues on the next page... Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 661 General Business Information

Page 662

FTFL_FCNFG field descriptions (continued) Field Description 4 ERSSUSP Erase Suspend The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector command while it is executing. 0 No suspend requested 1 Suspend the current Erase Flash Sector command execution. 3 SWAP Swap For program flash only configurations, the SWAP flag indicates which physical program flash block is located at relative address 0x0000. The state of the SWAP flag is set by the flash memory module during the reset sequence. See the Swap Control command section for information on swap management. 0 Physical program flash 0 is located at relative address 0x0000 1 If the PFLSH flag is set, physical program flash 1 is located at relative address 0x0000. If the PFLSH flag is not set, physical program flash 0 is located at relative address 0x0000 2 PFLSH Flash memory configuration 0 For devices with FlexNVM: Flash memory module configured for FlexMemory that supports data flash and/or EEPROM. For devices with program flash only: Reserved 1 For devices with FlexNVM: Reserved. For devices with program flash only: Flash memory module configured for program flash only, without support for data flash and/or EEPROM 1 RAMRDY RAM Ready This flag indicates the current status of the FlexRAM/programming acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally controlled by the Set FlexRAM Function command. During the reset sequence, the RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and is set if the FlexNVM block is not partitioned for EEPROM. The RAMRDY flag is cleared if the Program Partition command is run to partition the FlexNVM block for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks command or execution of the erase-all operation triggered external to the flash memory module. For devices without FlexNVM: This bit should always be set. 0 For devices with FlexNVM: FlexRAM is not available for traditional RAM access. For devices without FlexNVM: Programming acceleration RAM is not available. 1 For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations. For devices without FlexNVM: Programming acceleration RAM is available. 0 EEERDY For devices with FlexNVM: This flag indicates if the EEPROM backup data has been copied to the FlexRAM and is therefore available for read access. During the reset sequence, the EEERDY flag will remain cleared while CCIF is clear and will only set if the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM: This field is reserved. 0 For devices with FlexNVM: FlexRAM is not available for EEPROM operation. 1 For devices with FlexNVM: FlexRAM is available for EEPROM operations where: • reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and • writes to the FlexRAM clear EEERDY and launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup. Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 662 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 663

29.34.3 Flash Security Register (FTFL_FSEC) This read-only register holds all bits associated with the security of the MCU and flash memory module. During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. Address: 4002_0000h base + 2h offset = 4002_0002h Bit 7 6 5 4 3 2 1 0 Read KEYEN MEEN FSLACC SEC Write Reset x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • FTFL_FSEC field descriptions Field Description 7–6 KEYEN Backdoor Key Security Enable These bits enable and disable backdoor key access to the flash memory module. 00 Backdoor key access disabled 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 10 Backdoor key access enabled 11 Backdoor key access disabled 5–4 MEEN Mass Erase Enable Bits Enables and disables mass erase capability of the flash memory module. The state of the MEEN bits is only relevant when the SEC bits are set to secure outside of NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does not matter. 00 Mass erase is enabled 01 Mass erase is enabled 10 Mass erase is disabled 11 Mass erase is enabled 3–2 FSLACC Freescale Failure Analysis Access Code These bits enable or disable access to the flash memory contents during returned part failure analysis at Freescale. When SEC is secure and FSLACC is denied, access to the program flash contents is denied and any failure analysis performed by Freescale factory test must begin with a full erase to unsecure the part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted), Freescale factory testing has visibility of the current flash contents. The state of the FSLACC bits is only relevant when the SEC bits are set to secure. When the SEC field is set to unsecure, the FSLACC setting does not matter. Table continues on the next page... Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 663 General Business Information

Page 664

FTFL_FSEC field descriptions (continued) Field Description 00 Freescale factory access granted 01 Freescale factory access denied 10 Freescale factory access denied 11 Freescale factory access granted 1–0 SEC Flash Security These bits define the security state of the MCU. In the secure state, the MCU limits access to flash memory module resources. The limitations are defined per device and are detailed in the Chip Configuration details. If the flash memory module is unsecured using backdoor key access, the SEC bits are forced to 10b. 00 MCU security status is secure 01 MCU security status is secure 10 MCU security status is unsecure (The standard shipping condition of the flash memory module is unsecure.) 11 MCU security status is secure 29.34.4 Flash Option Register (FTFL_FOPT) The flash option register allows the MCU to customize its operations by examining the state of these read-only bits, which are loaded from NVM at reset. The function of the bits is defined in the device's Chip Configuration details. All bits in the register are read-only . During the reset sequence, the register is loaded from the flash nonvolatile option byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. Address: 4002_0000h base + 3h offset = 4002_0003h Bit 7 6 5 4 3 2 1 0 Read OPT Write Reset x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • FTFL_FOPT field descriptions Field Description 7–0 OPT Nonvolatile Option These bits are loaded from flash to this register at reset. Refer to the device's Chip Configuration details for the definition and use of these bits. Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 664 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 665

29.34.5 Flash Common Command Object Registers (FTFL_FCCOBn) The FCCOB register group provides 12 bytes for command codes and parameters. The individual bytes within the set append a 0-B hex identifier to the FCCOB register name: FCCOB0, FCCOB1, ..., FCCOBB. Address: 4002_0000h base + 4h offset + (1d × i), where i=0d to 11d Bit 7 6 5 4 3 2 1 0 Read CCOBn Write Reset 0 0 0 0 0 0 0 0 FTFL_FCCOBn field descriptions Field Description 7–0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller. The individual registers that compose the FCCOB data set can be written in any order, but you must provide all needed values, which vary from command to command. First, set up all required FCCOB fields and then initiate the command’s execution by writing a 1 to the FSTAT[CCIF] bit. This clears the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed by the user until the command completes (CCIF returns to 1). No command buffering or queueing is provided; the next command can be loaded only after the current command completes. Some commands return information to the FCCOB registers. Any values returned to FCCOB are available for reading after the FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a generic flash command format. The first FCCOB register, FCCOB0, always contains the command code. This 8-bit value defines the command to be executed. The command code is followed by the parameters required for this specific flash command, typically an address and/or data values. NOTE: The command parameter table is written in terms of FCCOB Number (which is equivalent to the byte number). This number is a reference to the FCCOB register name and is not the register address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 665 General Business Information

Page 666

FTFL_FCCOBn field descriptions (continued) Field Description FCCOB Number Typical Command Parameter Contents [7:0] A Data Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access : The FCCOB register group uses a big endian addressing convention. For all command parameter fields larger than 1 byte, the most significant data resides in the lowest FCCOB register number. The FCCOB register group may be read and written as individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). 29.34.6 Program Flash Protection Registers (FTFL_FPROTn) The FPROT registers define which logical program flash regions are protected from program and erase operations. Protected flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any flash command. Unprotected regions can be changed by program and erase operations. The four FPROT registers allow 32 protectable regions. Each bit protects a 1/32 region of the program flash memory . The bitfields are defined in each register as follows: Program flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the FPROT registers are loaded with the contents of the program flash protection bytes in the Flash Configuration Field as indicated in the following table. Program flash protection register Flash Configuration Field offset address FPROT0 0x0008 FPROT1 0x0009 FPROT2 0x000A FPROT3 0x000B Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 666 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 667

To change the program flash protection that is loaded during the reset sequence, unprotect the sector of program flash memory that contains the Flash Configuration Field. Then, reprogram the program flash protection byte. Address: 4002_0000h base + 10h offset + (1d × i), where i=0d to 3d Bit 7 6 5 4 3 2 1 0 Read PROT Write Reset x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • FTFL_FPROTn field descriptions Field Description 7–0 PROT Program Flash Region Protect Each program flash region can be protected from program and erase operations by setting the associated PROT bit. In NVM Normal mode: The protection can only be increased, meaning that currently unprotected memory can be protected, but currently protected memory cannot be unprotected. Since unprotected regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are writable without restriction. Unprotected areas can be protected and protected areas can be unprotected. Restriction: The user must never write to any FPROT register while a command is running (CCIF=0). Trying to alter data in any protected area in the program flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it contains any protected region. Each bit in the 32-bit protection register represents 1/32 of the total program flash. 0 Program flash region is protected. 1 Program flash region is not protected 29.34.7 EEPROM Protection Register (FTFL_FEPROT) For devices with FlexNVM: The FEPROT register defines which EEPROM regions of the FlexRAM are protected against program and erase operations. Protected EEPROM regions cannot have their content changed by writing to it. Unprotected regions can be changed by writing to the FlexRAM. For devices with program flash only: This register is reserved and not used. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 667 General Business Information

Page 668

Address: 4002_0000h base + 16h offset = 4002_0016h Bit 7 6 5 4 3 2 1 0 Read EPROT Write Reset x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • FTFL_FEPROT field descriptions Field Description 7–0 EPROT EEPROM Region Protect For devices with program flash only: Reserved For devices with FlexNVM: Individual EEPROM regions can be protected from alteration by setting the associated EPROT bit. The EPROT bits are not used when the FlexNVM Partition Code is set to data flash only. When the FlexNVM Partition Code is set to data flash and EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured EEPROM data (see the EEPROM Data Set Size parameter description). In NVM Normal mode: The protection can only be increased. This means that currently-unprotected memory can be protected, but currently-protected memory cannot be unprotected. Since unprotected regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special mode : All bits of the FEPROT register are writable without restriction. Unprotected areas can be protected and protected areas can be unprotected. Restriction: Never write to the FEPROT register while a command is running (CCIF=0). Reset: During the reset sequence, the FEPROT register is loaded with the contents of the FlexRAM protection byte in the Flash Configuration Field located in program flash. The flash basis for the reset values is signified by X in the register diagram. To change the EEPROM protection that will be loaded during the reset sequence, the sector of program flash that contains the Flash Configuration Field must be unprotected; then the EEPROM protection byte must be erased and reprogrammed. Trying to alter data by writing to any protected area in the EEPROM results in a protection violation error and sets the FPVIOL bit in the FSTAT register. 0 For devices with program flash only: Reserved. For devices with FlexNVM: EEPROM region is protected 1 For devices with program flash only: Reserved. For devices with FlexNVM: EEPROM region is not protected Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 668 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 669

29.34.8 Data Flash Protection Register (FTFL_FDPROT) The FDPROT register defines which data flash regions are protected against program and erase operations. Protected Flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any flash command. Unprotected regions can be changed by both program and erase operations. Address: 4002_0000h base + 17h offset = 4002_0017h Bit 7 6 5 4 3 2 1 0 Read DPROT Write Reset x* x* x* x* x* x* x* x*

Notes: x = Undefined at reset. • FTFL_FDPROT field descriptions Field Description 7–0 DPROT Data Flash Region Protect For devices with program flash only: Reserved. For devices with FlexNVM:Individual data flash regions can be protected from program and erase operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of the partitioned data flash memory space. The granularity of data flash protection cannot be less than the data flash sector size. If an unused DPROT bit is set, the Erase all Blocks command does not execute and the FSTAT[FPVIOL] flag is set. In NVM Normal mode: The protection can only be increased, meaning that currently unprotected memory can be protected but currently protected memory cannot be unprotected. Since unprotected regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FDPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special mode: All bits of the FDPROT register are writable without restriction. Unprotected areas can be protected and protected areas can be unprotected. Restriction: The user must never write to the FDPROT register while a command is running (CCIF=0). Reset: During the reset sequence, the FDPROT register is loaded with the contents of the data flash protection byte in the Flash Configuration Field located in program flash memory. The flash basis for the reset values is signified by X in the register diagram. To change the data flash protection that will be loaded during the reset sequence, unprotect the sector of program flash that contains the Flash Configuration Field. Then, erase and reprogram the data flash protection byte. Trying to alter data with the program and erase commands in any protected area in the data flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of the data flash memory (see the Erase Flash Block command description) is not possible if the data flash memory contains any protected region or if the FlexNVM block has been partitioned for EEPROM. 0 Data Flash region is protected 1 Data Flash region is not protected Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 669 General Business Information

Page 670

29.4 Functional Description The following sections describe functional details of the flash memory module. 29.4.1 Program Flash Memory Swap For devices that only contain program flash memory: The user can configure the logical memory map of the program flash space such that either of the two physical program flash blocks can exist at relative address 0x0000. This swap feature enables the lower half of the logical program flash space to be operational while the upper half is being updated for future use. The Swap Control command handles swapping the two logical P-Flash memory blocks within the memory map. See Swap Control Command for details. 29.4.2 Flash Protection Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers: • FPROTn — Four registers that protect 32 regions of the program flash memory as shown in the following figure Program flash size / 32 Program flash size / 32 Program flash size / 32 Program flash size / 32 Program flash size / 32 Program flash size / 32 Program flash size / 32 FPROT3[PROT0] 0x0_0000 FPROT3[PROT1] FPROT3[PROT2] FPROT3[PROT3] FPROT0[PROT29] FPROT0[PROT31] FPROT0[PROT30] Program flash Last program flash address Figure 29-27. Program flash protection Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 670 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 671

• FDPROT — • For 2n data flash sizes, protects eight regions of the data flash memory as shown in the following figure Data flash size / 8 DPROT0 0x0_0000 DPROT1 DPROT2 DPROT3 DPROT5 DPROT7 DPROT6 FlexNVM Last data flash address Data flash size / 8 Data flash size / 8 Data flash size / 8 Data flash size / 8 Data flash size / 8 Data flash size / 8 Data flash size / 8 DPROT4 EEPROM backup EEPROM backup size (DEPART) Last FlexNVM address Figure 29-28. Data flash protection • For the non-2n data flash sizes (192KB and 224KB), the protection granularity is 32KB. Therefore, for 192KB data flash size, only the DPROT[5:0] bits are used, and for 224KB data flash size, only the DPROT[6:0] bits are used. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 671 General Business Information

Page 672

32KB DPROT0 0x0_0000 DPROT1 DPROT2 DPROT3 DPROT5 DPROT6 224KB data flash 0x3_7FFF 32KB 32KB 32KB 32KB 32KB 32KB DPROT4 32KB EEPROM backup 0x3_FFFF 32KB DPROT0 0x0_0000 DPROT1 DPROT2 DPROT3 DPROT5 192KB data flash 0x2_FFFF 32KB 32KB 32KB 32KB 32KB DPROT4 64KB EEPROM backup 0x3_FFFF Figure 29-29. Data flash protection (192 and 224KB) • FEPROT — Protects eight regions of the EEPROM memory as shown in the following figure EEPROM size / 8 EPROT0 0x0_0000 EPROT1 EPROT2 EPROT5 EPROT7 EPROT6 FlexRAM Last EEPROM address EEPROM size / 8 EEPROM size / 8 EEPROM size / 8 EEPROM size / 8 EEPROM size / 8 EEPROM size / 8 EEPROM size / 8 EPROT3 EPROT4 Unavailable EEPROM size (EEESIZE) Last FlexRAM address Figure 29-30. EEPROM protection Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 672 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 673

29.4.3 FlexNVM Description This section describes the FlexNVM memory. This section does not apply for devices that contain only program flash memory. 29.4.3.1 FlexNVM Block Partitioning for FlexRAM The user can configure the FlexNVM block as either: • Basic data flash, • EEPROM flash records to support the built-in EEPROM feature, or • A combination of both. The user's FlexNVM configuration choice is specified using the Program Partition command described in Program Partition Command. CAUTION While different partitions of the FlexNVM block are available, the intention is that a single partition choice is used throughout the entire lifetime of a given application. The FlexNVM partition code choices affect the endurance and data retention characteristics of the device. 29.4.3.2 EEPROM User Perspective The EEPROM system is shown in the following figure. File system handler User access (effective EEPROM) FlexRAM EEPROM backup with 1KByte erase sectors Figure 29-31. Top Level EEPROM Architecture To handle varying customer requirements, the FlexRAM and FlexNVM blocks can be split into partitions as shown in the figure below.

EEPROM partition (EEESIZE) — The amount of FlexRAM used for EEPROM can be set from 0 Bytes (no EEPROM) to the maximum FlexRAM size (see Table 29-2). The remainder of the FlexRAM is not accessible while the FlexRAM is Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 673 General Business Information

Page 674

configured for EEPROM (see Set FlexRAM Function Command). The EEPROM partition grows upward from the bottom of the FlexRAM address space. 2. Data flash partition (DEPART) — The amount of FlexNVM memory used for data flash can be programmed from 0 bytes (all of the FlexNVM block is available for EEPROM backup) to the maximum size of the FlexNVM block (see Table 29-4). 3. FlexNVM EEPROM partition — The amount of FlexNVM memory used for EEPROM backup, which is equal to the FlexNVM block size minus the data flash memory partition size. The EEPROM backup size must be at least 16 times the EEPROM partition size in FlexRAM. 4. EEPROM split factor (EEESPLIT) — The FlexRAM partitioned for EEPROM can be divided into two subsystems, each backed by half of the partitioned EEPROM backup. One subsystem (A) is 1/8, 1/4, or 1/2 of the partitioned FlexRAM with the remainder belonging to the other subsystem (B). The partition information (EEESIZE, DEPART, EEESPLIT) is stored in the data flash IFR and is programmed using the Program Partition command (see Program Partition Command). Typically, the Program Partition command is executed only once in the lifetime of the device. Data flash memory is useful for applications that need to quickly store large amounts of data or store data that is static. The EEPROM partition in FlexRAM is useful for storing smaller amounts of data that will be changed often. The EEPROM partition in FlexRAM can be further sub-divided to provide subsystems, each backed by the same amount of EEPROM backup with subsystem A having higher endurance if the split factor is 1/8 or 1/4. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 674 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 675

FlexRAM Data flash 1 DEPART /2 FlexNVM Block 1 Subsystem B EEESIZE Unavailable EEPROM partition A DEPART /2 FlexNVM Block 0 Subsystem A Size of EEPROM partition A = EEESIZE x EEESPLIT Data flash 0 and 1 interleaved Data flash 0 EEPROM partition B EEPROM backup A EEESPLIT = 1/8, 1/4, or 1/2 Size of EEPROM partition B = EEESIZE x (1 - EEESPLIT) EEPROM backup B Figure 29-32. FlexRAM to FlexNVM Memory Mapping with 2 Sub-systems 29.4.3.3 EEPROM Implementation Overview Out of reset with the FSTAT[CCIF] bit clear, the partition settings (EEESIZE, DEPART, EEESPLIT) are read from the data flash IFR and the EEPROM file system is initialized accordingly. The EEPROM file system locates all valid EEPROM data records in EEPROM backup and copies the newest data to FlexRAM. The FSTAT[CCIF] and FCNFG[EEERDY] bits are set after data from all valid EEPROM data records is copied to the FlexRAM. After the CCIF bit is set, the FlexRAM is available for read or write access. When configured for EEPROM use, writes to an unprotected location in FlexRAM invokes the EEPROM file system to program a new EEPROM data record in the EEPROM backup memory in a round-robin fashion. As needed, the EEPROM file system identifies the EEPROM backup sector that is being erased for future use and partially erases that EEPROM backup sector. After a write to the FlexRAM, the FlexRAM is not accessible until the FSTAT[CCIF] bit is set. The FCNFG[EEERDY] bit will also be set. If enabled, the interrupt associated with the FSTAT[CCIF] bit can be used to determine when the FlexRAM is available for read or write access. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 675 General Business Information

Page 676

After a sector in EEPROM backup is full of EEPROM data records, EEPROM data records from the sector holding the oldest data are gradually copied over to a previously- erased EEPROM backup sector. When the sector copy completes, the EEPROM backup sector holding the oldest data is tagged for erase. 29.4.3.4 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = × Write_efficiency × n EEPROM – 2 × EEESPLIT × EEESIZE EEESPLIT × EEESIZE nvmcycd where • Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance) • EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command • EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • nnvmcycd — data flash cycling endurance (the following graph assumes 10,000 cycles) Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 676 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 677

Figure 29-33. EEPROM backup writes to FlexRAM 29.4.4 Interrupts The flash memory module can generate interrupt requests to the MCU upon the occurrence of various flash events. These interrupt events and their associated status and control bits are shown in the following table. Table 29-30. Flash Interrupt Sources Flash Event Readable Status Bit Interrupt Enable Bit Flash Command Complete FSTAT[CCIF] FCNFG[CCIE] Flash Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE] Note Vector addresses and their relative interrupt priority are determined at the MCU level. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 677 General Business Information

Page 678

29.4.5 Flash Operation in Low-Power Modes 29.4.5.1 Wait Mode When the MCU enters wait mode, the flash memory module is not affected. The flash memory module can recover the MCU from wait via the command complete interrupt (see Interrupts). 29.4.5.2 Stop Mode When the MCU requests stop mode, if a flash command is active (CCIF = 0) the command execution completes before the MCU is allowed to enter stop mode. CAUTION The MCU should never enter stop mode while any flash command is running (CCIF = 0). NOTE While the MCU is in very-low-power modes (VLPR, VLPW, VLPS), the flash memory module does not accept flash commands. 29.4.6 Functional Modes of Operation The flash memory module has two operating modes: NVM Normal and NVM Special. The operating mode affects the command set availability (see Table 29-31). Refer to the Chip Configuration details of this device for how to activate each mode. 29.4.7 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 678 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 679

The MCU must not read from the flash memory while commands are running (as evidenced by CCIF=0) on that block. Read data cannot be guaranteed from a flash block while any command is processing within that block. The block arbitration logic detects any simultaneous access and reports this as a read collision error (see the FSTAT[RDCOLERR] bit). 29.4.8 Read While Write (RWW) The following simultaneous accesses are allowed for devices with FlexNVM: • The user may read from the program flash memory while commands (typically program and erase operations) are active in the data flash and FlexRAM memory space. • The MCU can fetch instructions from program flash during both data flash program and erase operations and while EEPROM backup data is maintained by the EEPROM commands. • Conversely, the user may read from data flash and FlexRAM while program and erase commands are executing on the program flash. • When configured as traditional RAM, writes to the FlexRAM are allowed during program and data flash operations. Simultaneous data flash operations and FlexRAM writes, when FlexRAM is used for EEPROM, are not possible. The following simultaneous accesses are allowed for devices with program flash only: • The user may read from one logical program flash memory space while flash commands are active in the other logical program flash memory space. Simultaneous operations are further discussed in Allowed Simultaneous Flash Operations. 29.4.9 Flash Program and Erase All flash functions except read require the user to setup and launch a flash command through a series of peripheral bus writes. The user cannot initiate any further flash commands until notified that the current command has completed. The flash command structure and operation are detailed in Flash Command Operations. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 679 General Business Information

Page 680

29.4.10 Flash Command Operations Flash command operations are typically used to modify flash memory contents. The next sections describe: • The command write sequence used to set flash command parameters and launch execution • A description of all flash commands available 29.4.10.1 Command Write Sequence Flash commands are specified using a command write sequence illustrated in Figure 29-34. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be zero and the CCIF flag must read 1 to verify that any previous command has completed. If CCIF is zero, the previous command execution is still active, a new command write sequence cannot be started, and all writes to the FCCOB registers are ignored. 29.4.10.1.1 Load the FCCOB Registers The user must load the FCCOB registers with all parameters required by the desired flash command. The individual registers that make up the FCCOB data set can be written in any order. 29.4.10.1.2 Launch the Command by Clearing CCIF Once all relevant command parameters have been loaded, the user launches the command by clearing the FSTAT[CCIF] bit by writing a '1' to it. The CCIF flag remains zero until the flash command completes. The FSTAT register contains a blocking mechanism that prevents a new command from launching (can't clear CCIF) if the previous command resulted in an access error (FSTAT[ACCERR]=1) or a protection violation (FSTAT[FPVIOL]=1). In error scenarios, two writes to FSTAT are required to initiate the next command: the first write clears the error flags, the second write clears CCIF. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 680 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 681

29.4.10.1.3 Command Execution and Error Reporting The command processing has several steps:

The flash memory module reads the command code and performs a series of parameter checks and protection checks, if applicable, which are unique to each command. If the parameter check fails, the FSTAT[ACCERR] (access error) flag is set. ACCERR reports invalid instruction codes and out-of bounds addresses. Usually, access errors suggest that the command was not set-up with valid parameters in the FCCOB register group. Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, the FSTAT[FPVIOL] (protection error) flag is set. Command processing never proceeds to execution when the parameter or protection step fails. Instead, command processing is terminated after setting the FSTAT[CCIF] bit.
If the parameter and protection checks pass, the command proceeds to execution. Run-time errors, such as failure to erase verify, may occur during the execution phase. Run-time errors are reported in the FSTAT[MGSTAT0] bit. A command may have access errors, protection errors, and run-time errors, but the run-time errors are not seen until all access and protection errors have been corrected.
Command execution results, if applicable, are reported back to the user via the FCCOB and FSTAT registers.
The flash memory module sets the FSTAT[CCIF] bit signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 681 General Business Information

Page 682

Clear the CCIF to launch the command Write 0x80 to FSTAT register Clear the old errors Access Error and Protection Violation Check FCCOB ACCERR/ FPVIOL Set? EXIT Write to the FCCOB registers to load the required command parameter. More Parameters? Availability Check Results from previous command Read: FSTAT register Write 0x30 to FSTAT register no yes no yes Previous command complete? no CCIF = ‘1’? yes START Figure 29-34. Generic Flash Command Write Sequence Flowchart 29.4.10.2 Flash Commands The following table summarizes the function of all flash commands. If the program flash, data flash, or FlexRAM column is marked with an 'X', the flash command is relevant to that particular memory resource. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 682 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 683

FCMD Command Program flash 0 Program flash 1 (Devices with only program flash) Data flash (Devices with FlexNVM) FlexRAM (Devices with FlexNVM) Function 0x00 Read 1s Block × × × Verify that a program flash or data flash block is erased. FlexNVM block must not be partitioned for EEPROM. 0x01 Read 1s Section × × × Verify that a given number of program flash or data flash locations from a starting address are erased. 0x02 Program Check × × × Tests previously- programmed locations at margin read levels. 0x03 Read Resource IFR, ID IFR IFR Read 4 bytes from program flash IFR, data flash IFR, or version ID. 0x06 Program Longword × × × Program 4 bytes in a program flash block or a data flash block. 0x08 Erase Flash Block × × × Erase a program flash block or data flash block. An erase of any flash block is only possible when unprotected. FlexNVM block must not be partitioned for EEPROM. 0x09 Erase Flash Sector × × × Erase all bytes in a program flash or data flash sector. Table continues on the next page... Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 683 General Business Information

Page 684

FCMD Command Program flash 0 Program flash 1 (Devices with only program flash) Data flash (Devices with FlexNVM) FlexRAM (Devices with FlexNVM) Function 0x0B Program Section × × × × Program data from the Section Program Buffer to a program flash or data flash block. 0x40 Read 1s All Blocks × × × Verify that all program flash, data flash blocks, EEPROM backup data records, and data flash IFR are erased then release MCU security. 0x41 Read Once IFR Read 4 bytes of a dedicated 64 byte field in the program flash 0 IFR. 0x43 Program Once IFR One-time program of 4 bytes of a dedicated 64- byte field in the program flash 0 IFR. Table continues on the next page... Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 684 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 685

FCMD Command Program flash 0 Program flash 1 (Devices with only program flash) Data flash (Devices with FlexNVM) FlexRAM (Devices with FlexNVM) Function 0x44 Erase All Blocks × × × × Erase all program flash blocks, program flash 1 IFR, data flash blocks, FlexRAM, EEPROM backup data records, and data flash IFR. Then, verify- erase and release MCU security. NOTE: An erase is only possible when all memory locations are unprotected. 0x45 Verify Backdoor Access Key × × Release MCU security after comparing a set of user-supplied security keys to those stored in the program flash. 0x46 Swap Control × × Handles swap- related activities 0x80 Program Partition IFR × Program the FlexNVM Partition Code and EEPROM Data Set Size into the data flash IFR. Format all EEPROM backup data sectors allocated for EEPROM. Initialize the FlexRAM. Table continues on the next page... Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 685 General Business Information

Page 686

FCMD Command Program flash 0 Program flash 1 (Devices with only program flash) Data flash (Devices with FlexNVM) FlexRAM (Devices with FlexNVM) Function 0x81 Set FlexRAM Function x × Switches FlexRAM function between RAM and EEPROM. When switching to EEPROM, FlexNVM is not available while valid data records are being copied from EEPROM backup to FlexRAM. NOTE FlexRAM, or Programming Acceleration RAM, is used during PGMSEC command. 29.4.10.3 Flash Commands by Mode The following table shows the flash commands that can be executed in each flash operating mode. Table 29-31. Flash Commands by Mode FCMD Command NVM Normal NVM Special Unsecure Secure MEEN=10 Unsecure Secure MEEN=10 0x00 Read 1s Block × × × × — — 0x01 Read 1s Section × × × × — — 0x02 Program Check × × × × — — 0x03 Read Resource × × × × — — 0x06 Program Longword × × × × — — 0x08 Erase Flash Block × × × × — — 0x09 Erase Flash Sector × × × × — — 0x0B Program Section × × × × — — 0x40 Read 1s All Blocks × × × × × — 0x41 Read Once × × × × — — 0x43 Program Once × × × × — — Table continues on the next page... Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 686 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 687

Table 29-31. Flash Commands by Mode (continued) FCMD Command NVM Normal NVM Special Unsecure Secure MEEN=10 Unsecure Secure MEEN=10 0x44 Erase All Blocks × × × × × — 0x45 Verify Backdoor Access Key × × × × — — 0x46 Swap Control × × × × — — 0x80 Program Partition × × × × — — 0x81 Set FlexRAM Function × × × × — — 29.4.10.4 Allowed Simultaneous Flash Operations Only the operations marked 'OK' in the following table are permitted to run simultaneously on the program flash, data flash, and FlexRAM memories. Some operations cannot be executed simultaneously because certain hardware resources are shared by the memories. The priority has been placed on permitting program flash reads while program and erase operations execute on the FlexNVM and FlexRAM. This provides read (program flash) while write (FlexNVM, FlexRAM) functionality. For devices containing FlexNVM: Table 29-32. Allowed Simultaneous Memory Operations Program Flash Data Flash FlexRAM Read Program Sector Erase Read Program Sector Erase Read E-Write1 R-Write2 Program flash Read — OK OK OK Program — OK OK OK3 Sector Erase — OK OK OK Data flash Read OK OK — Program OK — OK OK Sector Erase OK — OK OK FlexRAM Read OK OK OK OK — E-Write1 OK — R-Write2 OK OK OK OK — 1. When FlexRAM configured for EEPROM (writes are effectively multi-cycle operations). 2. When FlexRAM configured as traditional RAM (writes are single-cycle operations). 3. When FlexRAM configured as traditional RAM, writes to the RAM are ignored while the Program Section command is active (CCIF = 0). For devices containing program flash only: Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 687 General Business Information

Page 688

Table 29-33. Allowed Simultaneous Memory Operations Program Flash 0 Program Flash 1 Read Program Sector Erase Read Program Sector Erase Program flash 0 Read — OK OK Program — OK Sector Erase — OK Program flash 1 Read OK OK — Program OK — Sector Erase OK — 29.4.11 Margin Read Commands The Read-1s commands (Read 1s All Blocks, Read 1s Block, and Read 1s Section) and the Program Check command have a margin choice parameter that allows the user to apply non-standard read reference levels to the program flash and data flash array reads performed by these commands. Using the preset 'user' and 'factory' margin levels, these commands perform their associated read operations at tighter tolerances than a 'normal' read. These non-standard read levels are applied only during the command execution. All simple (uncommanded) flash array reads to the MCU always use the standard, un- margined, read reference level. Only the 'normal' read level should be employed during normal flash usage. The non- standard, 'user' and 'factory' margin levels should be employed only in special cases. They can be used during special diagnostic routines to gain confidence that the device is not suffering from the end-of-life data loss customary of flash memory devices. Erased ('1') and programmed ('0') bit states can degrade due to elapsed time and data cycling (number of times a bit is erased and re-programmed). The lifetime of the erased states is relative to the last erase operation. The lifetime of the programmed states is measured from the last program time. The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. The 'user' margin is a small delta to the normal read reference level. 'User' margin levels can be employed to check that flash memory contents have adequate margin for normal level read operations. If unexpected read results are encountered when checking flash memory contents at the 'user' margin levels, loss of information might soon occur during 'normal' readout. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 688 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 689

The 'factory' margin is a bigger deviation from the norm, a more stringent read criteria that should only be attempted immediately (or very soon) after completion of an erase or program command, early in the cycling life. 'Factory' margin levels can be used to check that flash memory contents have adequate margin for long-term data retention at the normal level setting. If unexpected results are encountered when checking flash memory contents at 'factory' margin levels, the flash memory contents should be erased and reprogrammed. CAUTION Factory margin levels must only be used during verify of the initial factory programming. 29.4.12 Flash Command Description This section describes all flash commands that can be launched by a command write sequence. The flash memory module sets the FSTAT[ACCERR] bit and aborts the command execution if any of the following illegal conditions occur: • There is an unrecognized command code in the FCCOB FCMD field. • There is an error in a FCCOB field for the specific commands. Refer to the error handling table provided for each command. Ensure that the ACCERR and FPVIOL bits in the FSTAT register are cleared prior to starting the command write sequence. As described in Launch the Command by Clearing CCIF, a new command cannot be launched while these error flags are set. Do not attempt to read a flash block while the flash memory module is running a command (CCIF = 0) on that same block. The flash memory module may return invalid data to the MCU with the collision error flag (FSTAT[RDCOLERR]) set. When required by the command, address bit 23 selects between: • program flash (=0) • data flash (=1) CAUTION Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 689 General Business Information

Page 690

29.4.12.1 Read 1s Block Command The Read 1s Block command checks to see if an entire program flash or data flash block has been erased to the specified margin level. The FCCOB flash address bits determine which logical block is erase-verified. Table 29-34. Read 1s Block Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x00 (RD1BLK) 1 Flash address [23:16] in the flash block to be verified 2 Flash address [15:8] in the flash block to be verified 3 Flash address [7:0]1 in the flash block to be verified 4 Read-1 Margin Choice 1. Must be longword aligned (Flash address [1:0] = 00). After clearing CCIF to launch the Read 1s Block command, the flash memory module sets the read margin for 1s according to Table 29-35 and then reads all locations within the selected program flash or data flash block. When the data flash is targeted, DEPART must be set for no EEPROM, else the Read 1s Block command aborts setting the FSTAT[ACCERR] bit. If the flash memory module fails to read all 1s (i.e. the flash block is not fully erased), the FSTAT[MGSTAT0] bit is set. The CCIF flag sets after the Read 1s Block operation has completed. Table 29-35. Margin Level Choices for Read 1s Block Read Margin Choice Margin Level Description 0x00 Use the 'normal' read level for 1s 0x01 Apply the 'User' margin to the normal read-1 level 0x02 Apply the 'Factory' margin to the normal read-1 level Table 29-36. Read 1s Block Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Program flash is selected and the address is out of program flash range FSTAT[ACCERR] Data flash is selected and the address is out of data flash range FSTAT[ACCERR] Data flash is selected with EEPROM enabled FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 690 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 691

29.4.12.2 Read 1s Section Command The Read 1s Section command checks if a section of program flash or data flash memory is erased to the specified read margin level. The Read 1s Section command defines the starting address and the number of phrases to be verified. Table 29-37. Read 1s Section Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x01 (RD1SEC) 1 Flash address [23:16] of the first phrase to be verified 2 Flash address [15:8] of the first phrase to be verified 3 Flash address [7:0]1 of the first phrase to be verified 4 Number of phrases to be verified [15:8] 5 Number of phrases to be verified [7:0] 6 Read-1 Margin Choice 1. Must be phrase aligned (Flash address [2:0] = 000). Upon clearing CCIF to launch the Read 1s Section command, the flash memory module sets the read margin for 1s according to Table 29-38 and then reads all locations within the specified section of flash memory. If the flash memory module fails to read all 1s (i.e. the flash section is not erased), the FSTAT[MGSTAT0] bit is set. The CCIF flag sets after the Read 1s Section operation completes. Table 29-38. Margin Level Choices for Read 1s Section Read Margin Choice Margin Level Description 0x00 Use the 'normal' read level for 1s 0x01 Apply the 'User' margin to the normal read-1 level 0x02 Apply the 'Factory' margin to the normal read-1 level Table 29-39. Read 1s Section Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin code is supplied FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not phrase aligned FSTAT[ACCERR] The requested section crosses a Flash block boundary FSTAT[ACCERR] The requested number of phrases is zero FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 691 General Business Information

Page 692

29.4.12.3 Program Check Command The Program Check command tests a previously programmed program flash or data flash longword to see if it reads correctly at the specified margin level. Table 29-40. Program Check Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x02 (PGMCHK) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0]1 4 Margin Choice 8 Byte 0 expected data 9 Byte 1 expected data A Byte 2 expected data B Byte 3 expected data 1. Must be longword aligned (Flash address [1:0] = 00). Upon clearing CCIF to launch the Program Check command, the flash memory module sets the read margin for 1s according to Table 29-41, reads the specified longword, and compares the actual read data to the expected data provided by the FCCOB. If the comparison at margin-1 fails, the FSTAT[MGSTAT0] bit is set. The flash memory module then sets the read margin for 0s, re-reads, and compares again. If the comparison at margin-0 fails, the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Program Check operation completes. The supplied address must be longword aligned (the lowest two bits of the byte address must be 00): • Byte 3 data is written to the supplied byte address ('start'), • Byte 2 data is programmed to byte address start+0b01, • Byte 1 data is programmed to byte address start+0b10, • Byte 0 data is programmed to byte address start+0b11. NOTE See the description of margin reads, Margin Read Commands Table 29-41. Margin Level Choices for Program Check Read Margin Choice Margin Level Description 0x01 Read at 'User' margin-1 and 'User' margin-0 0x02 Read at 'Factory' margin-1 and 'Factory' margin-0 Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 692 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 693

Table 29-42. Program Check Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] An invalid margin choice is supplied FSTAT[ACCERR] Either of the margin reads does not match the expected data FSTAT[MGSTAT0] 29.4.12.4 Read Resource Command The Read Resource command allows the user to read data from special-purpose memory resources located within the flash memory module. The special-purpose memory resources available include program flash IFR space, data flash IFR space, and the Version ID field. Each resource is assigned a select code as shown in Table 29-44. Table 29-43. Read Resource Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x03 (RDRSRC) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0]1 Returned Values 4 Read Data [31:24] 5 Read Data [23:16] 6 Read Data [15:8] 7 Read Data [7:0] User-provided values 8 Resource Select Code (see Table 29-44) 1. Must be longword aligned (Flash address [1:0] = 00). Table 29-44. Read Resource Select Codes Resource Select Code Description Resource Size Local Address Range 0x00 Program Flash 0 IFR 256 Bytes 0x00_0000 - 0x00_00FF Table continues on the next page... Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 693 General Business Information

Page 694

Table 29-44. Read Resource Select Codes (continued) Resource Select Code Description Resource Size Local Address Range 0x00 Program Flash Swap IFR1 256 Bytes 0x02_0000 - 0x02_00FF (512 KB of program flash) 0x01_0000 - 0x01_00FF (256 KB of program flash) 0x00_8000 - 0x00_80FF (128 KB of program flash) 0x00 Data Flash 0 IFR2 256 Bytes 0x80_0000 - 0x80_00FF 0x013 Version ID 8 Bytes 0x00_0000 - 0x00_0007 1. This is for devices with program flash only. 2. This is for devices with FlexNVM. 3. Located in program flash 0 reserved space. After clearing CCIF to launch the Read Resource command, four consecutive bytes are read from the selected resource at the provided relative address and stored in the FCCOB register. The CCIF flag sets after the Read Resource operation completes. The Read Resource command exits with an access error if an invalid resource code is provided or if the address for the applicable area is out-of-range. Table 29-45. Read Resource Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid resource code is entered FSTAT[ACCERR] Flash address is out-of-range for the targeted resource. FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] 29.4.12.5 Program Longword Command The Program Longword command programs four previously-erased bytes in the program flash memory or in the data flash memory using an embedded algorithm. CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 694 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 695

Table 29-46. Program Longword Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x06 (PGM4) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0]1 4 Byte 0 program value 5 Byte 1 program value 6 Byte 2 program value 7 Byte 3 program value 1. Must be longword aligned (Flash address [1:0] = 00). Upon clearing CCIF to launch the Program Longword command, the flash memory module programs the data bytes into the flash using the supplied address. The swap indicator address in each program flash block is implicitly protected from programming. The targeted flash locations must be currently unprotected (see the description of the FPROT and FDPROT registers) to permit execution of the Program Longword operation. The programming operation is unidirectional. It can only move NVM bits from the erased state ('1') to the programmed state ('0'). Erased bits that fail to program to the '0' state are flagged as errors in FSTAT[MGSTAT0]. The CCIF flag is set after the Program Longword operation completes. The supplied address must be longword aligned (flash address [1:0] = 00): • Byte 3 data is written to the supplied byte address ('start'), • Byte 2 data is programmed to byte address start+0b01, • Byte 1 data is programmed to byte address start+0b10, and • Byte 0 data is programmed to byte address start+0b11. Table 29-47. Program Longword Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] Flash address points to a protected area FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 695 General Business Information

Page 696

29.4.12.6 Erase Flash Block Command The Erase Flash Block operation erases all addresses in a single program flash or data flash block. Table 29-48. Erase Flash Block Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x08 (ERSBLK) 1 Flash address [23:16] in the flash block to be erased 2 Flash address [15:8] in the flash block to be erased 3 Flash address [7:0]1 in the flash block to be erased 1. Must be longword aligned (Flash address [1:0] = 00). Upon clearing CCIF to launch the Erase Flash Block command, the flash memory module erases the main array of the selected flash block and verifies that it is erased. When the data flash is targeted, DEPART must be set for no EEPROM (see Table 29-4) else the Erase Flash Block command aborts setting the FSTAT[ACCERR] bit. The Erase Flash Block command aborts and sets the FSTAT[FPVIOL] bit if any region within the block is protected (see the description of the FPROT and FDPROT registers). The swap indicator address in each program flash block is implicitly protected from block erase unless the swap system is in the UPDATE or UPDATE-ERASED state and the program flash block being erased is the non-active block. If the erase verify fails, FSTAT[MGSTAT0] is set. The CCIF flag will set after the Erase Flash Block operation has completed. Table 29-49. Erase Flash Block Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] Program flash is selected and the address is out of program flash range FSTAT[ACCERR] Data flash is selected and the address is out of data flash range FSTAT[ACCERR] Data flash is selected with EEPROM enabled FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] Any area of the selected flash block is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 29.4.12.7 Erase Flash Sector Command The Erase Flash Sector operation erases all addresses in a flash sector. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 696 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 697

Table 29-50. Erase Flash Sector Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x09 (ERSSCR) 1 Flash address [23:16] in the flash sector to be erased 2 Flash address [15:8] in the flash sector to be erased 3 Flash address [7:0]1 in the flash sector to be erased 1. Must be phrase aligned (flash address [2:0] = 000). After clearing CCIF to launch the Erase Flash Sector command, the flash memory module erases the selected program flash or data flash sector and then verifies that it is erased. The Erase Flash Sector command aborts if the selected sector is protected (see the description of the FPROT and FDPROT registers). The swap indicator address in each program flash block is implicitly protected from sector erase unless the swap system is in the UPDATE or UPDATE-ERASED state and the program flash sector containing the swap indicator address being erased is the non-active block. If the erase-verify fails the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase Flash Sector operation completes. The Erase Flash Sector command is suspendable (see the FCNFG[ERSSUSP] bit and Figure 29-35). Table 29-51. Erase Flash Sector Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid Flash address is supplied FSTAT[ACCERR] Flash address is not phrase aligned FSTAT[ACCERR] The selected program flash or data flash sector is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 29.4.12.7.1 Suspending an Erase Flash Sector Operation To suspend an Erase Flash Sector operation set the FCNFG[ERSSUSP] bit (see Flash Configuration Field Description) when CCIF is clear and the CCOB command field holds the code for the Erase Flash Sector command. During the Erase Flash Sector operation (see Erase Flash Sector Command), the flash memory module samples the state of the ERSSUSP bit at convenient points. If the flash memory module detects that the ERSSUSP bit is set, the Erase Flash Sector operation is suspended and the flash memory module sets CCIF. While ERSSUSP is set, all writes to flash registers are ignored except for writes to the FSTAT and FCNFG registers. If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend request has been made, the flash memory module clears the ERSSUSP bit prior to setting CCIF. When an Erase Flash Sector operation has been Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 697 General Business Information

Page 698

successfully suspended, the flash memory module sets CCIF and leaves the ERSSUSP bit set. While CCIF is set, the ERSSUSP bit can only be cleared to prevent the withdrawal of a suspend request before the flash memory module has acknowledged it. 29.4.12.7.2 Resuming a Suspended Erase Flash Sector Operation If the ERSSUSP bit is still set when CCIF is cleared to launch the next command, the previous Erase Flash Sector operation resumes. The flash memory module acknowledges the request to resume a suspended operation by clearing the ERSSUSP bit. A new suspend request can then be made by setting ERSSUSP. A single Erase Flash Sector operation can be suspended and resumed multiple times. There is a minimum elapsed time limit between the request to resume the Erase Flash Sector operation (CCIF is cleared) and the request to suspend the operation again (ERSSUSP is set). This minimum time period is required to ensure that the Erase Flash Sector operation will eventually complete. If the minimum period is continually violated, i.e. the suspend requests come repeatedly and too quickly, no forward progress is made by the Erase Flash Sector algorithm. The resume/suspend sequence runs indefinitely without completing the erase. 29.4.12.7.3 Aborting a Suspended Erase Flash Sector Operation The user may choose to abort a suspended Erase Flash Sector operation by clearing the ERSSUSP bit prior to clearing CCIF for the next command launch. When a suspended operation is aborted, the flash memory module starts the new command using the new FCCOB contents. While FCNFG[ERSSUSP] is set, a write to the FlexRAM while FCNFG[EEERDY] is set clears ERSSUSP and aborts the suspended operation. The FlexRAM write operation is executed by the flash memory module. Note Aborting the erase leaves the bitcells in an indeterminate, partially-erased state. Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 698 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 699

Restore Erase Algo Clear SUSPACK = 0 ERSSCR Command (Write FCCOB) Launch/Resume Command (Clear CCIF) CCIF = 1? Request Suspend (Set ERSSUSP) Interrupt? CCIF = 1? Service Interrupt (Read Flash) ERSSUSP=0? Next Command (Write FCCOB) Clear ERSSUSP Enter with CCIF = 1 Resume ERSSCR No Memory Controller Command Processing SUSPACK=1 Clear ERSSUSP Execute Yes DONE? No ERSSUSP=1? Save Erase Algo Set CCIF No Yes Start New Resume Erase? No, Abort User Cmd Interrupt/Suspend Set SUSPACK = 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR Completed ERSSCR Suspended ERSSUSP=1 ERSSUSP: Bit in FCNFG register SUSPACK: Internal Suspend Acknowledge No Yes Yes No Yes No ERSSCR Completed ERSSUSP=0 Figure 29-35. Suspend and Resume of Erase Flash Sector Operation Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 699 General Business Information

Page 700

29.4.12.8 Program Section Command The Program Section operation programs the data found in the section program buffer to previously erased locations in the flash memory using an embedded algorithm. Data is preloaded into the section program buffer by writing to the FlexRAM while it is set to function as traditional RAM or the programming acceleration RAM (see Flash Sector Programming). The section program buffer is limited to the lower half of the RAM. Data written to the upper half of the RAM is ignored and may be overwritten during Program Section command execution. CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. Table 29-52. Program Section Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x0B (PGMSEC) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0]1 4 Number of phrases to program [15:8] 5 Number of phrases to program [7:0] 1. Must be phrase aligned (Flash address [2:0] = 000). After clearing CCIF to launch the Program Section command, the flash memory module blocks access to the programming acceleration RAM (program flash only devices) or FlexRAM (FlexNVM devices) and programs the data residing in the section program buffer into the flash memory starting at the flash address provided. The starting address must be unprotected (see the description of the FPROT and FDPROT registers) to permit execution of the Program Section operation. The swap indicator address in each program flash block is implicitly protected from programming. If the swap indicator address is encountered during the Program Section operation, it is bypassed without setting FPVIOL and the contents are not programmed. Programming, which is not allowed to cross a flash sector boundary, continues until all requested phrases have been programmed. The Program Section command also verifies that after programming, all bits requested to be programmed are programmed. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 700 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 701

After the Program Section operation completes, the CCIF flag is set and normal access to the RAM is restored. The contents of the section program buffer may be changed by the Program Section operation. Table 29-53. Program Section Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not phrase aligned FSTAT[ACCERR] The requested section crosses a program flash sector boundary FSTAT[ACCERR] The requested number of phrases is zero FSTAT[ACCERR] The space required to store data for the requested number of phrases is more than half the size of the programming acceleration RAM (program flash only devices) or FlexRAM (FlexNVM devices) FSTAT[ACCERR] The FlexRAM is not set to function as a traditional RAM, i.e. set if RAMRDY=0 FSTAT[ACCERR] The flash address falls in a protected area FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 29.4.12.8.1 Flash Sector Programming The process of programming an entire flash sector using the Program Section command is as follows:

If required, for FlexNVM devices, execute the Set FlexRAM Function command to make the FlexRAM available as traditional RAM and initialize the FlexRAM to all ones.
Launch the Erase Flash Sector command to erase the flash sector to be programmed.
Beginning with the starting address of the programming acceleration RAM (program flash only devices) or FlexRAM (FlexNVM devices), sequentially write enough data to the RAM to fill an entire flash sector. This area of the RAM serves as the section program buffer. NOTE In step 1, the section program buffer was initialized to all ones, the erased state of the flash memory. The section program buffer can be written to while the operation launched in step 2 is executing, i.e. while CCIF = 0.
Execute the Program Section command to program the contents of the section program buffer into the selected flash sector.
If a flash sector is larger than half the RAM, repeat steps 3 and 4 until the sector is completely programmed.
To program additional flash sectors, repeat steps 2 through 4. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 701 General Business Information

Page 702

To restore EEPROM functionality for FlexNVM devices, execute the Set FlexRAM Function command to make the FlexRAM available as EEPROM. 29.4.12.9 Read 1s All Blocks Command The Read 1s All Blocks command checks if the program flash blocks, data flash blocks, EEPROM backup records, and data flash IFR have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e. all data reads as '1'. Table 29-54. Read 1s All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x40 (RD1ALL) 1 Read-1 Margin Choice After clearing CCIF to launch the Read 1s All Blocks command, the flash memory module : • sets the read margin for 1s according to Table 29-55, • checks the contents of the program flash, data flash, EEPROM backup records, and data flash IFR are in the erased state. If the flash memory module confirms that these memory resources are erased, security is released by setting the FSEC[SEC] field to the unsecure state. The security byte in the flash configuration field (see Flash Configuration Field Description) remains unaffected by the Read 1s All Blocks command. If the read fails, i.e. all memory resources are not in the fully erased state, the FSTAT[MGSTAT0] bit is set. The EEERDY and RAMRDY bits are clear during the Read 1s All Blocks operation and are restored at the end of the Read 1s All Blocks operation. The CCIF flag sets after the Read 1s All Blocks operation has completed. Table 29-55. Margin Level Choices for Read 1s All Blocks Read Margin Choice Margin Level Description 0x00 Use the 'normal' read level for 1s 0x01 Apply the 'User' margin to the normal read-1 level 0x02 Apply the 'Factory' margin to the normal read-1 level Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 702 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 703

Table 29-56. Read 1s All Blocks Command Error Handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] 29.4.12.10 Read Once Command The Read Once command provides read access to a reserved 64-byte field located in the program flash 0 IFR (see Program Flash IFR Map and Program Once Field). Access to this field is via 16 records, each 4 bytes long. The Read Once field is programmed using the Program Once command described in Program Once Command. Table 29-57. Read Once Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x41 (RDONCE) 1 Read Once record index (0x00 - 0x0F) 2 Not used 3 Not used Returned Values 4 Read Once byte 0 value 5 Read Once byte 1 value 6 Read Once byte 2 value 7 Read Once byte 3 value After clearing CCIF to launch the Read Once command, a 4-byte Read Once record is read from the program flash IFR and stored in the FCCOB register. The CCIF flag is set after the Read Once operation completes. Valid record index values for the Read Once command range from 0x00 to 0x0F. During execution of the Read Once command, any attempt to read addresses within the program flash block containing this 64-byte field returns invalid data. The Read Once command can be executed any number of times. Table 29-58. Read Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 703 General Business Information

Page 704

29.4.12.11 Program Once Command The Program Once command enables programming to a reserved 64-byte field in the program flash 0 IFR (see Program Flash IFR Map and Program Once Field). Access to the Program Once field is via 16 records, each 4 bytes long. The Program Once field can be read using the Read Once command (see Read Once Command) or using the Read Resource command (see Read Resource Command). Each Program Once record can be programmed only once since the program flash 0 IFR cannot be erased. Table 29-59. Program Once Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x43 (PGMONCE) 1 Program Once record index (0x00 - 0x0F) 2 Not Used 3 Not Used 4 Program Once Byte 0 value 5 Program Once Byte 1 value 6 Program Once Byte 2 value 7 Program Once Byte 3 value After clearing CCIF to launch the Program Once command, the flash memory module first verifies that the selected record is erased. If erased, then the selected record is programmed using the values provided. The Program Once command also verifies that the programmed values read back correctly. The CCIF flag is set after the Program Once operation has completed. The reserved program flash 0 IFR location accessed by the Program Once command cannot be erased and any attempt to program one of these records when the existing value is not Fs (erased) is not allowed. Valid record index values for the Program Once command range from 0x00 to 0x0F. During execution of the Program Once command, any attempt to read addresses within the program flash block containing this 64-byte field returns invalid data. Table 29-60. Program Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] The requested record has already been programmed to a non-FFFF value1 FSTAT[ACCERR] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 1. If a Program Once record is initially programmed to 0xFFFF_FFFF, the Program Once command is allowed to execute again on that same record. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 704 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 705

29.4.12.12 Erase All Blocks Command The Erase All Blocks operation erases all flash memory, initializes the FlexRAM, verifies all memory contents, and releases MCU security. Table 29-61. Erase All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x44 (ERSALL) After clearing CCIF to launch the Erase All Blocks command, the flash memory module erases all program flash memory, program flash swap IFR space, data flash memory, data flash IFR space, EEPROM backup memory, and FlexRAM, then verifies that all are erased. If the flash memory module verifies that all flash memories and the FlexRAM were properly erased, security is released by setting the FSEC[SEC] field to the unsecure state and the FCNFG[RAMRDY] bit is set. The Erase All Blocks command aborts if any flash or FlexRAM region is protected. The swap indicator address in each program flash block is not implicitly protected from the Erase All Blocks operation. The security byte and all other contents of the flash configuration field (see Flash Configuration Field Description) are erased by the Erase All Blocks command. If the erase-verify fails, the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase All Blocks operation completes. Table 29-62. Erase All Blocks Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] Any region of the program flash memory, data flash memory, or FlexRAM is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 29.4.12.12.1 Triggering an Erase All External to the Flash Memory Module The functionality of the Erase All Blocks command is also available in an uncommanded fashion outside of the flash memory. Refer to the device's Chip Configuration details for information on this functionality. Before invoking the external erase all function, the FSTAT[ACCERR and PVIOL] flags must be cleared and the FCCOB0 register must not contain 0x44. When invoked, the erase-all function erases all program flash memory, program flash swap IFR space, data flash memory, data flash IFR space, EEPROM backup, and FlexRAM regardless of the Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 705 General Business Information

Page 706

protection settings or if the swap system has been initialized. If the post-erase verify passes, the routine then releases security by setting the FSEC[SEC] field register to the unsecure state and the FCNFG[RAMRDY] bit sets. The security byte in the Flash Configuration Field is also programmed to the unsecure state. The status of the erase-all request is reflected in the FCNFG[ERSAREQ] bit. The FCNFG[ERSAREQ] bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in Erase All Blocks Command. 29.4.12.13 Verify Backdoor Access Key Command The Verify Backdoor Access Key command only executes if the mode and security conditions are satisfied (see Flash Commands by Mode). Execution of the Verify Backdoor Access Key command is further qualified by the FSEC[KEYEN] bits. The Verify Backdoor Access Key command releases security if user-supplied keys in the FCCOB match those stored in the Backdoor Comparison Key bytes of the Flash Configuration Field (see Flash Configuration Field Description). The column labelled Flash Configuration Field offset address shows the location of the matching byte in the Flash Configuration Field. Table 29-63. Verify Backdoor Access Key Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] Flash Configuration Field Offset Address 0 0x45 (VFYKEY) 1-3 Not Used 4 Key Byte 0 0x0_0000 5 Key Byte 1 0x0_0001 6 Key Byte 2 0x0_0002 7 Key Byte 3 0x0_0003 8 Key Byte 4 0x0_0004 9 Key Byte 5 0x0_0005 A Key Byte 6 0x0_0006 B Key Byte 7 0x0_0007 After clearing CCIF to launch the Verify Backdoor Access Key command, the flash memory module checks the FSEC[KEYEN] bits to verify that this command is enabled. If not enabled, the flash memory module sets the FSTAT[ACCERR] bit and terminates. If the command is enabled, the flash memory module compares the key provided in FCCOB to the backdoor comparison key in the Flash Configuration Field. If the backdoor keys match, the FSEC[SEC] field is changed to the unsecure state and security is released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are immediately aborted Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 706 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 707

and the FSTAT[ACCERR] bit is (again) set to 1 until a reset of the flash memory module module occurs. If the entire 8-byte key is all zeros or all ones, the Verify Backdoor Access Key command fails with an access error. The CCIF flag is set after the Verify Backdoor Access Key operation completes. Table 29-64. Verify Backdoor Access Key Command Error Handling Error Condition Error Bit The supplied key is all-0s or all-Fs FSTAT[ACCERR] An incorrect backdoor key is supplied FSTAT[ACCERR] Backdoor key access has not been enabled (see the description of the FSEC register) FSTAT[ACCERR] This command is launched and the backdoor key has mismatched since the last power down reset FSTAT[ACCERR] 29.4.12.14 Swap Control Command The Swap Control command handles specific activities associated with swapping the two logical program flash memory blocks within the memory map. Table 29-65. Swap Control Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x46 (SWAP) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 1 4 Swap Control Code: 0x01 - Initialize Swap System 0x02 - Set Swap in Update State 0x04 - Set Swap in Complete State 0x08 - Report Swap Status Returned values 5 Current Swap State: 0x00 - Uninitialized 0x01 - Ready 0x02 - Update 0x03 - Update-Erased 0x04 - Complete 6 Current Swap Block Status: 0x00 - Program flash block 0 at 0x0_0000 0x01 - Program flash block 1 at 0x0_0000 Table continues on the next page... Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 707 General Business Information

Page 708

Table 29-65. Swap Control Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] 7 Next Swap Block Status (after any reset): 0x00 - Program flash block 0 at 0x0_0000 0X01 - Program flash block 1 at 0x0_0000 1. Must be phrase-aligned (Flash address [2:0] = 000). Upon clearing CCIF to launch the Swap Control command, the flash memory module will handle swap-related activities based on the swap control code provided in FCCOB4 as follows: • 0x01 (Initialize Swap System to UPDATE-ERASED State) - After verifying that the current swap state is UNINITIALIZED and that the flash address provided is in Program flash block 0 but not in the Flash Configuration Field, the flash address (shifted with bits[2:0] removed) will be programmed into the IFR Swap Field found in program flash swap IFR. After the swap indicator address has been programmed into the IFR Swap Field, the swap enable word will be programmed to 0x0000. After the swap enable word has been programmed, the swap indicator, located within the Program flash block 0 address provided, will be programmed to 0xFF00. • 0x02 (Progress Swap to UPDATE State) - After verifying that the current swap state is READY and that the flash address provided matches the one stored in the IFR Swap Field, the swap indicator located within bits [15:0] of the flash address in the currently active program flash block will be programmed to 0xFF00. • 0x04 (Progress Swap to COMPLETE State) - After verifying that the current swap state is UPDATE-ERASED and that the flash address provided matches the one stored in the IFR Swap Field, the swap indicator located within bits [15:0] of the flash address in the currently active program flash block will be programmed to 0x0000. Before executing with this swap control code, the user must erase the non- active swap indicator using the Erase Flash Block or Erase Flash Sector commands and update the application code or data as needed. The non-active swap indicator will be checked at the erase verify level and if the check fails, the current swap state will be changed to UPDATE with FSTAT[ACCERR] set. • 0x08 (Report Swap System Status) - After verifying that the flash address provided matches the one stored in the IFR Swap Field, the status of the swap system will be reported as follows: • FCCOB5 (Current Swap State) - indicates the current swap state based on the status of the swap enable word and the swap indicators. If the FSTAT[MGSTAT0] flag is set after command completion, the swap state returned was not successfully transitioned from and the appropriate swap command code must be attempted again. If the current swap state is UPDATE Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 708 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 709

and the non-active swap indicator is 0xFFFF, the current swap state is changed to UPDATE-ERASED. • FCCOB6 (Current Swap Block Status) - indicates which program flash block is currently located at relative flash address 0x0_0000. • FCCOB7 (Next Swap Block Status) - indicates which program flash block will be located at relative flash address 0x0_0000 after the next reset of the flash memory module. NOTE It is recommended that the user execute the Swap Control command to report swap status (code 0x08) after any reset to determine if issues with the swap system were detected during the swap state determination procedure. NOTE It is recommended that the user write 0xFF to FCCOB5, FCCOB6, and FCCOB7 since the Swap Control command will not always return the swap state and status fields when an access error is detected. The swap indicators are implicitly protected from being programmed during Program Longword or Program Section command operations and are implicitly unprotected during Swap Control command operations. The swap indicators are implicitly protected from being erased during Erase Flash Block and Erase Flash Sector command operations unless the swap indicator being erased is in the non-active program flash block and the swap system is in the UPDATE or UPDATE-ERASED state. Once the swap system has been initialized, the Erase All Blocks command can be used to uninitialize the swap system. Table 29-66. Swap Control Command Error Handling Error Condition Swap Control Code Error Bit Command not available in current mode/security1 All FSTAT[ACCERR] Flash address is not in program flash block 0 All FSTAT[ACCERR] Flash address is in the Flash Configuration Field All FSTAT[ACCERR] Flash address is not phrase aligned All FSTAT[ACCERR] Flash address does not match the swap indicator address in the IFR 2, 4 FSTAT[ACCERR] Swap initialize requested when swap system is not in the uninitialized state 1 FSTAT[ACCERR] Swap update requested when swap system is not in the ready state 2 FSTAT[ACCERR] Swap complete requested when swap system is not in the update-erased state 4 FSTAT[ACCERR] An undefined swap control code is provided

FSTAT[ACCERR] Table continues on the next page... Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 709 General Business Information

Page 710

Table 29-66. Swap Control Command Error Handling (continued) Error Condition Swap Control Code Error Bit Any errors have been encountered during the swap determination and program-verify operations 1, 2, 4 FSTAT[MGSTAT0] Any brownouts were detected during the swap determination procedure 8 FSTAT[MGSTAT0] 1. Returned fields will not be updated, i.e. no swap state or status reporting Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 710 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 711

Reset 2 Erase 4 Erase Reset Block0 Active States Block1 Active States Ready0 Update0 Complete0 Ready1 UpErs1 Complete1 1 0xFFFF 0x0000 0xFF00 0x0000 0x0000 0xFFFF 0x0000 0xFFFF 0xFFFF 0xFF00 0xFFFF 0x0000 Swap State Indicator0 Indicator1 Legend Swap Control Code 4 UpErs0 0xFF00 0xFFFF 2 Update1 0x0000 0xFF00 Erase: ERSBLK or ERSSCR commands Reset: POR, VLLSx exit, warm/system reset Uninitialized0 0xFFFF 0xFFFF Figure 29-36. Valid Swap State Sequencing Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 711 General Business Information

Page 712

Table 29-67. Swap State Report Mapping Case Swap Enable Field1 Swap Indicator 01 Swap Indicator 11 Swap State2 State Code MGST AT0 Active Block 1 0xFFFF

Uninitialized 0 0 0 2 0x0000 0xFF00 0x0000 Update 2 0 0 3 0x0000 0xFF00- 0xFFFF Update-Erased 3 0 0 4 0x0000 0x0000 0xFFFF3 Complete4 4 0 0 5 0x0000 0x0000 0xFFFF Ready5 1 0 1 6 0x0000 0x0000 0xFF00 Update 2 0 1 7 0x0000 0xFFFF 0xFF00 Update-Erased 3 0 1 8 0x0000 0xFFFF3 0x0000 Complete4 4 0 1 9 0x0000 0xFFFF 0x0000 Ready5 1 0 0 10 0xXXXX

Uninitialized 0 1 0 11 0x0000 0xFFFF 0xFFFF Uninitialized 0 1 0 12 0x0000 0xFFXX 0xFFFF Ready 1 1 0 13 0x0000 0xFFXX 0x0000 Ready 1 1 0 146 0x0000 0xXXXX 0x0000 Ready 1 1 0 156 0x0000 0xFFFF 0xFFXX Ready 1 1 1 16 0x0000 0x0000 0xFFXX Ready 1 1 1 176 0x0000 0x0000 0xXXXX Ready 1 1 1 18 0x0000 0xFF00 0xFFFF7 Update 2 1 0 19 0x0000 0xFF00 0xXXXX Update 2 1 0 20 0x0000 0xFF(00) 0xFFXX Update 2 1 0 216 0x0000 0x0000 0x0000 Update 2 1 0 226 0x0000 0xXXXX 0xXXXX Update 2 1 0 23 0x0000 0xFFFF7 0xFF00 Update 2 1 1 24 0x0000 0xXXXX 0xFF00 Update 2 1 1 25 0x0000 0xFFXX 0xFF(00) Update 2 1 1 26 0x0000 0xXX00 0xFFFF Update-Erased 3 1 0 27 0x0000 0xXXXX 0xFFFF Update-Erased 3 1 0 28 0x0000 0xFFFF 0xXX00 Update-Erased 3 1 1 29 0x0000 0xFFFF 0xXXXX Update-Erased 3 1 1 1. 0xXXXX, 0xFFXX, 0xXX00 indicates a non-valid value was read; 0xFF(00) indicates more 0’s than other indicator (if same number of 0’s, then swap system defaults to block 0 active) 2. Cases 10-29 due to brownout (abort) detected during program or erase steps related to swap 3. Must read 0xFFFF with erase verify level before transition to Complete allowed 4. No reset since successful Swap Complete execution 5. Reset after successful Swap Complete execution 6. Not a valid case 7. Fails to read 0xFFFF at erase verify level Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 712 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 713

29.4.12.14.1 Swap State Determination During the reset sequence, the state of the swap system is determined by evaluating the IFR Swap Field in the program flash swap IFR and the swap indicators located in each of the program flash blocks at the swap indicator address stored in the IFR Swap Field. Table 29-68. Program Flash 1 IFR Swap Field Address Range Size (Bytes) Field Description 0x00 – 0x01 2 Swap Enable Word 0x02 – 0x03 2 Swap Indicator Address 0x04 – 0xFF 252 Reserved 29.4.12.15 Program Partition Command The Program Partition command prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the FlexRAM. The Program Partition command must not be launched from flash memory, since flash memory resources are not accessible during Program Partition command execution. CAUTION While different partitions of the FlexNVM are available, the intention is that a single partition choice is used throughout the entire lifetime of a given application. The FlexNVM Partition Code choices affect the endurance and data retention characteristics of the device. Table 29-69. Program Partition Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x80 (PGMPART) 1 Not Used 2 Not Used 3 Not Used 4 EEPROM Data Size Code1 5 FlexNVM Partition Code2 1. See Table 29-70 and EEPROM Data Set Size 2. See Table 29-71 and Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 713 General Business Information

Page 714

Table 29-70. Valid EEPROM Data Set Size Codes EEPROM Data Size Code (FCCOB4)1 EEPROM Data Set Size (Bytes) Subsystem A + B FCCOB4[EEESPLIT] FCCOB4[EEESIZE] 11 0xF 02 00 0x9 4 + 28 01 0x9 8 + 24 10 0x9 16 + 16 11 0x9 16 + 16 00 0x8 8 + 56 01 0x8 16 + 48 10 0x8 32 + 32 11 0x8 32 + 32 00 0x7 16 + 112 01 0x7 32 + 96 10 0x7 64 + 64 11 0x7 64 + 64 00 0x6 32 + 224 01 0x6 64 + 192 10 0x6 128 + 128 11 0x6 128 + 128 00 0x5 64 + 448 01 0x5 128 + 384 10 0x5 256 + 256 11 0x5 256 + 256 00 0x4 128 + 896 01 0x4 256 + 768 10 0x4 512 + 512 11 0x4 512 + 512 00 0x3 256 + 1,792 01 0x3 512 + 1,536 10 0x3 1,024 + 1,024 11 0x3 1,024 + 1,024 00 0x2 512 + 3,584 01 0x2 1,024 + 3,072 10 0x2 2,048 + 2,048 11 0x2 2,048 + 2,048 1. FCCOB4[7:6] = 00 2. EEPROM Data Set Size must be set to 0 bytes when the FlexNVM Partition Code is set for no EEPROM. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 714 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 715

Table 29-71. Valid FlexNVM Partition Codes FlexNVM Partition Code (FCCOB5[DEPART])1 Data flash Size (Kbytes) EEPROM backup Size (Kbytes) 0000 256 0 0011 224 32 0100 192 64 0101 128 128 0110 0 256 1000 0 256 1011 32 224 1100 64 192 1101 128 128 1110 256 0 1. FCCOB5[7:4] = 0000 After clearing CCIF to launch the Program Partition command, the flash memory module first verifies that the EEPROM Data Size Code and FlexNVM Partition Code in the data flash IFR are erased. If erased, the Program Partition command erases the contents of the FlexNVM memory. If the FlexNVM is to be partitioned for EEPROM backup, the allocated EEPROM backup sectors are formatted for EEPROM use. Finally, the partition codes are programmed into the data flash IFR using the values provided. The Program Partition command also verifies that the partition codes read back correctly after programming. If the FlexNVM is partitioned for EEPROM backup, the EEERDY flag will set with RAMRDY clear. If the FlexNVM is not partitioned for EEPROM backup, the RAMRDY flag will set with EEERDY clear. The CCIF flag is set after the Program Partition operation completes. Prior to launching the Program Partition command, the data flash IFR must be in an erased state, which can be accomplished by executing the Erase All Blocks command or by an external request (see Erase All Blocks Command). The EEPROM Data Size Code and FlexNVM Partition Code are read using the Read Resource command (see Read Resource Command). Table 29-72. Program Partition Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] The EEPROM data size and FlexNVM partition code bytes are not initially 0xFFFF FSTAT[ACCERR] Invalid EEPROM Data Size Code is entered (see Table 29-70 for valid codes) FSTAT[ACCERR] Invalid FlexNVM Partition Code is entered (see Table 29-71 for valid codes) FSTAT[ACCERR] FlexNVM Partition Code = full data flash (no EEPROM) and EEPROM Data Size Code allocates FlexRAM for EEPROM FSTAT[ACCERR] Table continues on the next page... Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 715 General Business Information

Page 716

Table 29-72. Program Partition Command Error Handling (continued) Error Condition Error Bit FlexNVM Partition Code allocates space for EEPROM backup, but EEPROM Data Size Code allocates no FlexRAM for EEPROM FSTAT[ACCERR] FCCOB4[7:6] != 00 FSTAT[ACCERR] FCCOB5[7:4] != 0000 FSTAT[ACCERR] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 29.4.12.16 Set FlexRAM Function Command The Set FlexRAM Function command changes the function of the FlexRAM: • When not partitioned for EEPROM, the FlexRAM is typically used as traditional RAM. • When partitioned for EEPROM, the FlexRAM is typically used to store EEPROM data. Table 29-73. Set FlexRAM Function Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x81 (SETRAM) 1 FlexRAM Function Control Code (see Table 29-74) Table 29-74. FlexRAM Function Control FlexRAM Function Control Code Action 0xFF Make FlexRAM available as RAM: • Clear the FCNFG[EEERDY] and FCNFG[RAMRDY] flags • Write a background of ones to all FlexRAM locations • Set the FCNFG[RAMRDY] flag 0x00 Make FlexRAM available for EEPROM: • Clear the FCNFG[EEERDY] and FCNFG[RAMRDY] flags • Write a background of ones to all FlexRAM locations • Copy-down existing EEPROM data to FlexRAM • Set the FCNFG[EEERDY] flag After clearing CCIF to launch the Set FlexRAM Function command, the flash memory module sets the function of the FlexRAM based on the FlexRAM Function Control Code. When making the FlexRAM available as traditional RAM, the flash memory module clears the FCNFG[EEERDY] and FCNFG[RAMRDY] flags, overwrites the contents of the entire FlexRAM with a background pattern of all ones, and sets the Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 716 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 717

FCNFG[RAMRDY] flag. The state of the FEPROT register does not prevent the FlexRAM from being overwritten. When the FlexRAM is set to function as a RAM, normal read and write accesses to the FlexRAM are available. When large sections of flash memory need to be programmed, e.g. during factory programming, the FlexRAM can be used as the Section Program Buffer for the Program Section command (see Program Section Command). When making the FlexRAM available for EEPROM, the flash memory module clears the FCNFG[EEERDY] and FCNFG[RAMRDY] flags, overwrites the contents of the FlexRAM allocated for EEPROM with a background pattern of all ones, and copies the existing EEPROM data from the EEPROM backup record space to the FlexRAM. After completion of the EEPROM copy-down, the FCNFG[EEERDY] flag is set. When the FlexRAM is set to function as EEPROM, normal read and write access to the FlexRAM is available, but writes to the FlexRAM also invoke EEPROM activity. The CCIF flag is set after the Set FlexRAM Function operation completes. Table 29-75. Set FlexRAM Function Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] FlexRAM Function Control Code is not defined FSTAT[ACCERR] FlexRAM Function Control Code is set to make the FlexRAM available for EEPROM, but FlexNVM is not partitioned for EEPROM FSTAT[ACCERR] 29.4.13 Security The flash memory module provides security information to the MCU based on contents of the FSEC security register. The MCU then limits access to flash memory resources as defined in the device's Chip Configuration details. During reset, the flash memory module initializes the FSEC register using data read from the security byte of the Flash Configuration Field (see Flash Configuration Field Description). The following fields are available in the FSEC register. The settings are described in the Flash Security Register (FTFL_FSEC) details. Table 29-76. FSEC register fields FSEC field Description KEYEN Backdoor Key Access MEEN Mass Erase Capability FSLACC Freescale Factory Access SEC MCU security Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 717 General Business Information

Page 718

29.4.13.1 Flash Memory Access by Mode and Security The following table summarizes how access to the flash memory module is affected by security and operating mode. Table 29-77. Flash Memory Access Summary Operating Mode Chip Security State Unsecure Secure NVM Normal Full command set NVM Special Full command set Only the Erase All Blocks and Read 1s All Blocks commands. 29.4.13.2 Changing the Security State The security state out of reset can be permanently changed by programming the security byte of the flash configuration field. This assumes that you are starting from a mode where the necessary program flash erase and program commands are available and that the region of the program flash containing the flash configuration field is unprotected. If the flash security byte is successfully programmed, its new value takes affect after the next chip reset. 29.4.13.2.1 Unsecuring the Chip Using Backdoor Key Access The chip can be unsecured by using the backdoor key access feature, which requires knowledge of the contents of the 8-byte backdoor key value stored in the Flash Configuration Field (see Flash Configuration Field Description). If the FSEC[KEYEN] bits are in the enabled state, the Verify Backdoor Access Key command (see Verify Backdoor Access Key Command) can be run; it allows the user to present prospective keys for comparison to the stored keys. If the keys match, the FSEC[SEC] bits are changed to unsecure the chip. The entire 8-byte key cannot be all 0s or all 1s; that is, 0000_0000_0000_0000h and FFFF_FFFF_FFFF_FFFFh are not accepted by the Verify Backdoor Access Key command as valid comparison values. While the Verify Backdoor Access Key command is active, program flash memory is not available for read access and returns invalid data. The user code stored in the program flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 718 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 719

If the KEYEN bits are in the enabled state, the chip can be unsecured by the following backdoor key access sequence:

Follow the command sequence for the Verify Backdoor Access Key command as explained in Verify Backdoor Access Key Command
If the Verify Backdoor Access Key command is successful, the chip is unsecured and the FSEC[SEC] bits are forced to the unsecure state An illegal key provided to the Verify Backdoor Access Key command prohibits further use of the Verify Backdoor Access Key command. A reset of the chip is the only method to re-enable the Verify Backdoor Access Key command when a comparison fails. After the backdoor keys have been correctly matched, the chip is unsecured by changing the FSEC[SEC] bits. A successful execution of the Verify Backdoor Access Key command changes the security in the FSEC register only. It does not alter the security byte or the keys stored in the Flash Configuration Field (Flash Configuration Field Description). After the next reset of the chip, the security state of the flash memory module reverts back to the flash security byte in the Flash Configuration Field. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the program flash protection registers. If the backdoor keys successfully match, the unsecured chip has full control of the contents of the Flash Configuration Field. The chip may erase the sector containing the Flash Configuration Field and reprogram the flash security byte to the unsecure state and change the backdoor keys to any desired value. 29.4.14 Reset Sequence On each system reset the flash memory module executes a sequence which establishes initial values for the flash block configuration parameters, FPROT, FDPROT, FEPROT, FOPT, and FSEC registers and the FCNFG[SWAP, PFLSH, RAMRDY, EEERDY] bits. FSTAT[CCIF] is cleared throughout the reset sequence. The flash memory module holds off CPU access during the reset sequence. Flash reads are possible when the hold is removed. Completion of the reset sequence is marked by setting CCIF which enables flash user commands. If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. Chapter 29 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 719 General Business Information

Page 720

Functional Description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 720 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 721

Chapter 30 External Bus Interface (FlexBus) 30.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. PUBLICATION ERROR: In module memory map tables, register reset values may be incorrect. See the individual register diagrams for accurate reset information. This chapter describes external bus data transfer operations and error conditions. It describes transfers initiated by the core processor (or any other bus master) and includes detailed timing diagrams showing the interaction of signals in supported bus operations. 30.1.1 Definition The FlexBus multifunction external bus interface controller is a hardware module that: • Provides memory expansion and provides connection to external peripherals with a parallel bus • Can be directly connected to the following asynchronous or synchronous slave-only devices with little or no additional circuitry: • External ROMs • Flash memories • Programmable logic devices • Other simple target (slave) devices K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 721 General Business Information

Page 722

30.1.2 Features FlexBus offers the following features: • Six independent, user-programmable chip-select signals (FB_CS5 –FB_CS0) • 8-bit, 16-bit, and 32-bit port sizes with configuration for multiplexed or nonmultiplexed address and data buses • 8-bit, 16-bit, 32-bit, and 16-byte transfers • Programmable burst and burst-inhibited transfers selectable for each chip-select and transfer direction • Programmable address-setup time with respect to the assertion of a chip-select • Programmable address-hold time with respect to the deassertion of a chip-select and transfer direction • Extended address latch enable option to assist with glueless connections to synchronous and asynchronous memory devices 30.2 Signal descriptions This table describes the external signals involved in data-transfer operations. NOTE Not all of the following signals may be available on a particular device. See the Chip Configuration details for information on which signals are available. Table 30-1. FlexBus signal descriptions Signal I/O Function FB_A31–FB_A0 O Address Bus When FlexBus is used in a nonmultiplexed configuration, this is the address bus. When FlexBus is used in a multiplexed configuration, this bus is not used. FB_D31–FB_D0 I/O Data Bus—During the first cycle, this bus drives the upper address byte, addr[31:24]. When FlexBus is used in a nonmultiplexed configuration, this is the data bus, FB_D. When FlexBus is used in a multiplexed configuration, this is the address and data bus, FB_AD. The number of byte lanes carrying the data is determined by the port size associated with the matching chip-select. When FlexBus is used in a multiplexed configuration, the full 32-bit address is driven on the first clock of a bus cycle (address phase). After the first clock, the data is driven on the bus (data phase). During the data phase, the address is driven on the pins not used for data. For example, in 16-bit mode, the lower address is driven on FB_AD15– FB_AD0, and in 8-bit mode, the lower address is driven on FB_AD23–FB_AD0. Table continues on the next page... Signal descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 722 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 723

Table 30-1. FlexBus signal descriptions (continued) Signal I/O Function FB_CS5–FB_CS0 O General Purpose Chip-Selects—Indicate which external memory or peripheral is selected. A particular chip-select is asserted when the transfer address is within the external memory's or peripheral's address space, as defined in CSAR[BA] and CSMR[BAM]. FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 O Byte Enables—Indicate that data is to be latched or driven onto a specific byte lane of the data bus. CSCR[BEM] determines if these signals are asserted on reads and writes or on writes only. For external SRAM or flash devices, the FB_BE outputs should be connected to individual byte strobe signals. FB_OE O Output Enable—Sent to the external memory or peripheral to enable a read transfer. This signal is asserted during read accesses only when a chip-select matches the current address decode. FB_R/W O Read/Write—Indicates whether the current bus operation is a read operation (FB_R/W high) or a write operation (FB_R/W low). FB_TS O Transfer Start—Indicates that the chip has begun a bus transaction and that the address and attributes are valid. An inverted FB_TS is available as an address latch enable (FB_ALE), which indicates when the address is being driven on the FB_AD bus. FB_TS/FB_ALE is asserted for one bus clock cycle. The chip can extend this signal until the first positive clock edge after FB_CS asserts. See CSCR[EXTS] and Extended Transfer Start/Address Latch Enable. FB_ALE O Address Latch Enable—Indicates when the address is being driven on the FB_A bus (inverse of FB_TS). Table continues on the next page... Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 723 General Business Information

Page 724

Table 30-1. FlexBus signal descriptions (continued) Signal I/O Function FB_TSIZ1–FB_TSIZ0 O Transfer Size—Indicates (along with FB_TBST) the data transfer size of the current bus operation. The interface supports 8-, 16-, and 32-bit operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. • 00b = 4 bytes • 01b = 1 byte • 10b = 2 bytes • 11b = 16 bytes (line) For misaligned transfers, FB_TSIZ1–FB_TSIZ0 indicate the size of each transfer. For example, if a 32-bit access through a 32-bit port device occurs at a misaligned offset of 1h, 8 bits are transferred first (FB_TSIZ1–FB_TSIZ0 = 01b), 16 bits are transferred next at offset 2h (FB_TSIZ1–FB_TSIZ0 = 10b), and the final 8 bits are transferred at offset 4h (FB_TSIZ1–FB_TSIZ0 = 01b). For aligned transfers larger than the port size, FB_TSIZ1–FB_TSIZ0 behave as follows: • If bursting is used, FB_TSIZ1–FB_TSIZ0 are driven to the transfer size. • If bursting is inhibited, FB_TSIZ1–FB_TSIZ0 first show the entire transfer size and then show the port size. For burst-inhibited transfers, FB_TSIZ1–FB_TSIZ0 change with each FB_TS assertion to reflect the next transfer size. For transfers to port sizes smaller than the transfer size, FB_TSIZ1–FB_TSIZ0 indicate the size of the entire transfer on the first access and the size of the current port transfer on subsequent transfers. For example, for a 32-bit write to an 8-bit port, FB_TSIZ1– FB_TSIZ0 are 00b for the first transaction and 01b for the next three transactions. If bursting is used for a 32-bit write to an 8-bit port, FB_TSIZ1–FB_TSIZ0 are driven to 00b for the entire transfer. FB_TBST O Transfer Burst—Indicates that a burst transfer is in progress as driven by the chip. A burst transfer can be 2 to 16 beats depending on FB_TSIZ1–FB_TSIZ0 and the port size. Note: When a burst transfer is in progress (FB_TBST = 0b), the transfer size is 16 bytes (FB_TSIZ1–FB_TSIZ0 = 11b), and the address is misaligned within the 16-byte boundary, the external memory or peripheral must be able to wrap around the address. Table continues on the next page... Signal descriptions K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 724 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 725

Table 30-1. FlexBus signal descriptions (continued) Signal I/O Function FB_TA I Transfer Acknowledge—Indicates that the external data transfer is complete. When FB_TA is asserted during a read transfer, FlexBus latches the data and then terminates the transfer. When FB_TA is asserted during a write transfer, the transfer is terminated. If auto-acknowledge is disabled (CSCR[AA] = 0), the external memory or peripheral drives FB_TA to terminate the transfer. If auto-acknowledge is enabled (CSCR[AA] = 1), FB_TA is generated internally after a specified number of wait states, or the external memory or peripheral may assert external FB_TA before the wait-state countdown to terminate the transfer early. The chip deasserts FB_CS one cycle after the last FB_TA is asserted. During read transfers, the external memory or peripheral must continue to drive data until FB_TA is recognized. For write transfers, the chip continues driving data one clock cycle after FB_CS is deasserted. The number of wait states is determined by CSCR or the external FB_TA input. If the external FB_TA is used, the external memory or peripheral has complete control of the number of wait states. Note: External memory or peripherals should assert FB_TA only while the FB_CS signal to the external memory or peripheral is asserted. The CSPMCR register controls muxing of FB_TA with other signals. If auto- acknowledge is not used and CSPMCR does not allow FB_TA control, FlexBus may hang. FB_CLK O FlexBus Clock Output 30.3 Memory Map/Register Definition The following tables describe the registers and bit meanings for configuring chip-select operation. The actual number of chip selects available depends upon the device and its pin configuration. If the device does not support certain chip select signals or the pin is not configured for a chip-select function, then that corresponding set of chip-select registers has no effect on an external pin. Note You must set CSMR0[V] before the chip select registers take effect. A bus error occurs when writing to reserved register locations. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 725 General Business Information

Page 726

FB memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_C000 Chip Select Address Register (FB_CSAR0) 32 R/W 0_0000 _0000h 30.3.1/727 4000_C004 Chip Select Mask Register (FB_CSMR0) 32 R/W 0_0000 _0000h 30.3.2/727 4000_C008 Chip Select Control Register (FB_CSCR0) 32 R/W 0_0000 _0000h 30.3.3/728 4000_C00C Chip Select Address Register (FB_CSAR1) 32 R/W 0_0000 _0000h 30.3.1/727 4000_C010 Chip Select Mask Register (FB_CSMR1) 32 R/W 0_0000 _0000h 30.3.2/727 4000_C014 Chip Select Control Register (FB_CSCR1) 32 R/W 0_0000 _0000h 30.3.3/728 4000_C018 Chip Select Address Register (FB_CSAR2) 32 R/W 0_0000 _0000h 30.3.1/727 4000_C01C Chip Select Mask Register (FB_CSMR2) 32 R/W 0_0000 _0000h 30.3.2/727 4000_C020 Chip Select Control Register (FB_CSCR2) 32 R/W 0_0000 _0000h 30.3.3/728 4000_C024 Chip Select Address Register (FB_CSAR3) 32 R/W 0_0000 _0000h 30.3.1/727 4000_C028 Chip Select Mask Register (FB_CSMR3) 32 R/W 0_0000 _0000h 30.3.2/727 4000_C02C Chip Select Control Register (FB_CSCR3) 32 R/W 0_0000 _0000h 30.3.3/728 4000_C030 Chip Select Address Register (FB_CSAR4) 32 R/W 0_0000 _0000h 30.3.1/727 4000_C034 Chip Select Mask Register (FB_CSMR4) 32 R/W 0_0000 _0000h 30.3.2/727 4000_C038 Chip Select Control Register (FB_CSCR4) 32 R/W 0_0000 _0000h 30.3.3/728 4000_C03C Chip Select Address Register (FB_CSAR5) 32 R/W 0_0000 _0000h 30.3.1/727 4000_C040 Chip Select Mask Register (FB_CSMR5) 32 R/W 0_0000 _0000h 30.3.2/727 4000_C044 Chip Select Control Register (FB_CSCR5) 32 R/W 0_0000 _0000h 30.3.3/728 4000_C060 Chip Select port Multiplexing Control Register (FB_CSPMCR) 32 R/W 0_0000 _0000h 30.3.4/731 Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 726 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 727

30.3.1 Chip Select Address Register (FB_CSARn) Specifies the associated chip-select's base address. Address: 4000_C000h base + 0h offset + (12d × i), where i=0d to 5d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BA 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB_CSARn field descriptions Field Description 31–16 BA Base Address Defines the base address for memory dedicated to the associated chip-select. BA is compared to bits 31– 16 on the internal address bus to determine if the associated chip-select's memory is being accessed. NOTE: Because the FlexBus module is one of the slaves connected to the crossbar switch, it is only accessible within a certain memory range. See the chip memory map for the applicable FlexBus "expansion" address range for which the chip-selects can be active. Set the CSARn and CSMRn registers appropriately before accessing this region. 15–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30.3.2 Chip Select Mask Register (FB_CSMRn) Specifies the address mask and allowable access types for the associated chip-select. Address: 4000_C000h base + 4h offset + (12d × i), where i=0d to 5d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BAM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 WP 0 V W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB_CSMRn field descriptions Field Description 31–16 BAM Base Address Mask Defines the associated chip-select's block size by masking address bits. Table continues on the next page... Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 727 General Business Information

Page 728

FB_CSMRn field descriptions (continued) Field Description 0 The corresponding address bit in CSAR is used in the chip-select decode. 1 The corresponding address bit in CSAR is a don’t care in the chip-select decode. 15–9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8 WP Write Protect Controls write accesses to the address range in the corresponding CSAR. 0 Write accesses are allowed. 1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. 7–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 V Valid Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip- selects do not assert until the V bit is 1b (except for FB_CS0, which acts as the global chip-select). NOTE: At reset, no chip-select other than FB_CS0 can be used until CSMR0[V] is 1b. Afterward, the FB_CS [5:0] signals function as programmed. 0 Chip-select is invalid. 1 Chip-select is valid. 30.3.3 Chip Select Control Register (FB_CSCRn) Controls the auto-acknowledge, address setup and hold times, port size, burst capability, and number of wait states for the associated chip select. NOTE To support the global chip-select ( FB_CS0 ), the CSCR0 reset values differ from the other CSCRs. The reset value of CSCR0 is as follows: • Bits 31–24 are 0b • Bit 23–3 are chip-dependent • Bits 3–0 are 0b See the chip configuration details for your particular chip for information on the exact CSCR0 reset value. Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 728 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 729

Address: 4000_C000h base + 8h offset + (12d × i), where i=0d to 5d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SWS 0 SWSEN EXTS ASET RDAH WRAH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R WS BLS AA PS BEM BSTR BSTW 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB_CSCRn field descriptions Field Description 31–26 SWS Secondary Wait States Used only when the SWSEN bit is 1b. Specifies the number of wait states inserted before an internal transfer acknowledge is generated for a burst transfer (except for the first termination, which is controlled by WS). 25–24 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 23 SWSEN Secondary Wait State Enable 0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. 22 EXTS Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted. 0 Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. 1 Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. 21–20 ASET Address Setup Controls when the chip-select is asserted with respect to assertion of a valid address and attributes. 00 Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). 01 Assert FB_CSn on the second rising clock edge after the address is asserted. 10 Assert FB_CSn on the third rising clock edge after the address is asserted. 11 Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). 19–18 RDAH Read Address Hold or Deselect Controls the address and attribute hold time after the termination during a read cycle that hits in the associated chip-select's address space. Table continues on the next page... Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 729 General Business Information

Page 730

FB_CSCRn field descriptions (continued) Field Description NOTE: • The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a transfer to a port size smaller than the transfer size, the hold time is only added after the last bus cycle. • The number of cycles the address and attributes are held after FB_CSn deassertion depends on the value of the AA bit. 00 When AA is 0b, 1 cycle. When AA is 1b, 0 cycles. 01 When AA is 0b, 2 cycles. When AA is 1b, 1 cycle. 10 When AA is 0b, 3 cycles. When AA is 1b, 2 cycles. 11 When AA is 0b, 4 cycles. When AA is 1b, 3 cycles. 17–16 WRAH Write Address Hold or Deselect Controls the address, data, and attribute hold time after the termination of a write cycle that hits in the associated chip-select's address space. NOTE: The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a transfer to a port size smaller than the transfer size, the hold time is only added after the last bus cycle. 00 1 cycle (default for all but FB_CS0 ) 01 2 cycles 10 3 cycles 11 4 cycles (default for FB_CS0 ) 15–10 WS Wait States Specifies the number of wait states inserted after FlexBus asserts the associated chip-select and before an internal transfer acknowledge is generated (WS = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states). 9 BLS Byte-Lane Shift Specifies if data on FB_AD appears left-aligned or right-aligned during the data phase of a FlexBus access. 0 Not shifted. Data is left-aligned on FB_AD. 1 Shifted. Data is right-aligned on FB_AD. 8 AA Auto-Acknowledge Enable Asserts the internal transfer acknowledge for accesses specified by the chip-select address. NOTE: If AA is 1b for a corresponding FB_CSn and the external system asserts an external FB_TA before the wait-state countdown asserts the internal FB_TA, the cycle is terminated. Burst cycles increment the address bus between each internal termination. NOTE: This field must be 1b if CSPMCR disables FB_TA. 0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 1 Enabled. Internal transfer acknowledge is asserted as specified by WS. 7–6 PS Port Size Specifies the data port width of the associated chip-select, and determines where data is driven during write cycles and where data is sampled during read cycles. 00 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 01 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 730 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 731

FB_CSCRn field descriptions (continued) Field Description 10 16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. 5 BEM Byte-Enable Mode Specifies whether the corresponding FB_BE is asserted for read accesses. Certain memories have byte enables that must be asserted during reads and writes. Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode of byte enable support for these SRAMs. 0 FB_BE is asserted for data write only. 1 FB_BE is asserted for data read and write accesses. 4 BSTR Burst-Read Enable Specifies whether burst reads are enabled for memory associated with each chip select. 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. 3 BSTW Burst-Write Enable Specifies whether burst writes are enabled for memory associated with each chip select. 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8 and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. 2–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30.3.4 Chip Select port Multiplexing Control Register (FB_CSPMCR) Controls the multiplexing of the FlexBus signals. NOTE A bus error occurs when you do any of the following: • Write to a reserved address • Write to a reserved field in this register, or • Access this register using a size other than 32 bits. Address: 4000_C000h base + 60h offset = 4000_C060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GROUP1 GROUP2 GROUP3 GROUP4 GROUP5 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 731 General Business Information

Page 732

FB_CSPMCR field descriptions Field Description 31–28 GROUP1 FlexBus Signal Group 1 Multiplex control Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals. 0000 FB_ALE 0001 FB_CS1 0010 FB_TS Any other value Reserved 27–24 GROUP2 FlexBus Signal Group 2 Multiplex control Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals. 0000 FB_CS4 0001 FB_TSIZ0 0010 FB_BE_31_24 Any other value Reserved 23–20 GROUP3 FlexBus Signal Group 3 Multiplex control Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals. 0000 FB_CS5 0001 FB_TSIZ1 0010 FB_BE_23_16 Any other value Reserved 19–16 GROUP4 FlexBus Signal Group 4 Multiplex control Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals. 0000 FB_TBST 0001 FB_CS2 0010 FB_BE_15_8 Any other value Reserved 15–12 GROUP5 FlexBus Signal Group 5 Multiplex control Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. NOTE: When GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the bus hangs during a transfer. 0000 FB_TA 0001 FB_CS3 . You must also write 1b to CSCR[AA]. 0010 FB_BE_7_0 . You must also write 1b to CSCR[AA]. Any other value Reserved 11–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30.4 Functional description Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 732 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 733

30.4.1 Modes of operation FlexBus supports the following modes of operation: • Multiplexed 32-bit address and 32-bit data • Multiplexed 32-bit address and 16-bit data (non-multiplexed 16-bit address and 16- bit data) • Multiplexed 32-bit address and 8-bit data (non-multiplexed 24-bit address and 8-bit data) • Non-multiplexed 32-bit address and 32-bit data busses 30.4.2 Address comparison When a bus cycle is routed to FlexBus, FlexBus compares the transfer address to the base address and base address mask. This table describes how FlexBus decides to assert a chip-select and complete the bus cycle based on the address comparison. When the transfer address Then FlexBus Matches one address register configuration Asserts the appropriate chip-select, generating a FlexBus bus cycle as defined in the appropriate CSCR. If CSMR[WP] is set and a write access is performed, FlexBus terminates the internal bus cycle with a bus error, does not assert a chip-select, and does not perform an external bus cycle. Does not match a address register configuration Terminates the transfer with a bus error response, does not assert a chip-select, and does not perform a FlexBus cycle. Matches more than one address register configuration Terminates the transfer with a bus error response, does not assert a chip-select, and does not perform a FlexBus cycle. 30.4.3 Address driven on address bus FlexBus always drives a 32-bit address on the FB_AD bus regardless of the external memory's or peripheral's address size. 30.4.4 Connecting address/data lines The external device must connect its address and data lines as follows: Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 733 General Business Information

Page 734

• Address lines • FB_AD from FB_AD0 upward • Data lines • If CSCR[BLS] = 0, FB_AD from FB_AD31 downward • If CSCR[BLS] = 1, FB_AD from FB_AD0 upward 30.4.5 Bit ordering No bit ordering is required when connecting address and data lines to the FB_AD bus. For example, a full 16-bit address/16-bit data device connects its addr15–addr0 to FB_AD16–FB_AD1 and data15–data0 to FB_AD31–FB_AD16. See Data-byte alignment and physical connections for a graphical connection. 30.4.6 Data transfer signals Data transfers between FlexBus and the external memory or peripheral involve these signals: • Address/data bus (FB_AD31–FB_AD0 ) • Control signals (FB_TS/FB_ALE, FB_TA, FB_CSn, FB_OE, FB_R/W, FB_BEn) • Attribute signals (FB_TBST, FB_TSIZ1–FB_TSIZ0) 30.4.7 Signal transitions These signals change on the rising edge of the FlexBus clock (FB_CLK): • Address • Write data • FB_TS/FB_ALE • FB_CSn • All attribute signals FlexBus latches the read data on the rising edge of the clock. 30.4.8 Data-byte alignment and physical connections The device aligns data transfers in FlexBus byte lanes with the number of lanes depending on the data port width. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 734 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 735

The following figure shows the byte lanes that external memory or peripheral connects to and the sequential transfers of a 32-bit transfer for the supported port sizes when byte lane shift is disabled. For example, an 8-bit memory connects to the single lane FB_AD31–FB_AD24 (FB_BE_31_24). A 32-bit transfer through this 8-bit port takes four transfers, starting with the LSB to the MSB. A 32-bit transfer through a 32-bit port requires one transfer on each four-byte lane. External Data Bus 32-Bit Port Memory 16-Bit Port Memory 8-Bit Port Memory Byte Select Byte 0 Byte 1 Byte 2 Byte 3 Byte 1 Byte 0 Byte 3 Byte 2 Byte 3 Byte 2 Byte 1 Byte 0 Driven with address values Driven with address values FB_D[31:24] FB_D[23:16] FB_D[15:8] FB_D[7:0] FB_BE_7_0 FB_BE_15_8 FB_BE_23_16 FB_BE_31_24 Figure 30-23. Connections for external memory port sizes (CSCRn[BLS] = 0) The following figure shows the byte lanes that external memory or peripheral connects to and the sequential transfers of a 32-bit transfer for the supported port sizes when byte lane shift is enabled. 32-Bit Port Memory 16-Bit Port Memory 8-Bit Port Memory Byte 3 Byte 2 Byte 1 Byte 0 Driven with address values Driven with address values Byte 1 Byte 0 Byte 3 Byte 2 Byte 0 Byte 1 Byte 2 Byte 3 External Data Bus Byte Select FB_AD[31:24] FB_AD[23:16] FB_AD15:8] FB_AD[7:0] FB_BE31_24 FB_BE23_16 FB_BE15_8 FB_BE7_0 FB_BE23_16 FB_BE31_24 FB_BE31_24 Figure 30-24. Connections for external memory port sizes (CSCRn[BLS] = 1) Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 735 General Business Information

Page 736

30.4.9 Address/data bus multiplexing FlexBus supports a single 32-bit wide multiplexed address and data bus (FB_AD31– FB_AD0). FlexBus always drives the full 32-bit address on the first clock of a bus cycle. During the data phase, the FB_AD31– FB_AD0 lines used for data are determined by the programmed port size and BLS setting for the corresponding chip-select. FlexBus continues to drive the address on any FB_AD31– FB_AD0 lines not used for data. 30.4.9.1 FlexBus multiplexed operating modes for CSCRn[BLS]=0 This table shows the supported combinations of address and data bus widths when CSCRn[BLS] is 0b. Port size and phase FB_AD 31–24 23–16 15–8 7–0 32-bit Address phase Address Data phase Data 16-bit Address phase Address Data phase Data Address 8-bit Address phase Address Data phase Data Address 30.4.9.2 FlexBus multiplexed operating modes for CSCRn[BLS]=1 This table shows the supported combinations of address and data bus widths when CSCRn[BLS] is 1b. Port size and phase FB_AD 31–24 23–16 15–8 7–0 32-bit Address phase Address Data phase Data 16-bit Address phase Address Data phase Address Data 8-bit Address phase Address Data phase Address Data Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 736 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 737

30.4.10 Data transfer states Basic data transfers occur in four clocks or states. (See Figure 30-26 and Figure 30-28 for examples of basic data transfers.) The FlexBus state machine controls the data-transfer operation. This figure shows the state-transition diagram for basic read and write cycles. S0 S1 S2 Wait States S3 Next Cycle The states are described in this table. State Cycle Description S0 All The read or write cycle is initiated. On the rising clock edge, FlexBus: • Places a valid address on FB_ADn • Asserts FB_TS/FB_ALE • Drives FB_R/W high for a read and low for a write S1 All FlexBus: • Negates FB_TS/FB_ALE on the rising edge of FB_CLK • Asserts FB_CSn • Drives the data on FB_AD31– FB_ADX for writes • Tristates FB_AD31– FB_ADX for reads • Continues to drive the address on FB_AD pins that are unused for data If the external memory or perihperal asserts FB_TA, then the process moves to S2. If FB_TA is not asserted internally or externally, then S1 repeats. Read The external memory or peripheral drives the data before the next rising edge of FB_CLK (the rising edge that begins S2) with FB_TA asserted. S2 All For internal termination, FlexBus negates FB_CSn and the transfer is complete. For external termination, the external memory or peripheral negates FB_TA, and FlexBus negates FB_CSn after the rising edge of FB_CLK at the end of S2. Read FlexBus latches the data on the rising clock edge entering S2. The external memory or peripheral can stop driving the data after this edge or continue to drive the data until the end of S3 or through any additional address hold cycles. S3 All FlexBus invalidates the address, data, and FB_R/W on the rising edge of FB_CLK at the beginning of S3, terminating the transfer. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 737 General Business Information

Page 738

30.4.11 FlexBus Timing Examples Note The timing diagrams throughout this section use signal names that may not be included on your particular device. Ignore these extraneous signals. Note Throughout this section: • FB_D[X] indicates a 32-, 16-, or 8-bit wide data bus • FB_A[Y] indicates an address bus that can be 32, 24, or 16 bits wide. 30.4.11.1 Basic Read Bus Cycle During a read cycle, the MCU receives data from memory or a peripheral device. The following figure shows a read cycle flowchart.

Decode address.
Assert FB_TA (external termination).
Negate FB_TA (external termination).
Set FB_R/W to read.
Assert FB_CSn. (auto-acknowledge/internal termination).
Sample FB_TA low and latch data.
Start next cycle. System
Place address on the external address signals.
Drive data on the external data signals.
Select the appropriate slave device.
Assert transfer start.
Negate transfer start.
FlexBus asserts internal FB_TA Microcontroller Figure 30-25. Read Cycle Flowchart The read cycle timing diagram is shown in the following figure. Note FB_TA does not have to be driven by the external device for internally-terminated bus cycles. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 738 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 739

Note The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses. However, some applications may find this feature beneficial. The address and data busses are muxed between the FlexBus and another module. At the end of the read bus cycles the address signals are indeterminate. Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-26. Basic Read-Bus Cycle 30.4.11.2 Basic Write Bus Cycle During a write cycle, the device sends data to memory or to a peripheral device. The following figure shows the write cycle flowchart. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 739 General Business Information

Page 740

Set FB_R/W to write.
Place address on the external address signals.
Assert transfer start.
Decode address.
Start next cycle.
Sample FB_TA low. External Memory/Peripheral
Latch data on the external address signals.
Assert FB_TA (external termination).
Negate FB_TA (external termination).
Select the appropriate slave device.
Negate transfer start.
Assert FB_CSn.
Drive data.
FlexBus asserts internal FB_TA (auto acknowledge/internal termination). FlexBus Figure 30-27. Write-Cycle Flowchart The following figure shows the write cycle timing diagram. Note The address and data busses are muxed between the FlexBus and another module. At the end of the write bus cycles, the address signals are indeterminate. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 740 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 741

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-28. Basic Write-Bus Cycle 30.4.11.3 Bus Cycle Sizing This section shows timing diagrams for various port size scenarios. 30.4.11.3.1 Bus Cycle Sizing—Byte Transfer, 8-bit Device, No Wait States The following figure illustrates the basic byte read transfer to an 8-bit device with no wait states: • The address is driven on the full FB_AD[31:8] bus in the first clock. • The device tristates FB_AD[31:24] on the second clock and continues to drive address on FB_AD[23:0] throughout the bus cycle. • The external device returns the read data on FB_AD[31:24] and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 741 General Business Information

Page 742

Address Address Data TSIZ = 01 AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-29. Single Byte-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:24]. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 742 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 743

Address Address Data TSIZ=01 AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-30. Single Byte-Write Transfer 30.4.11.3.2 Bus Cycle Sizing—Word Transfer, 16-bit Device, No Wait States The following figure illustrates the basic word read transfer to a 16-bit device with no wait states. • The address is driven on the full FB_AD[31:8] bus in the first clock. • The device tristates FB_AD[31:16] on the second clock and continues to drive address on FB_AD[15:0] throughout the bus cycle. • The external device returns the read data on FB_AD[31:16] and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 743 General Business Information

Page 744

Address Address Data TSIZ = 10 AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-31. Single Word-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:16]. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 744 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 745

Address Address Data TSIZ=10 AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-32. Single Word-Write Transfer 30.4.11.3.3 Bus Cycle Sizing—Longword Transfer, 32-bit Device, No Wait States The following figure depicts a longword read from a 32-bit device. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 745 General Business Information

Page 746

Address Address Data TSIZ = 00 AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-33. Longword-Read Transfer The following figure illustrates the longword write to a 32-bit device. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 746 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 747

Address Address Data TSIZ=00 AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-34. Longword-Write Transfer 30.4.11.4 Timing Variations The FlexBus module has several features that can change the timing characteristics of a basic read- or write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch data. 30.4.11.4.1 Wait States Wait states can be inserted before each beat of a transfer by programming the CSCRn registers. Wait states can give the peripheral or memory more time to return read data or sample write data. The following figures show the basic read and write bus cycles (also shown in Figure 30-26 and Figure 30-31) with the default of no wait states respectively. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 747 General Business Information

Page 748

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-35. Basic Read-Bus Cycle (No Wait States) Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 748 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 749

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-36. Basic Write-Bus Cycle (No Wait States) If wait states are used, the S1 state repeats continuously until the chip-select auto- acknowledge unit asserts internal transfer acknowledge or the external FB_TA is recognized as asserted. The following figures show a read and write cycle with one wait state respectively. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 749 General Business Information

Page 750

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-37. Read-Bus Cycle (One Wait State) Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 750 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 751

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-38. Write-Bus Cycle (One Wait State) 30.4.11.4.2 Address Setup and Hold The timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip-select basis. Each chip-select can be programmed to assert one to four clocks after transfer start/address-latch enable (FB_TS/FB_ALE) is asserted. The following figures show read- and write-bus cycles with two clocks of address setup respectively. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 751 General Business Information

Page 752

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-39. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 752 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 753

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-40. Write-Bus Cycle with Two Clock Address Setup (No Wait States) In addition to address setup, a programmable address hold option for each chip select exists. Address and attributes can be held one to four clocks after chip-select, byte- selects, and output-enable negate. The following figures show read and write bus cycles with two clocks of address hold respectively. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 753 General Business Information

Page 754

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-41. Read Cycle with Two-Clock Address Hold (No Wait States) Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 754 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 755

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-42. Write Cycle with Two-Clock Address Hold (No Wait States) The following figure shows a bus cycle using address setup, wait states, and address hold. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 755 General Business Information

Page 756

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] Figure 30-43. Write Cycle with Two-Clock Address Setup and Two-Clock Hold (One Wait State) 30.4.12 Burst cycles The chip can be programmed to initiate burst cycles if its transfer size exceeds the port size of the selected destination. The initiation of a burst cycle is encoded on the transfer size pins (FB_TSIZ[1:0]). For burst transfers to smaller port sizes, FB_TSIZ[1:0] indicates the size of the entire transfer. For example, with bursting enabled, a 16-bit transfer to an 8-bit port takes two beats (two byte-sized transfers), for which FB_TSIZ[1:0] equals 10b throughout. A 32-bit transfer to an 8-bit port takes four beats (four byte-sized transfers), for which FB_TSIZ[1:0] equals 00b throughout. 30.4.12.1 Enabling and inhibiting burst The CSCRn registers enable bursting for reads, writes, or both. Memory spaces can be declared burst-inhibited for reads and writes by writing 0b to the appropriate CSCRn[BSTR] and CSCRn[BSTW] fields. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 756 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 757

30.4.12.2 Transfer size and port size translation With bursting disabled, any transfer larger than the port size breaks into multiple individual transfers (e.g. <Addr+1><Addr+2>). With bursting enabled, any transfer larger than the port size results in a burst cycle of multiple beats (e.g. ). The following table shows the result of such transfer translations. Port size PS[1:0] Transfer size FB_TSIZ[1:0] Burst-inhibited: Number of transfers Burst enabled: Number of beats 01b (8 bit) 10b (16 bits) 2 00b (32 bits) 4 11b (16 bytes) 16 1Xb (16 bit) 00b (32 bits) 2 11b (16 bytes) 8 00b (32 bit) 11b (line) 4 The FlexBus can support X-1-1-1 burst cycles to maximize system performance, where X is the primary number of wait states (max 63). Delaying termination of the cycle can add wait states. If internal termination is used, different wait state counters can be used for the first access and the following beats. 30.4.12.3 32-bit-Read burst from 8-Bit port 2-1-1-1 (no wait states) The following figure shows a 32-bit read to an 8-bit external chip programmed for burst enable. The transfer results in a 4-beat burst and the data is driven on FB_AD[31:24]. The transfer size is driven at 32-bit (00b) throughout the bus cycle. Note In non-multiplexed address/data mode, the address on FB_A increments only during internally-terminated burst cycles. The first address is driven throughout the entire burst for externally- terminated cycles. In multiplexed address/data mode, the address is driven on FB_AD only during the first cycle for all terminated cycles. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 757 General Business Information

Page 758

Address Address Data TSIZ = 11 AA=1 AA=0 AA=1 AA=0 Data Data Data Add+1 Add+2 Add+3 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] 30.4.12.4 32-bit-Write burst to 8-Bit port 3-1-1-1 (no wait states) The following figure shows a 32-bit write to an 8-bit external chip with burst enabled. The transfer results in a 4-beat burst and the data is driven on FB_AD[31:24]. The transfer size is driven at 32-bit (00b) throughout the bus cycle. Note The first beat of any write burst cycle has at least one wait state. If the bus cycle is programmed for zero wait states (CSCRn[WS] = 0b), one wait state is added. Otherwise, the programmed number of wait states are used. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 758 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 759

Address Address Data TSIZ AA=1 AA=0 AA=1 AA=0 Data Data Data Add+1 Add+2 Add+3 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] 30.4.12.5 32-bit-write burst-inhibited to 8-bit port (no wait states) The following figure shows a 32-bit write to an 8-bit device with burst inhibited. The transfer results in four individual transfers. The transfer size is driven at 32-bit (00b) during the first transfer and at byte (01b) during the next three transfers. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 759 General Business Information

Page 760

Add Data TSIZ = 00 AA=1 AA=0 AA=1 AA=0 Data Data Data TSIZ = 01 Add+3 Add+2 Add+1 Add+1 Add+2 Add+3 Address FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TBST FB_TSIZ[1:0] 30.4.12.6 32-bit-read burst from 8-bit port 3-2-2-2 (one wait state) The following figure illustrates another read burst transfer, but in this case a wait state is added between individual beats. Note CSCRn[WS] determines the number of wait states in the first beat. However, for subsequent beats, the CSCRn[WS] (or CSCRn[SWS] if CSCRn[SWSEN] = 1b) determines the number of wait states. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 760 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 761

Address Address Data TSIZ = 00 AA=1 AA=0 AA=1 AA=0 Data Data Add+1 Add+2 Add+3 Data FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] 30.4.12.7 32-bit-write burst to 8-bit port 3-2-2-2 (one wait state) The following figure illustrates a write burst transfer with one wait state. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 761 General Business Information

Page 762

Address Address Data TSIZ = 00 AA=1 AA=0 AA=1 AA=0 Data Data Add+1 Add+2 Add+3 Data FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] 30.4.12.8 32-bit-read burst from 8-bit port 3-1-1-1 (address setup and hold) If address setup and hold are used, only the first and last beat of the burst cycle are affected. The following figure shows a read cycle with one clock of address setup and address hold. Note In non-multiplexed address/data mode, the address on FB_A increments only during internally-terminated burst cycles (CSCRn[AA] = 1b). The attached device must be able to account for this, or a wait state must be added. The first address is driven throughout the entire burst for externally-terminated cycles. In multiplexed address/data mode, the address is driven on FB_AD only during the first cycle for internally- and externally-terminated cycles. Functional description K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 762 Preliminary Freescale Semiconductor, Inc. General Business Information

Page 763

Address Address Data TSIZ=11 AA=1 AA=0 AA=1 AA=0 Data Data Data Add+1 Add+2 Add+3 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] 30.4.12.9 32-bit-write burst to 8-bit port 3-1-1-1 (address setup and hold) The following figure shows a write cycle with one clock of address setup and address hold. Chapter 30 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 Freescale Semiconductor, Inc. Preliminary 763 General Business Information

Page 764

Address Address Data TSIZ=11 AA=1 AA=0 AA=1 AA=0 Data Data Data Add+1 Add+2 Add+3 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] 30.4.13 Extended Transfer Start/Address Latch Enable The FB_TS/FB_ALE signal indicates that a bus transaction has begun and the address and attributes are valid. By default, the FB_TS/FB_ALE signal asserts for a single bus clock cycle. When CSCRn[EXTS] is set, the FB_TS/FB_ALE signal asserts and remain asserted until the first positive clock edge after FB_CSn asserts. See the following figure. NOTE When EXTS is set, CSCRn[WS] must be programmed to have

1.4 MiB Raw Permalink Blame History Unescape Escape