Ryan Malloy
c2197f6fe6
Three-pass optimization eliminates cable crossings: 1. Order boundary components by average header pin position 2. Regroup header pins by boundary component (reduces inter-cable crossings) 3. Reorder boundary component pins to parallel header (eliminates within-cable crossings) Safety hardening from Apollo review: - Duplicate header pin deduplication (prevents silent mapping corruption) - Connection structure validation at entry - Fan-out averaging for component pins connected to multiple header pins - Explicit ValueError on pin remapping failures with diagnostic context 145 tests passing (was 130).
spice2wireviz
Convert LTspice SPICE netlists to WireViz wiring diagrams.
What it does
spice2wireviz reads SPICE netlist files (.net, .cir, .sp) and generates WireViz YAML that documents the physical wiring: connectors, test points, and inter-module cables.
Two operating modes:
- Single module — External interface of one subcircuit (its connectors, test points, port interface)
- Inter-module — How multiple subcircuits/boards connect to each other
Install
uv tool install spice2wireviz
# or
pip install spice2wireviz
Usage
# Inter-module wiring (auto-detected from top-level X instances)
spice2wireviz top_level.net -o wiring.yml --render
# Single module external interface
spice2wireviz design.net -s amplifier_board -o amp.yml
# Only connectors and test points, no ground
spice2wireviz design.net --include-prefixes J,TP --no-ground
# Inspect before converting
spice2wireviz design.net --list-subcircuits
spice2wireviz design.net --list-components
spice2wireviz design.net --dry-run
Filtering
Cherry-pick what appears in the diagram:
--include-prefixes J,TP # Only these component types
--exclude-refs X3,J_DEBUG # Hide specific references
--include-nets "SIG_*" # Glob patterns for net names
--no-ground # Hide GND connections
--no-power # Hide VCC/VDD connections
Development
uv sync --extra dev
uv run pytest
uv run ruff check src/ tests/