Ryan Malloy
eb3ad60bd1
- Use CalVer dot notation (2026.2.13) for PEP 440 compliance - Filter pinlabels for top-level components when ground/power hidden - Fix unused variables, long lines, import ordering (ruff clean) - Use StrEnum for PinDirection (Python 3.11+) - Add .gitignore and README.md - All 105 tests pass including WireViz roundtrip validation
59 lines
1.5 KiB
Markdown
59 lines
1.5 KiB
Markdown
# spice2wireviz
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Convert LTspice SPICE netlists to WireViz wiring diagrams.
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## What it does
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`spice2wireviz` reads SPICE netlist files (`.net`, `.cir`, `.sp`) and generates [WireViz](https://github.com/wireviz/WireViz) YAML that documents the physical wiring: connectors, test points, and inter-module cables.
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Two operating modes:
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- **Single module** — External interface of one subcircuit (its connectors, test points, port interface)
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- **Inter-module** — How multiple subcircuits/boards connect to each other
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## Install
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```bash
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uv tool install spice2wireviz
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# or
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pip install spice2wireviz
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```
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## Usage
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```bash
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# Inter-module wiring (auto-detected from top-level X instances)
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spice2wireviz top_level.net -o wiring.yml --render
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# Single module external interface
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spice2wireviz design.net -s amplifier_board -o amp.yml
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# Only connectors and test points, no ground
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spice2wireviz design.net --include-prefixes J,TP --no-ground
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# Inspect before converting
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spice2wireviz design.net --list-subcircuits
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spice2wireviz design.net --list-components
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spice2wireviz design.net --dry-run
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```
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## Filtering
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Cherry-pick what appears in the diagram:
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```bash
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--include-prefixes J,TP # Only these component types
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--exclude-refs X3,J_DEBUG # Hide specific references
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--include-nets "SIG_*" # Glob patterns for net names
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--no-ground # Hide GND connections
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--no-power # Hide VCC/VDD connections
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```
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## Development
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```bash
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uv sync --extra dev
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uv run pytest
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uv run ruff check src/ tests/
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```
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