Ryan Malloy eb3ad60bd1 Fix linting issues and ground/power filtering in inter-module mapper

- Use CalVer dot notation (2026.2.13) for PEP 440 compliance
- Filter pinlabels for top-level components when ground/power hidden
- Fix unused variables, long lines, import ordering (ruff clean)
- Use StrEnum for PinDirection (Python 3.11+)
- Add .gitignore and README.md
- All 105 tests pass including WireViz roundtrip validation

2026-02-13 01:27:45 -07:00

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spice2wireviz

Convert LTspice SPICE netlists to WireViz wiring diagrams.

What it does

spice2wireviz reads SPICE netlist files (.net, .cir, .sp) and generates WireViz YAML that documents the physical wiring: connectors, test points, and inter-module cables.

Two operating modes:

Single module — External interface of one subcircuit (its connectors, test points, port interface)
Inter-module — How multiple subcircuits/boards connect to each other

Install

uv tool install spice2wireviz
# or
pip install spice2wireviz

Usage

# Inter-module wiring (auto-detected from top-level X instances)
spice2wireviz top_level.net -o wiring.yml --render

# Single module external interface
spice2wireviz design.net -s amplifier_board -o amp.yml

# Only connectors and test points, no ground
spice2wireviz design.net --include-prefixes J,TP --no-ground

# Inspect before converting
spice2wireviz design.net --list-subcircuits
spice2wireviz design.net --list-components
spice2wireviz design.net --dry-run

Filtering

Cherry-pick what appears in the diagram:

--include-prefixes J,TP     # Only these component types
--exclude-refs X3,J_DEBUG   # Hide specific references
--include-nets "SIG_*"      # Glob patterns for net names
--no-ground                 # Hide GND connections
--no-power                  # Hide VCC/VDD connections

Development

uv sync --extra dev
uv run pytest
uv run ruff check src/ tests/

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