Ryan Malloy
08c92bfefb
Implement three-tier resolution for LTspice .asc schematic files: 1. Companion netlist - finds .net/.cir/.sp beside the .asc (automatic) 2. LTspice generation - invokes LTspice binary (opt-in via --generate-netlist) 3. Metadata-only fallback - extracts component refs/values without connectivity Safety: DataCompleteness enum forces callers to check completeness. CLI blocks diagram generation on METADATA_ONLY with clear remediation. Metadata enrichment is additive-only with protected field guards. Also: update project URLs to Gitea, add .asc usage docs to README, fix pre-existing ruff warning in test_single_module.py.
321 lines
13 KiB
Python
321 lines
13 KiB
Python
"""Tests for the single-module mapper."""
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from pathlib import Path
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import pytest
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from spice2wireviz.filter import FilterConfig
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from spice2wireviz.mapper.single_module import (
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_optimize_single_layout,
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_remap_pins,
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map_single_module,
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)
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from spice2wireviz.parser.netlist import parse_netlist
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FIXTURES = Path(__file__).parent / "fixtures"
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class TestSingleModuleMapping:
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def test_simple_board_connectors(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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connectors = result["connectors"]
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assert "amplifier_board" in connectors # module header
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assert "J1" in connectors
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assert "J2" in connectors
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assert "TP1" in connectors
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def test_module_header_pinlabels(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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header = result["connectors"]["amplifier_board"]
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assert header["pinlabels"] == ["VIN", "GND", "VOUT", "SIGNAL_IN"]
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assert header["type"] == "Module Interface"
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def test_connector_pinlabels(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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j1 = result["connectors"]["J1"]
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assert j1["pinlabels"] == ["VIN", "GND"]
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def test_test_point_style(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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tp1 = result["connectors"]["TP1"]
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assert tp1.get("style") == "simple"
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def test_cables_created(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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cables = result["cables"]
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assert len(cables) >= 2 # At least cables for J1 and J2 connections
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def test_connections_created(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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connections = result["connections"]
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assert len(connections) >= 2
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def test_traceability_notes(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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header = result["connectors"]["amplifier_board"]
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assert "SPICE subcircuit" in header["notes"]
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def test_nonexistent_subcircuit_raises(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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with pytest.raises(ValueError, match="not found"):
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map_single_module(netlist, "nonexistent")
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def test_metadata_passthrough(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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meta = {"title": "Test Diagram", "author": "Test"}
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result = map_single_module(netlist, "amplifier_board", metadata=meta)
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assert result["metadata"]["title"] == "Test Diagram"
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class TestSingleModuleFiltering:
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def test_no_ground_filter(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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config = FilterConfig(show_ground=False)
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result = map_single_module(netlist, "amplifier_board", config)
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header = result["connectors"]["amplifier_board"]
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assert "GND" not in header["pinlabels"]
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def test_no_power_filter(self):
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"""When power is hidden, VIN should still appear as it's a port name, not a power net."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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config = FilterConfig(show_power=False)
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result = map_single_module(netlist, "amplifier_board", config)
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# VIN is a port name — it's not VCC/VDD so it stays
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header = result["connectors"]["amplifier_board"]
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assert "VIN" in header["pinlabels"]
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def test_exclude_component_ref(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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config = FilterConfig(exclude_refs=["TP1"])
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result = map_single_module(netlist, "amplifier_board", config)
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assert "TP1" not in result["connectors"]
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class TestSingleModuleLayoutOptimization:
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"""Tests for the star-topology layout optimization."""
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def test_boundary_component_order(self):
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"""Boundary components should appear in header pin order."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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names = list(result["connectors"].keys())
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# Header first, then J1 (avg pin 1.5), then J2 (avg pin 3.5), then TP1
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assert names[0] == "amplifier_board"
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assert names.index("J1") < names.index("J2")
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def test_j2_pins_reordered_to_eliminate_crossing(self):
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"""J2 pins should be [VOUT, SIGNAL_IN] to match header order."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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j2 = result["connectors"]["J2"]
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# Header has VOUT@3, SIGNAL_IN@4 — J2 must match: VOUT first
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assert j2["pinlabels"] == ["VOUT", "SIGNAL_IN"]
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def test_connections_parallel_after_optimization(self):
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"""After optimization, cable wires should not cross (pins monotonic)."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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for conn in result["connections"]:
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left_pins = conn[0][next(iter(conn[0]))]
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right_pins = conn[2][next(iter(conn[2]))]
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l_list = [left_pins] if isinstance(left_pins, int) else left_pins
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r_list = [right_pins] if isinstance(right_pins, int) else right_pins
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assert l_list == sorted(l_list), f"Left pins not sorted: {l_list}"
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assert r_list == sorted(r_list), f"Right pins not sorted: {r_list}"
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def test_connection_pins_valid(self):
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"""All pin indices must be within the connector's pin count."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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connectors = result["connectors"]
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for conn in result["connections"]:
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for entry in [conn[0], conn[2]]:
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name = next(iter(entry))
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pins = entry[name]
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pin_list = [pins] if isinstance(pins, int) else pins
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n_pins = len(connectors[name].get("pinlabels", []))
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if n_pins == 0:
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n_pins = connectors[name].get("pincount", 0)
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for p in pin_list:
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assert 1 <= p <= n_pins, (
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f"Pin {p} out of range for {name} ({n_pins} pins)"
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)
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def test_optimize_no_crash_single_connector(self):
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"""Single connector (no boundary) should pass through."""
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connectors = {"header": {"pinlabels": ["A", "B"]}}
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result_c, _cb, _cn = _optimize_single_layout("header", connectors, {}, [])
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assert result_c == connectors
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def test_optimize_no_crash_empty(self):
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"""Empty inputs should pass through."""
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result_c, _cb, _cn = _optimize_single_layout("header", {}, {}, [])
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assert result_c == {}
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def test_header_pin_regrouping(self):
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"""Header pins connecting to the same component should be grouped."""
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# Synthetic: header has interleaved pins
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# Pin 1 → compA, Pin 2 → compB, Pin 3 → compA, Pin 4 → compB
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connectors = {
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"H": {"pinlabels": ["A1", "B1", "A2", "B2"]},
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"CA": {"pinlabels": ["X", "Y"]},
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"CB": {"pinlabels": ["M", "N"]},
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}
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connections = [
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[{"H": [1, 3]}, {"W1": [1, 2]}, {"CA": [1, 2]}],
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[{"H": [2, 4]}, {"W2": [1, 2]}, {"CB": [1, 2]}],
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]
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result_c, _, _result_cn = _optimize_single_layout(
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"H", connectors, {}, connections
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)
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# Header should be regrouped: [A1, A2, B1, B2]
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assert result_c["H"]["pinlabels"] == ["A1", "A2", "B1", "B2"]
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# CA should come before CB
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names = list(result_c.keys())
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assert names.index("CA") < names.index("CB")
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def test_header_regrouping_updates_connections(self):
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"""After header regrouping, connection pin indices must be updated."""
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connectors = {
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"H": {"pinlabels": ["A1", "B1", "A2", "B2"]},
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"CA": {"pinlabels": ["X", "Y"]},
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"CB": {"pinlabels": ["M", "N"]},
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}
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connections = [
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[{"H": [1, 3]}, {"W1": [1, 2]}, {"CA": [1, 2]}],
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[{"H": [2, 4]}, {"W2": [1, 2]}, {"CB": [1, 2]}],
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]
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_, _, result_cn = _optimize_single_layout("H", connectors, {}, connections)
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# After regrouping: H pins [A1,A2,B1,B2] → old 1→new 1, old 3→new 2,
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# old 2→new 3, old 4→new 4
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# Connection 1: H:[1,3] should become H:[1,2]
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h_pins_0 = result_cn[0][0]["H"]
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assert h_pins_0 == [1, 2]
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# Connection 2: H:[2,4] should become H:[3,4]
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h_pins_1 = result_cn[1][0]["H"]
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assert h_pins_1 == [3, 4]
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def test_comp_pin_reorder_eliminates_crossing(self):
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"""Component pins should be reordered to match header pin order."""
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# Header: [A, B], CompX: [Y, X] where A→Y and B→X
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# This means header pin 1→comp pin 2, header pin 2→comp pin 1 (crossing!)
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connectors = {
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"H": {"pinlabels": ["A", "B"]},
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"CX": {"pinlabels": ["Y", "X"]},
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}
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connections = [
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[{"H": [1, 2]}, {"W1": [1, 2]}, {"CX": [2, 1]}],
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]
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result_c, _, result_cn = _optimize_single_layout(
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"H", connectors, {}, connections
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)
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# CX should be reordered to [X, Y] so pin 1→pin 1, pin 2→pin 2
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assert result_c["CX"]["pinlabels"] == ["X", "Y"]
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# Connection should now be CX:[1,2] (no crossing)
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assert result_cn[0][2]["CX"] == [1, 2]
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def test_disconnected_test_point_preserved(self):
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"""Test points with no header connection should appear last."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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names = list(result["connectors"].keys())
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# TP1 connects to internal net N001 (not a port), so it's disconnected
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# from the header. It should appear after connected components.
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assert names[-1] == "TP1"
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def test_connections_sorted_by_header_pin(self):
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"""Connections should be sorted by their minimum header pin."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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prev_min = 0
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for conn in result["connections"]:
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# Header is always on the left in single-module connections
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left_name = next(iter(conn[0]))
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h_pins = conn[0][left_name]
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pin_list = [h_pins] if isinstance(h_pins, int) else h_pins
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min_pin = min(pin_list)
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assert min_pin >= prev_min, (
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f"Connection order wrong: min pin {min_pin} < previous {prev_min}"
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)
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prev_min = min_pin
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def test_shared_header_pin_deduplication(self):
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"""Header pin shared by two components should not corrupt mapping."""
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# Pin 2 of header connects to both CA and CB (e.g., GND fan-out)
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connectors = {
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"H": {"pinlabels": ["VIN", "GND", "VOUT"]},
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"CA": {"pinlabels": ["X", "Y"]},
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"CB": {"pinlabels": ["M", "N"]},
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}
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connections = [
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[{"H": [1, 2]}, {"W1": [1, 2]}, {"CA": [1, 2]}],
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[{"H": [2, 3]}, {"W2": [1, 2]}, {"CB": [1, 2]}],
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]
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result_c, _, result_cn = _optimize_single_layout(
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"H", connectors, {}, connections
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)
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# Should not crash, and all pin indices must be valid
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h_labels = result_c["H"]["pinlabels"]
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assert len(h_labels) == 3
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# All connections should have valid pin references
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for conn in result_cn:
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h_pins = conn[0]["H"]
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pin_list = [h_pins] if isinstance(h_pins, int) else h_pins
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for p in pin_list:
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assert 1 <= p <= 3, f"Header pin {p} out of range"
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def test_remap_pins_missing_key_raises(self):
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"""_remap_pins should raise ValueError with context on missing pin."""
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mapping = {1: 2, 2: 1}
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with pytest.raises(ValueError, match="Pin remapping failed for J1"):
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_remap_pins("J1", [1, 3], mapping)
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def test_remap_pins_scalar(self):
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"""_remap_pins should handle scalar pin input."""
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mapping = {1: 3, 2: 1, 3: 2}
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assert _remap_pins("X", 2, mapping) == 1
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def test_comp_pin_fanout_averaging(self):
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"""Component pin connecting to multiple header pins should use average."""
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# CX pin 1 connects to header pins 4 and 5 → remapped avg = 2.5
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# CX pin 2 connects to header pin 1 → remapped pos = 1.0
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# After header regrouping [1,4,5] → positions [1,2,3]:
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# pin 1: avg(2,3) = 2.5, pin 2: pos(1) = 1.0
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# So pin 2 should come before pin 1 → [P2, P1]
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connectors = {
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"H": {"pinlabels": ["A", "B", "C", "D", "E"]},
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"CX": {"pinlabels": ["P1", "P2"]},
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}
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connections = [
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[{"H": 4}, {"W1": 1}, {"CX": 1}],
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[{"H": 5}, {"W2": 1}, {"CX": 1}],
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[{"H": 1}, {"W3": 1}, {"CX": 2}],
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]
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result_c, _, _ = _optimize_single_layout("H", connectors, {}, connections)
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# Pin 2 (remapped h_pos=1.0) before Pin 1 (avg remapped h_pos=2.5)
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assert result_c["CX"]["pinlabels"] == ["P2", "P1"]
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