Ryan Malloy
5a5337566c
- Fix _try_ltspice_generation() to use spicelib.simulators.ltspice_simulator.LTspice instead of the abstract Simulator base class (which always returned unavailable) - Use LTspice.create_netlist() instead of Simulator.run() for correct netlist generation - Add --ltspice-exe CLI option to specify LTspice binary path - Add --bom flag for component BOM CSV output (works on any parse completeness) - Add --bom-wiring flag for wiring BOM CSV from mapped output - Add real 1002A.asc demo circuit and pre-generated .net as test fixtures - Add @pytest.mark.ltspice marker for tests requiring LTspice binary - Bump version to 2026.2.14
spice2wireviz
Convert LTspice SPICE netlists to WireViz wiring diagrams.
What it does
spice2wireviz reads SPICE netlist files (.net, .cir, .sp) and LTspice schematics (.asc) and generates WireViz YAML that documents the physical wiring: connectors, test points, and inter-module cables.
Two operating modes:
- Single module -- External interface of one subcircuit (its connectors, test points, port interface)
- Inter-module -- How multiple subcircuits/boards connect to each other
Install
uv tool install spice2wireviz
# or
pip install spice2wireviz
For .asc file metadata extraction (optional):
pip install spice2wireviz[asc]
Usage
From netlist files
# Inter-module wiring (auto-detected from top-level X instances)
spice2wireviz top_level.net -o wiring.yml --render
# Single module external interface
spice2wireviz design.net -s amplifier_board -o amp.yml
# Only connectors and test points, no ground
spice2wireviz design.net --include-prefixes J,TP --no-ground
# Inspect before converting
spice2wireviz design.net --list-subcircuits
spice2wireviz design.net --list-components
spice2wireviz design.net --dry-run
From .asc schematics
LTspice .asc files are supported with tiered netlist resolution:
- Companion netlist (automatic) -- If a
.net,.cir, or.spfile exists alongside the.asc(same basename), it's used for full connectivity. LTspice generates these automatically when you run a simulation. - LTspice generation (opt-in) -- Pass
--generate-netlistto invoke LTspice and produce a.netfile. - Metadata only -- Without a netlist, only component refs/values are available. Diagram generation is blocked, but
--list-componentsstill works.
# .asc with companion .net in the same directory -- works like .net input
spice2wireviz schematic.asc -s amplifier_board -o amp.yml
# No companion .net -- invoke LTspice to generate one
spice2wireviz schematic.asc --generate-netlist -o wiring.yml
# Inspect component metadata (no .net required)
spice2wireviz schematic.asc --list-components
Filtering
Cherry-pick what appears in the diagram:
--include-prefixes J,TP # Only these component types
--exclude-refs X3,J_DEBUG # Hide specific references
--include-nets "SIG_*" # Glob patterns for net names
--no-ground # Hide GND connections
--no-power # Hide VCC/VDD connections
Development
uv sync --extra dev --extra asc
uv run pytest
uv run ruff check src/ tests/