Ryan Malloy
b9154e851b
C1: Port count mismatch now emits ERROR to stderr and marks
unconnected ports as __UNCONNECTED_<name>__ (never silent)
C2: Single-module pin mapping built in lockstep — cable_wires
always matches header_pins length, warns on unmappable nets
C3: VSS removed from is_power_net (it's ground per CMOS convention),
dead _POWER_PATTERN regex replaced with _KNOWN_NET_PATTERN
C4: apply_filters dead computation removed, docstring clarifies
that net-level filtering is a mapper concern
I3: WireViz render catches (ValueError, TypeError, OSError) with
diagnostic context instead of bare Exception
I5: Invalid --format flags now warn and error instead of silently
falling through to defaults
I6: Model/value heuristic warns on stderr when it triggers, since
signal names like ALERT or DATA could be misidentified
New tests: VSS classification, port count mismatch (C1), model/value
heuristic warning (I6), duplicate refs (S3), empty subcircuit (S2),
full pipeline determinism across 3 runs (S1)
115 tests pass, ruff clean
217 lines
8.0 KiB
Python
217 lines
8.0 KiB
Python
"""Roundtrip tests: parse SPICE -> emit YAML -> validate with WireViz.
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These tests verify the generated YAML is structurally valid by feeding
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it to wireviz.wireviz.parse() and checking it doesn't raise exceptions.
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"""
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from pathlib import Path
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import pytest
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import yaml
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from spice2wireviz.emitter.yaml_emitter import emit_yaml
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from spice2wireviz.filter import FilterConfig
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from spice2wireviz.mapper.inter_module import map_inter_module
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from spice2wireviz.mapper.single_module import map_single_module
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from spice2wireviz.parser.netlist import parse_netlist
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FIXTURES = Path(__file__).parent / "fixtures"
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def _has_wireviz() -> bool:
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try:
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from wireviz.wireviz import parse # noqa: F401
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return True
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except ImportError:
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return False
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class TestYamlValidity:
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"""Verify generated YAML is valid YAML and has required WireViz keys."""
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def test_single_module_yaml_structure(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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yaml_str = emit_yaml(result)
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parsed = yaml.safe_load(yaml_str)
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assert "connectors" in parsed
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assert "cables" in parsed
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assert "connections" in parsed
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assert isinstance(parsed["connectors"], dict)
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assert isinstance(parsed["cables"], dict)
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assert isinstance(parsed["connections"], list)
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def test_inter_module_yaml_structure(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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yaml_str = emit_yaml(result)
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parsed = yaml.safe_load(yaml_str)
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assert "connectors" in parsed
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assert "cables" in parsed
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assert "connections" in parsed
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def test_hierarchical_yaml_structure(self):
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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result = map_inter_module(netlist)
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yaml_str = emit_yaml(result)
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parsed = yaml.safe_load(yaml_str)
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assert "connectors" in parsed
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assert len(parsed["connectors"]) >= 6 # 3 instances + 3 top-level
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def test_connector_has_pin_spec(self):
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"""Every connector must have at least one of pincount/pins/pinlabels."""
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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yaml_str = emit_yaml(result)
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parsed = yaml.safe_load(yaml_str)
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for name, conn in parsed["connectors"].items():
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has_pins = any(k in conn for k in ("pincount", "pins", "pinlabels"))
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assert has_pins, f"Connector '{name}' missing pin specification"
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def test_cable_has_wire_spec(self):
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"""Every cable must have wirecount or colors."""
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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yaml_str = emit_yaml(result)
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parsed = yaml.safe_load(yaml_str)
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for name, cable in parsed["cables"].items():
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has_wires = "wirecount" in cable or "colors" in cable
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assert has_wires, f"Cable '{name}' missing wire specification"
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def test_connection_set_structure(self):
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"""Each connection set should be a list of dicts."""
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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yaml_str = emit_yaml(result)
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parsed = yaml.safe_load(yaml_str)
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for i, conn_set in enumerate(parsed["connections"]):
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assert isinstance(conn_set, list), f"Connection set {i} is not a list"
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assert len(conn_set) == 3, f"Connection set {i} doesn't have 3 elements"
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for entry in conn_set:
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assert isinstance(entry, dict), f"Connection set {i} entry is not a dict"
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class TestPipelineDeterminism:
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"""S1: Verify the full pipeline produces byte-identical output on repeated runs."""
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def test_inter_module_deterministic(self):
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"""Parse the same file multiple times; output must be identical."""
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outputs = []
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for _ in range(3):
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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result = map_inter_module(netlist)
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yaml_str = emit_yaml(result)
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outputs.append(yaml_str)
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assert outputs[0] == outputs[1] == outputs[2]
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def test_single_module_deterministic(self):
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outputs = []
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for _ in range(3):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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yaml_str = emit_yaml(result)
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outputs.append(yaml_str)
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assert outputs[0] == outputs[1] == outputs[2]
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def test_filtered_deterministic(self):
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config = FilterConfig(show_ground=False, show_power=False)
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outputs = []
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for _ in range(3):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist, config)
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yaml_str = emit_yaml(result)
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outputs.append(yaml_str)
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assert outputs[0] == outputs[1] == outputs[2]
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class TestEmptySubcircuit:
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"""S2: Subcircuit with ports but no boundary components."""
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def test_empty_subcircuit_produces_header_only(self):
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text = """\
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.subckt bare_module A B C
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* No J*/TP*/P* inside — just passives
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R1 A B 10k
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.ends bare_module
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"""
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netlist = parse_netlist(text)
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result = map_single_module(netlist, "bare_module")
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# Should produce a header connector but no cables or connections
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assert "bare_module" in result["connectors"]
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assert len(result["cables"]) == 0
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assert len(result["connections"]) == 0
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class TestDuplicateRefInMapper:
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"""S3: Duplicate reference designators in the mapper."""
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def test_duplicate_ref_last_wins_in_inter_module(self):
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"""When two top-level components share a reference, the mapper
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builds connectors from both but dict key collision means last wins.
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This is a known limitation that should at least not crash."""
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text = """\
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.subckt mod A B
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.ends mod
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X1 NET1 NET2 mod
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J1 NET1 NET2 CONN_A
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J1 NET3 NET4 CONN_B
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"""
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netlist = parse_netlist(text)
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result = map_inter_module(netlist)
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# Should not crash; J1 connector exists (last definition wins)
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assert "J1" in result["connectors"]
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@pytest.mark.skipif(not _has_wireviz(), reason="WireViz not installed")
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class TestWireVizRoundtrip:
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"""Feed generated YAML to WireViz's parse() to verify full compatibility."""
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def test_single_module_roundtrip(self):
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from wireviz.wireviz import parse as wv_parse
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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# WireViz parse() accepts dicts directly
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harness = wv_parse(result, return_types="harness")
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assert harness is not None
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def test_inter_module_roundtrip(self):
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from wireviz.wireviz import parse as wv_parse
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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harness = wv_parse(result, return_types="harness")
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assert harness is not None
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def test_hierarchical_roundtrip(self):
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from wireviz.wireviz import parse as wv_parse
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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result = map_inter_module(netlist)
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harness = wv_parse(result, return_types="harness")
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assert harness is not None
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def test_filtered_roundtrip(self):
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from wireviz.wireviz import parse as wv_parse
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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config = FilterConfig(show_ground=False, show_power=False)
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result = map_inter_module(netlist, config)
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harness = wv_parse(result, return_types="harness")
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assert harness is not None
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def test_render_svg(self, tmp_path):
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from wireviz.wireviz import parse as wv_parse
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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svg = wv_parse(result, return_types="svg")
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assert svg is not None
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assert len(svg) > 100 # Should be a real SVG
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