2 Commits

Author	SHA1	Message	Date
Ryan Malloy	b8ff2d19da	Add Sugiyama-lite layout optimization for inter-module diagrams ... Layered graph drawing approach to minimize cable crossings: - Layer assignment via BFS from external connectors (J*, TP*, P*) - Barycenter ordering (forward + backward sweep) within each layer - Connection orientation: earlier connector always on the left - Pin reordering: weighted average neighbor position groups pins by destination, reducing within-connector crossings - Connection sorting: shorter (adjacent-pair) connections first Fixes from Apollo safety review: - Explicit ValueError on pin remapping failures (was silent KeyError) - Weighted pin averaging for star topology (GND shared across modules) - Fully deterministic sort keys for reproducible output - Documented closure capture pattern in loop sort keys	2026-02-13 02:01:06 -07:00
Ryan Malloy	e20a956f51	Initial project structure for spice2wireviz ... SPICE netlist to WireViz YAML converter with: - Custom lightweight netlist parser (.net/.cir/.sp) - Single-module mapper (subcircuit external interface) - Inter-module mapper (multi-board wiring) - Filter engine with glob patterns - Click CLI with auto-detection, inspection commands - Optional .asc parser via spicelib - Comprehensive test suite with fixtures	2026-02-13 01:24:41 -07:00