Ryan Malloy
e20a956f51
SPICE netlist to WireViz YAML converter with: - Custom lightweight netlist parser (.net/.cir/.sp) - Single-module mapper (subcircuit external interface) - Inter-module mapper (multi-board wiring) - Filter engine with glob patterns - Click CLI with auto-detection, inspection commands - Optional .asc parser via spicelib - Comprehensive test suite with fixtures
146 lines
5.1 KiB
Python
146 lines
5.1 KiB
Python
"""Tests for the inter-module mapper."""
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from pathlib import Path
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from spice2wireviz.filter import FilterConfig
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from spice2wireviz.mapper.inter_module import map_inter_module
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from spice2wireviz.parser.netlist import parse_netlist
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FIXTURES = Path(__file__).parent / "fixtures"
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class TestInterModuleMapping:
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def test_multi_board_connectors(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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connectors = result["connectors"]
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# Should have connectors for each X instance and top-level components
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assert "X1" in connectors
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assert "X2" in connectors
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assert "X3" in connectors
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assert "J_CHASSIS" in connectors
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assert "TP_VCC" in connectors
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def test_instance_connector_type(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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x1 = result["connectors"]["X1"]
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assert x1["type"] == "power_supply"
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def test_instance_pinlabels(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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x2 = result["connectors"]["X2"]
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assert "VIN" in x2["pinlabels"]
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assert "GND" in x2["pinlabels"]
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assert "VOUT" in x2["pinlabels"]
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def test_cables_for_shared_nets(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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# Should have cables connecting modules via shared nets
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cables = result["cables"]
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assert len(cables) >= 1
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def test_connections_exist(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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connections = result["connections"]
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assert len(connections) >= 1
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def test_traceability_notes(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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x1 = result["connectors"]["X1"]
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assert "SPICE instance" in x1["notes"]
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def test_top_level_test_point_style(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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result = map_inter_module(netlist)
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tp = result["connectors"]["TP_VCC"]
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assert tp.get("style") == "simple"
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class TestInterModuleFiltering:
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def test_exclude_instance(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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config = FilterConfig(exclude_refs=["X1"])
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result = map_inter_module(netlist, config)
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assert "X1" not in result["connectors"]
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assert "X2" in result["connectors"]
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def test_exclude_subcircuit(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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config = FilterConfig(exclude_subcircuits=["power_supply"])
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result = map_inter_module(netlist, config)
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assert "X1" not in result["connectors"]
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def test_no_ground_filter(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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config = FilterConfig(show_ground=False)
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result = map_inter_module(netlist, config)
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# GND should not appear in any connector's pinlabels
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for name, conn in result["connectors"].items():
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if "pinlabels" in conn:
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assert "GND" not in conn["pinlabels"], f"GND found in {name}"
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def test_no_power_filter(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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config = FilterConfig(show_power=False)
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result = map_inter_module(netlist, config)
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for name, conn in result["connectors"].items():
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if "pinlabels" in conn:
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assert "VCC" not in conn["pinlabels"], f"VCC found in {name}"
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class TestHierarchicalInterModule:
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def test_hierarchical_instances(self):
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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result = map_inter_module(netlist)
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connectors = result["connectors"]
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assert "X_REG" in connectors
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assert "X_SENSOR" in connectors
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assert "X_MAIN" in connectors
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def test_external_connectors(self):
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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result = map_inter_module(netlist)
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connectors = result["connectors"]
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assert "J_PWR" in connectors
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assert "J_USB" in connectors
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assert "TP_3V3" in connectors
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def test_grouped_parallel_wires(self):
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"""Parallel wires between same modules should be grouped."""
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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config = FilterConfig(group_parallel_wires=True)
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result = map_inter_module(netlist, config)
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# With grouping, fewer cables than total net connections
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cables = result["cables"]
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connections = result["connections"]
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assert len(cables) == len(connections)
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def test_ungrouped_wires(self):
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"""Without grouping, each wire gets its own cable."""
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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config = FilterConfig(group_parallel_wires=False)
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result = map_inter_module(netlist, config)
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# Each cable should have wirecount=1
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for cable in result["cables"].values():
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assert cable.get("wirecount", 1) == 1 or len(cable.get("colors", [])) == 1
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