From b89e520479c7b1a97dc1b00309205e4f12e971d1 Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Mon, 23 Feb 2026 14:25:50 -0700 Subject: [PATCH] Consistent label offsets across all schematic layout engines Add ofst=0.15 to all component labels for uniform clearance between label text and component bodies. Previously, loop layout had no offsets, grid layout was missing offsets on multi-terminal devices (BJT/FET), and connected layout was missing offsets on transistor and horizontal labels. --- backend/src/spicebook/engine/schematic.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/backend/src/spicebook/engine/schematic.py b/backend/src/spicebook/engine/schematic.py index cf526f3..8d35032 100644 --- a/backend/src/spicebook/engine/schematic.py +++ b/backend/src/spicebook/engine/schematic.py @@ -638,7 +638,7 @@ def _render_loop(parsed: ParsedNetlist, loop: list[SpiceComponent]) -> str: d.add( _get_element(source, parsed.models) .up() - .label(_component_label(source), loc="left") + .label(_component_label(source), loc="left", ofst=0.15) ) d.add(elm.Ground()) return d.get_imagedata("svg").decode() @@ -647,7 +647,7 @@ def _render_loop(parsed: ParsedNetlist, loop: list[SpiceComponent]) -> str: src = d.add( _get_element(source, parsed.models) .up() - .label(_component_label(source), loc="left") + .label(_component_label(source), loc="left", ofst=0.15) ) # All components except the last go right across the top @@ -655,7 +655,7 @@ def _render_loop(parsed: ParsedNetlist, loop: list[SpiceComponent]) -> str: d.add( _get_element(comp, parsed.models) .right() - .label(_component_label(comp)) + .label(_component_label(comp), ofst=0.15) ) # Last component goes down, ending at the same y-level as the source start @@ -664,7 +664,7 @@ def _render_loop(parsed: ParsedNetlist, loop: list[SpiceComponent]) -> str: _get_element(last_comp, parsed.models) .down() .toy(src.start) - .label(_component_label(last_comp), loc="right") + .label(_component_label(last_comp), loc="right", ofst=0.15) ) # Return wire along the bottom back to source start @@ -1009,7 +1009,7 @@ def _render_grid(parsed: ParsedNetlist) -> str: node_ys = [tiers.get(n, _GRID_MID_Y) for n in comp.nodes[:3]] center_y = (max(node_ys) + min(node_ys)) / 2 placed_elem = d.add( - elem.at((x, center_y)).label(_component_label(comp)) + elem.at((x, center_y)).label(_component_label(comp), loc="right", ofst=0.15) ) elif len(comp.nodes) >= 2: # 2-terminal: orient vertically between the two node tiers @@ -1199,7 +1199,7 @@ def _draw_horiz_then_down(d, parsed, start, path, going_right): ) break else: - d.add(getattr(elem, h_dir)().label(_component_label(comp))) + d.add(getattr(elem, h_dir)().label(_component_label(comp), ofst=0.15)) # Single-component horizontal path ending at ground/supply/open if len(comps) == 1: @@ -1228,7 +1228,7 @@ def _render_connected(parsed: ParsedNetlist, layout: ActiveLayout) -> str: # (Mims convention: transistor type label beside the symbol) if layout.device_type.startswith("bjt"): dev_elem = elm.BjtPnp() if is_inverted else elm.BjtNpn() - q = d.add(dev_elem.label(_component_label(layout.device), loc="right")) + q = d.add(dev_elem.label(_component_label(layout.device), loc="right", ofst=0.15)) anchors = { "collector": q.collector, "base": q.base, @@ -1238,7 +1238,7 @@ def _render_connected(parsed: ParsedNetlist, layout: ActiveLayout) -> str: input_term = "base" else: dev_elem = elm.PFet() if is_inverted else elm.NFet() - q = d.add(dev_elem.label(_component_label(layout.device), loc="right")) + q = d.add(dev_elem.label(_component_label(layout.device), loc="right", ofst=0.15)) anchors = { "drain": q.drain, "gate": q.gate,