Ryan Malloy
e20a956f51
SPICE netlist to WireViz YAML converter with: - Custom lightweight netlist parser (.net/.cir/.sp) - Single-module mapper (subcircuit external interface) - Inter-module mapper (multi-board wiring) - Filter engine with glob patterns - Click CLI with auto-detection, inspection commands - Optional .asc parser via spicelib - Comprehensive test suite with fixtures
105 lines
3.9 KiB
Python
105 lines
3.9 KiB
Python
"""Tests for the single-module mapper."""
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from pathlib import Path
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import pytest
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from spice2wireviz.filter import FilterConfig
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from spice2wireviz.mapper.single_module import map_single_module
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from spice2wireviz.parser.netlist import parse_netlist
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FIXTURES = Path(__file__).parent / "fixtures"
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class TestSingleModuleMapping:
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def test_simple_board_connectors(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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connectors = result["connectors"]
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assert "amplifier_board" in connectors # module header
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assert "J1" in connectors
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assert "J2" in connectors
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assert "TP1" in connectors
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def test_module_header_pinlabels(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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header = result["connectors"]["amplifier_board"]
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assert header["pinlabels"] == ["VIN", "GND", "VOUT", "SIGNAL_IN"]
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assert header["type"] == "Module Interface"
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def test_connector_pinlabels(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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j1 = result["connectors"]["J1"]
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assert j1["pinlabels"] == ["VIN", "GND"]
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def test_test_point_style(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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tp1 = result["connectors"]["TP1"]
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assert tp1.get("style") == "simple"
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def test_cables_created(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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cables = result["cables"]
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assert len(cables) >= 2 # At least cables for J1 and J2 connections
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def test_connections_created(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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connections = result["connections"]
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assert len(connections) >= 2
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def test_traceability_notes(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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header = result["connectors"]["amplifier_board"]
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assert "SPICE subcircuit" in header["notes"]
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def test_nonexistent_subcircuit_raises(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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with pytest.raises(ValueError, match="not found"):
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map_single_module(netlist, "nonexistent")
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def test_metadata_passthrough(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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meta = {"title": "Test Diagram", "author": "Test"}
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result = map_single_module(netlist, "amplifier_board", metadata=meta)
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assert result["metadata"]["title"] == "Test Diagram"
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class TestSingleModuleFiltering:
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def test_no_ground_filter(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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config = FilterConfig(show_ground=False)
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result = map_single_module(netlist, "amplifier_board", config)
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header = result["connectors"]["amplifier_board"]
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assert "GND" not in header["pinlabels"]
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def test_no_power_filter(self):
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"""When power is hidden, VIN should still appear as it's a port name, not a power net."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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config = FilterConfig(show_power=False)
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result = map_single_module(netlist, "amplifier_board", config)
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# VIN is a port name — it's not VCC/VDD so it stays
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header = result["connectors"]["amplifier_board"]
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assert "VIN" in header["pinlabels"]
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def test_exclude_component_ref(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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config = FilterConfig(exclude_refs=["TP1"])
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result = map_single_module(netlist, "amplifier_board", config)
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assert "TP1" not in result["connectors"]
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