08c92bfefb
Add tiered .asc parser with companion netlist resolution
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Implement three-tier resolution for LTspice .asc schematic files:
1. Companion netlist - finds .net/.cir/.sp beside the .asc (automatic)
2. LTspice generation - invokes LTspice binary (opt-in via --generate-netlist)
3. Metadata-only fallback - extracts component refs/values without connectivity
Safety: DataCompleteness enum forces callers to check completeness.
CLI blocks diagram generation on METADATA_ONLY with clear remediation.
Metadata enrichment is additive-only with protected field guards.
Also: update project URLs to Gitea, add .asc usage docs to README,
fix pre-existing ruff warning in test_single_module.py.
2026-02-13 04:59:03 -07:00
eb3ad60bd1
Fix linting issues and ground/power filtering in inter-module mapper
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- Use CalVer dot notation (2026.2.13) for PEP 440 compliance
- Filter pinlabels for top-level components when ground/power hidden
- Fix unused variables, long lines, import ordering (ruff clean)
- Use StrEnum for PinDirection (Python 3.11+)
- Add .gitignore and README.md
- All 105 tests pass including WireViz roundtrip validation
2026-02-13 01:27:45 -07:00
e20a956f51
Initial project structure for spice2wireviz
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SPICE netlist to WireViz YAML converter with:
- Custom lightweight netlist parser (.net/.cir/.sp)
- Single-module mapper (subcircuit external interface)
- Inter-module mapper (multi-board wiring)
- Filter engine with glob patterns
- Click CLI with auto-detection, inspection commands
- Optional .asc parser via spicelib
- Comprehensive test suite with fixtures
2026-02-13 01:24:41 -07:00
