Ryan Malloy
890a38bfa0
Correct BCM4500 I2C address from 0x10 (8-bit wire) to 0x08 (7-bit) since fx2lib shifts internally. Add i2c_combined_read() with repeated START for proper BCM4500 register access. Add I2C bus scan (0xB4), raw read (0xB5), and indirect protocol diagnostic (0xB6) commands. Single-transaction indirect reads/writes for BCM4500 register protocol. Verified on hardware: BCM4500 ACKs at 0x08, BOOT_8PSK returns config 0x03. Register reads still return zeros — BCM4500 needs DSP firmware loaded via LOAD_BCM4500 (0x88) before registers become functional.
1027 lines
28 KiB
C
1027 lines
28 KiB
C
/*
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* Genpix SkyWalker-1 Custom Firmware
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* For Cypress CY7C68013A (FX2LP) + Broadcom BCM4500 demodulator
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*
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* Stock-compatible vendor commands (0x80-0x94) plus new
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* spectrum sweep, raw demod access, and blind scan commands (0xB0-0xB3).
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*
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* SDCC + fx2lib toolchain. Loaded into FX2 RAM for testing.
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*/
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#include <fx2regs.h>
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#include <fx2macros.h>
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#include <delay.h>
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#include <autovector.h>
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#include <setupdat.h>
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#include <eputils.h>
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#include <i2c.h>
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#define SYNCDELAY SYNCDELAY4
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/* BCM4500 I2C address (7-bit); 8-bit wire address is 0x10/0x11 */
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#define BCM4500_ADDR 0x08
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/* BCM4500 indirect register protocol registers */
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#define BCM_REG_PAGE 0xA6
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#define BCM_REG_DATA 0xA7
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#define BCM_REG_CMD 0xA8
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/* BCM4500 status registers */
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#define BCM_REG_STATUS 0xA2
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#define BCM_REG_LOCK 0xA4
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/* BCM commands */
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#define BCM_CMD_READ 0x01
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#define BCM_CMD_WRITE 0x03
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/* vendor command IDs */
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#define GET_8PSK_CONFIG 0x80
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#define TUNE_8PSK 0x86
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#define GET_SIGNAL_STRENGTH 0x87
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#define BOOT_8PSK 0x89
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#define START_INTERSIL 0x8A
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#define SET_LNB_VOLTAGE 0x8B
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#define SET_22KHZ_TONE 0x8C
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#define SEND_DISEQC 0x8D
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#define ARM_TRANSFER 0x85
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#define GET_SIGNAL_LOCK 0x90
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#define GET_FW_VERS 0x92
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#define USE_EXTRA_VOLT 0x94
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/* custom vendor commands */
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#define SPECTRUM_SWEEP 0xB0
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#define RAW_DEMOD_READ 0xB1
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#define RAW_DEMOD_WRITE 0xB2
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#define BLIND_SCAN 0xB3
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/* configuration status byte bits */
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#define BM_STARTED 0x01
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#define BM_FW_LOADED 0x02
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#define BM_INTERSIL 0x04
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#define BM_DVB_MODE 0x08
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#define BM_22KHZ 0x10
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#define BM_SEL18V 0x20
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#define BM_DC_TUNED 0x40
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#define BM_ARMED 0x80
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/* GPIO pin definitions for v2.06 hardware */
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#define PIN_22KHZ 0x08 /* P0.3 */
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#define PIN_LNB_VOLT 0x10 /* P0.4 */
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#define PIN_DISEQC 0x80 /* P0.7 */
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/* configuration status byte -- stored in ordinary variable */
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static volatile BYTE config_status;
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/* ISR flag */
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volatile __bit got_sud;
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/* I2C scratch buffers in xdata */
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static __xdata BYTE i2c_buf[8];
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static __xdata BYTE i2c_rd[8];
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/* ---------- BCM4500 I2C helpers ---------- */
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/*
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* Combined I2C write-read with repeated START (no STOP between
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* write and read phases). Many I2C devices including the BCM4500
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* require this pattern instead of separate write+stop/read+stop.
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*
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* Sequence: START → addr+W → reg → RESTART → addr+R → data → STOP
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*/
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static BOOL i2c_combined_read(BYTE addr, BYTE reg, BYTE len, BYTE *buf) {
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BYTE i;
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BYTE tmp;
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/* START + write address */
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I2CS |= bmSTART;
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I2DAT = addr << 1;
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while (!(I2CS & bmDONE))
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;
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if (!(I2CS & bmACK))
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goto fail;
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/* Write register address */
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I2DAT = reg;
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while (!(I2CS & bmDONE))
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;
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if (!(I2CS & bmACK))
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goto fail;
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/* REPEATED START + read address */
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I2CS |= bmSTART;
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I2DAT = (addr << 1) | 1;
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while (!(I2CS & bmDONE))
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;
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if (!(I2CS & bmACK))
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goto fail;
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/* For single byte, set LASTRD before dummy read */
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if (len == 1)
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I2CS |= bmLASTRD;
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/* Dummy read to trigger first clock burst */
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tmp = I2DAT;
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for (i = 0; i < len; i++) {
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while (!(I2CS & bmDONE))
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;
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if (i == len - 2)
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I2CS |= bmLASTRD;
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if (i == len - 1)
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I2CS |= bmSTOP;
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buf[i] = I2DAT;
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}
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while (I2CS & bmSTOP)
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;
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return TRUE;
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fail:
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I2CS |= bmSTOP;
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while (I2CS & bmSTOP)
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;
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return FALSE;
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}
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/*
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* Write one byte to a BCM4500 direct I2C register (subaddr).
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* This writes to the I2C register directly, not through the
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* indirect protocol.
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*/
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static BOOL bcm_direct_write(BYTE reg, BYTE val) {
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i2c_buf[0] = val;
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return i2c_write(BCM4500_ADDR, 1, ®, 1, i2c_buf);
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}
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/*
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* Read one byte from a BCM4500 direct I2C register using
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* combined write-read with repeated START.
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*/
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static BOOL bcm_direct_read(BYTE reg, BYTE *val) {
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return i2c_combined_read(BCM4500_ADDR, reg, 1, val);
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}
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/*
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* Write a value to a BCM4500 indirect register.
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* Single multi-byte I2C write to 0xA6 with auto-increment:
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* [0xA6] = page, [0xA7] = data, [0xA8] = 0x03 (write cmd)
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*/
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static BOOL bcm_indirect_write(BYTE reg, BYTE val) {
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BYTE start_reg = BCM_REG_PAGE;
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i2c_rd[0] = reg;
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i2c_rd[1] = val;
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i2c_rd[2] = BCM_CMD_WRITE;
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return i2c_write(BCM4500_ADDR, 1, &start_reg, 3, i2c_rd);
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}
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/*
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* Read a value from a BCM4500 indirect register.
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* Protocol: single multi-byte I2C write to 0xA6 with auto-increment:
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* [0xA6] = page, [0xA7] = 0x00, [0xA8] = 0x01 (read cmd)
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* Then read the result from 0xA7.
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*/
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static BOOL bcm_indirect_read(BYTE reg, BYTE *val) {
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BYTE start_reg = BCM_REG_PAGE;
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/* page, placeholder data, read command — written to A6,A7,A8 in one shot */
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i2c_rd[0] = reg;
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i2c_rd[1] = 0x00;
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i2c_rd[2] = BCM_CMD_READ;
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if (!i2c_write(BCM4500_ADDR, 1, &start_reg, 3, i2c_rd))
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return FALSE;
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delay(1);
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return i2c_combined_read(BCM4500_ADDR, BCM_REG_DATA, 1, val);
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}
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/*
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* Write a multi-byte block to BCM4500 via indirect protocol.
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* Page select, then N data bytes to 0xA7, then commit with 0x03.
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*/
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static BOOL bcm_indirect_write_block(BYTE page, __xdata BYTE *data, BYTE len) {
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BYTE reg;
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reg = BCM_REG_PAGE;
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i2c_buf[0] = page;
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if (!i2c_write(BCM4500_ADDR, 1, ®, 1, i2c_buf))
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return FALSE;
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reg = BCM_REG_DATA;
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if (!i2c_write(BCM4500_ADDR, 1, ®, len, data))
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return FALSE;
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if (!bcm_direct_write(BCM_REG_CMD, BCM_CMD_WRITE))
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return FALSE;
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return TRUE;
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}
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/*
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* Poll BCM4500 for readiness. Reads status registers and waits
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* for the command register to indicate idle.
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*/
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static BOOL bcm_poll_ready(void) {
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BYTE i, val;
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for (i = 0; i < 20; i++) {
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if (bcm_direct_read(BCM_REG_CMD, &val)) {
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if (!(val & 0x01))
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return TRUE;
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}
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delay(5);
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}
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return FALSE;
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}
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/* ---------- GPIF streaming ---------- */
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static void gpif_start(void) {
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if (config_status & BM_ARMED)
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return;
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config_status |= BM_ARMED;
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/* IFCONFIG: internal 48MHz, GPIF master, async, clock output */
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IFCONFIG = 0xEE;
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SYNCDELAY;
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/* EP2FIFOCFG: AUTOIN, ZEROLENIN, 8-bit */
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EP2FIFOCFG = 0x0C;
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SYNCDELAY;
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/* FLOWSTATE: enable flow state + FS[3] */
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FLOWSTATE |= 0x09;
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/* Set transaction count large (effectively infinite) */
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GPIFTCB3 = 0x80;
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SYNCDELAY;
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GPIFTCB2 = 0x00;
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SYNCDELAY;
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GPIFTCB1 = 0x00;
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SYNCDELAY;
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GPIFTCB0 = 0x00;
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SYNCDELAY;
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/* Assert P3.5 low (BCM4500 TS enable) briefly */
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IOD &= ~0x20;
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/* Wait for GPIF idle */
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while (!(GPIFTRIG & 0x80))
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;
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IOD |= 0x20;
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/* Trigger continuous GPIF read into EP2 */
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GPIFTRIG = 0x04;
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/* P0.7 low = streaming indicator */
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IOA &= ~0x80;
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}
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static void gpif_stop(void) {
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if (!(config_status & BM_ARMED))
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return;
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/* P0.7 high = streaming stopped */
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IOA |= 0x80;
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/* Force-flush current FIFO buffer */
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EP2FIFOBCH = 0xFF;
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SYNCDELAY;
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/* Wait for GPIF idle */
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while (!(GPIFTRIG & 0x80))
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;
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/* Skip/discard partial EP2 packet */
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OUTPKTEND = 0x82;
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SYNCDELAY;
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config_status &= ~BM_ARMED;
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/* De-assert all BCM4500 control lines on P3 */
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IOD |= 0xE0;
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}
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/* ---------- DiSEqC tone burst ---------- */
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/*
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* Send a tone burst (mini DiSEqC). This is the simpler variant.
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* Tone burst A: unmodulated 22kHz for 12.5ms
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* Tone burst B: modulated (not implemented yet)
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*
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* Uses Timer2 for timing as the stock firmware does.
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*/
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static void diseqc_tone_burst(BYTE sat_b) {
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BYTE i;
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(void)sat_b; /* both A and B send 22kHz burst for now */
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/* Configure Timer2 auto-reload */
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/* CKCON.T2M = 0 -> Timer2 clk = 48MHz/12 = 4MHz */
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CKCON &= ~0x20;
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T2CON = 0x04; /* auto-reload, running */
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RCAP2H = 0xF8;
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RCAP2L = 0x2F; /* reload = 63535 -> ~500us tick */
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TL2 = 0xFF;
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TH2 = 0xFF; /* force immediate overflow */
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/* Pre-burst settling: 15 ticks (~7.5ms) with carrier off */
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IOA &= ~PIN_22KHZ;
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TF2 = 0;
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for (i = 0; i < 15; i++) {
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while (!TF2)
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;
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TF2 = 0;
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}
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/* Burst: 25 ticks (~12.5ms) with carrier on */
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IOA |= PIN_22KHZ;
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for (i = 0; i < 25; i++) {
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while (!TF2)
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;
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TF2 = 0;
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}
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/* Carrier off */
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IOA &= ~PIN_22KHZ;
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/* Post-burst settling: 5 ticks (~2.5ms) */
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for (i = 0; i < 5; i++) {
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while (!TF2)
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;
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TF2 = 0;
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}
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/* Stop Timer2 */
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TR2 = 0;
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}
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/* ---------- Spectrum sweep (0xB0) ---------- */
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/*
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* Step through frequencies from start to stop, reading signal strength
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* at each step. Results are packed as u16 LE power values into EP2 bulk.
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*
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* The host sends a 10-byte payload via EP0:
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* [0..3] start_freq (u32 LE, kHz)
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* [4..7] stop_freq (u32 LE, kHz)
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* [8..9] step_khz (u16 LE)
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*
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* We tune to each frequency with a fixed symbol rate (e.g. 20000 sps, DVB-S
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* QPSK auto-FEC), read the SNR register, and pack u16 results into EP2.
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*
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* The sweep uses a simple approach: program freq via BCM4500 indirect write
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* at each step, wait briefly, and read the signal energy register.
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*/
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static void do_spectrum_sweep(void) {
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static __xdata DWORD start_freq, stop_freq, cur_freq;
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static __xdata WORD step_khz;
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WORD buf_idx;
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BYTE snr_lo, snr_hi;
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/* Parse the 10-byte EP0 payload */
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start_freq = (DWORD)EP0BUF[0] |
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((DWORD)EP0BUF[1] << 8) |
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((DWORD)EP0BUF[2] << 16) |
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((DWORD)EP0BUF[3] << 24);
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stop_freq = (DWORD)EP0BUF[4] |
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((DWORD)EP0BUF[5] << 8) |
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((DWORD)EP0BUF[6] << 16) |
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((DWORD)EP0BUF[7] << 24);
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step_khz = (WORD)EP0BUF[8] | ((WORD)EP0BUF[9] << 8);
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if (step_khz == 0)
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step_khz = 1000;
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buf_idx = 0;
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cur_freq = start_freq;
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while (cur_freq <= stop_freq) {
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/*
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* Program frequency into BCM4500 via indirect write.
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* The BCM4500 expects big-endian frequency bytes at page 0.
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* We write 4 freq bytes (BE) to the data register.
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*/
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i2c_buf[0] = (BYTE)(cur_freq >> 24);
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i2c_buf[1] = (BYTE)(cur_freq >> 16);
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i2c_buf[2] = (BYTE)(cur_freq >> 8);
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i2c_buf[3] = (BYTE)(cur_freq);
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bcm_indirect_write_block(0x00, i2c_buf, 4);
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/* Wait for demod to settle */
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delay(10);
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/* Read signal strength via indirect register */
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snr_lo = 0;
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snr_hi = 0;
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bcm_indirect_read(0x00, &snr_lo);
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bcm_indirect_read(0x01, &snr_hi);
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/* Store u16 LE into EP2 FIFO buffer */
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if (buf_idx < 1024 - 1) {
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EP2FIFOBUF[buf_idx++] = snr_lo;
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EP2FIFOBUF[buf_idx++] = snr_hi;
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}
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/* If buffer is nearly full, commit this chunk */
|
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if (buf_idx >= 512) {
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EP2BCH = MSB(buf_idx);
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SYNCDELAY;
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EP2BCL = LSB(buf_idx);
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SYNCDELAY;
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buf_idx = 0;
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|
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/* Wait for the buffer to be taken by host */
|
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while (EP2CS & bmEPFULL)
|
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;
|
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}
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|
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cur_freq += step_khz;
|
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}
|
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|
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/* Commit any remaining data */
|
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if (buf_idx > 0) {
|
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EP2BCH = MSB(buf_idx);
|
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SYNCDELAY;
|
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EP2BCL = LSB(buf_idx);
|
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SYNCDELAY;
|
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}
|
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}
|
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|
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/* ---------- Blind scan (0xB3) ---------- */
|
|
|
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/*
|
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* Try symbol rates from sr_min to sr_max in sr_step increments
|
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* at a given frequency, looking for signal lock.
|
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*
|
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* EP0 payload (16 bytes):
|
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* [0..3] freq_khz (u32 LE)
|
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* [4..7] sr_min (u32 LE, sps)
|
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* [8..11] sr_max (u32 LE, sps)
|
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* [12..15] sr_step (u32 LE, sps)
|
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*
|
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* Returns via EP0: 8 bytes on lock [freq_khz(4) + sr_locked(4)]
|
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* or 1 byte 0x00 if no lock found.
|
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*/
|
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static BOOL do_blind_scan(void) {
|
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static __xdata DWORD freq_khz, sr_min, sr_max, sr_step, sr_cur;
|
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BYTE lock_val;
|
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|
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freq_khz = (DWORD)EP0BUF[0] |
|
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((DWORD)EP0BUF[1] << 8) |
|
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((DWORD)EP0BUF[2] << 16) |
|
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((DWORD)EP0BUF[3] << 24);
|
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sr_min = (DWORD)EP0BUF[4] |
|
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((DWORD)EP0BUF[5] << 8) |
|
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((DWORD)EP0BUF[6] << 16) |
|
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((DWORD)EP0BUF[7] << 24);
|
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sr_max = (DWORD)EP0BUF[8] |
|
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((DWORD)EP0BUF[9] << 8) |
|
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((DWORD)EP0BUF[10] << 16) |
|
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((DWORD)EP0BUF[11] << 24);
|
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sr_step = (DWORD)EP0BUF[12] |
|
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((DWORD)EP0BUF[13] << 8) |
|
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((DWORD)EP0BUF[14] << 16) |
|
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((DWORD)EP0BUF[15] << 24);
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|
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if (sr_step == 0)
|
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sr_step = 1000000;
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|
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sr_cur = sr_min;
|
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while (sr_cur <= sr_max) {
|
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/*
|
|
* Program frequency (BE) and symbol rate (BE) into BCM4500.
|
|
* We write both in a single block: 4 bytes SR + 4 bytes freq.
|
|
*/
|
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i2c_buf[0] = (BYTE)(sr_cur >> 24);
|
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i2c_buf[1] = (BYTE)(sr_cur >> 16);
|
|
i2c_buf[2] = (BYTE)(sr_cur >> 8);
|
|
i2c_buf[3] = (BYTE)(sr_cur);
|
|
bcm_indirect_write_block(0x00, i2c_buf, 4);
|
|
|
|
i2c_buf[0] = (BYTE)(freq_khz >> 24);
|
|
i2c_buf[1] = (BYTE)(freq_khz >> 16);
|
|
i2c_buf[2] = (BYTE)(freq_khz >> 8);
|
|
i2c_buf[3] = (BYTE)(freq_khz);
|
|
bcm_indirect_write_block(0x00, i2c_buf, 4);
|
|
|
|
/* Issue tune command */
|
|
bcm_direct_write(BCM_REG_CMD, BCM_CMD_WRITE);
|
|
|
|
/* Wait for acquisition attempt */
|
|
delay(100);
|
|
|
|
/* Check lock */
|
|
lock_val = 0;
|
|
bcm_direct_read(BCM_REG_LOCK, &lock_val);
|
|
if (lock_val & 0x20) {
|
|
/* Locked -- report back via EP0 */
|
|
EP0BUF[0] = (BYTE)(freq_khz);
|
|
EP0BUF[1] = (BYTE)(freq_khz >> 8);
|
|
EP0BUF[2] = (BYTE)(freq_khz >> 16);
|
|
EP0BUF[3] = (BYTE)(freq_khz >> 24);
|
|
EP0BUF[4] = (BYTE)(sr_cur);
|
|
EP0BUF[5] = (BYTE)(sr_cur >> 8);
|
|
EP0BUF[6] = (BYTE)(sr_cur >> 16);
|
|
EP0BUF[7] = (BYTE)(sr_cur >> 24);
|
|
EP0BCH = 0;
|
|
EP0BCL = 8;
|
|
return TRUE;
|
|
}
|
|
|
|
sr_cur += sr_step;
|
|
}
|
|
|
|
/* No lock found */
|
|
EP0BUF[0] = 0x00;
|
|
EP0BCH = 0;
|
|
EP0BCL = 1;
|
|
return FALSE;
|
|
}
|
|
|
|
/* ---------- TUNE_8PSK (0x86) handler ---------- */
|
|
|
|
/*
|
|
* Parse 10-byte EP0 payload, program BCM4500 via I2C indirect registers.
|
|
* Follows the stock firmware's protocol:
|
|
* EP0BUF[0..3] = symbol_rate (LE u32, sps)
|
|
* EP0BUF[4..7] = freq_khz (LE u32, kHz)
|
|
* EP0BUF[8] = modulation index (0-9)
|
|
* EP0BUF[9] = FEC index
|
|
*/
|
|
static void do_tune(void) {
|
|
BYTE i;
|
|
__xdata BYTE tune_data[12];
|
|
|
|
if (!(config_status & BM_STARTED))
|
|
return;
|
|
|
|
/*
|
|
* Byte-reverse symbol rate (LE->BE) into tune_data[0..3]
|
|
* and frequency (LE->BE) into tune_data[4..7]
|
|
*/
|
|
for (i = 0; i < 4; i++) {
|
|
tune_data[i] = EP0BUF[3 - i]; /* SR BE */
|
|
tune_data[4 + i] = EP0BUF[7 - i]; /* Freq BE */
|
|
}
|
|
|
|
/* Modulation type and FEC rate */
|
|
tune_data[8] = EP0BUF[8];
|
|
tune_data[9] = EP0BUF[9];
|
|
|
|
/* Demod mode: default standard (0x10) */
|
|
tune_data[10] = 0x10;
|
|
|
|
/* Turbo flag: 0x00 for DVB-S, 0x01 for turbo modes */
|
|
tune_data[11] = 0x00;
|
|
if (EP0BUF[8] >= 1 && EP0BUF[8] <= 3)
|
|
tune_data[11] = 0x01;
|
|
|
|
/* Set demod mode for DCII variants */
|
|
switch (EP0BUF[8]) {
|
|
case 5: tune_data[10] = 0x12; break; /* DCII I-stream */
|
|
case 6: tune_data[10] = 0x16; break; /* DCII Q-stream */
|
|
case 7: tune_data[10] = 0x11; break; /* DCII Offset QPSK */
|
|
default: break;
|
|
}
|
|
|
|
/* Poll BCM4500 for readiness */
|
|
bcm_poll_ready();
|
|
|
|
/* Write page 0 */
|
|
bcm_direct_write(BCM_REG_PAGE, 0x00);
|
|
|
|
/* Write all configuration data to BCM4500 data register */
|
|
{
|
|
BYTE reg = BCM_REG_DATA;
|
|
i2c_write(BCM4500_ADDR, 1, ®, 12, tune_data);
|
|
}
|
|
|
|
/* Execute indirect write */
|
|
bcm_direct_write(BCM_REG_CMD, BCM_CMD_WRITE);
|
|
|
|
/* Wait for command completion */
|
|
bcm_poll_ready();
|
|
}
|
|
|
|
/* ---------- Vendor command handler ---------- */
|
|
|
|
BOOL handle_vendorcommand(BYTE cmd) {
|
|
WORD wval;
|
|
BYTE val;
|
|
|
|
wval = SETUP_VALUE();
|
|
|
|
switch (cmd) {
|
|
|
|
/* 0x80: GET_8PSK_CONFIG -- return config status byte */
|
|
case GET_8PSK_CONFIG:
|
|
EP0BUF[0] = config_status;
|
|
EP0BCH = 0;
|
|
EP0BCL = 1;
|
|
return TRUE;
|
|
|
|
/* 0x85: ARM_TRANSFER -- start/stop MPEG-2 streaming */
|
|
case ARM_TRANSFER:
|
|
if (wval)
|
|
gpif_start();
|
|
else
|
|
gpif_stop();
|
|
return TRUE;
|
|
|
|
/* 0x86: TUNE_8PSK -- 10-byte tuning payload */
|
|
case TUNE_8PSK:
|
|
/* EP0 data phase: wait for 10 bytes from host */
|
|
EP0BCL = 0;
|
|
SYNCDELAY;
|
|
while (EP0CS & bmEPBUSY)
|
|
;
|
|
do_tune();
|
|
return TRUE;
|
|
|
|
/* 0x87: GET_SIGNAL_STRENGTH -- read 6 bytes from BCM4500 */
|
|
case GET_SIGNAL_STRENGTH:
|
|
if (!(config_status & BM_STARTED)) {
|
|
EP0BUF[0] = 0; EP0BUF[1] = 0;
|
|
EP0BUF[2] = 0; EP0BUF[3] = 0;
|
|
EP0BUF[4] = 0; EP0BUF[5] = 0;
|
|
EP0BCH = 0;
|
|
EP0BCL = 6;
|
|
return TRUE;
|
|
}
|
|
/* Read signal quality via indirect registers */
|
|
bcm_indirect_read(0x00, &EP0BUF[0]);
|
|
bcm_indirect_read(0x01, &EP0BUF[1]);
|
|
bcm_indirect_read(0x02, &EP0BUF[2]);
|
|
bcm_indirect_read(0x03, &EP0BUF[3]);
|
|
bcm_indirect_read(0x04, &EP0BUF[4]);
|
|
bcm_indirect_read(0x05, &EP0BUF[5]);
|
|
EP0BCH = 0;
|
|
EP0BCL = 6;
|
|
return TRUE;
|
|
|
|
/* 0x89: BOOT_8PSK -- initialize BCM4500 demodulator */
|
|
case BOOT_8PSK:
|
|
if (wval) {
|
|
/* Power on: scan for BCM4500 at address 0x10 */
|
|
val = 0;
|
|
if (bcm_direct_read(BCM_REG_STATUS, &val)) {
|
|
config_status |= BM_STARTED;
|
|
config_status |= BM_FW_LOADED;
|
|
}
|
|
} else {
|
|
config_status &= ~BM_STARTED;
|
|
}
|
|
EP0BUF[0] = config_status;
|
|
EP0BCH = 0;
|
|
EP0BCL = 1;
|
|
return TRUE;
|
|
|
|
/* 0x8A: START_INTERSIL -- enable LNB power supply */
|
|
case START_INTERSIL:
|
|
if (wval) {
|
|
/* Enable LNB power */
|
|
OEA |= (PIN_22KHZ | PIN_LNB_VOLT | PIN_DISEQC);
|
|
config_status |= BM_INTERSIL;
|
|
} else {
|
|
config_status &= ~BM_INTERSIL;
|
|
}
|
|
EP0BUF[0] = config_status;
|
|
EP0BCH = 0;
|
|
EP0BCL = 1;
|
|
return TRUE;
|
|
|
|
/* 0x8B: SET_LNB_VOLTAGE -- 13V (wval=0) or 18V (wval=1) */
|
|
case SET_LNB_VOLTAGE:
|
|
if (wval) {
|
|
IOA |= PIN_LNB_VOLT;
|
|
config_status |= BM_SEL18V;
|
|
} else {
|
|
IOA &= ~PIN_LNB_VOLT;
|
|
config_status &= ~BM_SEL18V;
|
|
}
|
|
return TRUE;
|
|
|
|
/* 0x8C: SET_22KHZ_TONE -- on (wval=1) or off (wval=0) */
|
|
case SET_22KHZ_TONE:
|
|
if (wval) {
|
|
IOA |= PIN_22KHZ;
|
|
config_status |= BM_22KHZ;
|
|
} else {
|
|
IOA &= ~PIN_22KHZ;
|
|
config_status &= ~BM_22KHZ;
|
|
}
|
|
return TRUE;
|
|
|
|
/* 0x8D: SEND_DISEQC -- tone burst or DiSEqC message */
|
|
case SEND_DISEQC: {
|
|
WORD wlen;
|
|
wlen = SETUP_LENGTH();
|
|
if (wlen == 0) {
|
|
/* Tone burst: A if wval==0, B if wval!=0 */
|
|
diseqc_tone_burst((BYTE)wval);
|
|
}
|
|
/* Full DiSEqC message: future implementation */
|
|
return TRUE;
|
|
}
|
|
|
|
/* 0x90: GET_SIGNAL_LOCK -- read BCM4500 lock register */
|
|
case GET_SIGNAL_LOCK:
|
|
val = 0;
|
|
if (config_status & BM_STARTED) {
|
|
bcm_direct_read(BCM_REG_LOCK, &val);
|
|
}
|
|
EP0BUF[0] = val;
|
|
EP0BCH = 0;
|
|
EP0BCL = 1;
|
|
return TRUE;
|
|
|
|
/* 0x92: GET_FW_VERS -- return firmware version and build date */
|
|
case GET_FW_VERS:
|
|
EP0BUF[0] = 0x01; /* patch -> version 3.00.1 */
|
|
EP0BUF[1] = 0x00; /* minor */
|
|
EP0BUF[2] = 0x03; /* major */
|
|
EP0BUF[3] = 0x0B; /* day = 11 */
|
|
EP0BUF[4] = 0x02; /* month = 2 */
|
|
EP0BUF[5] = 0x1A; /* year - 2000 = 26 */
|
|
EP0BCH = 0;
|
|
EP0BCL = 6;
|
|
return TRUE;
|
|
|
|
/* 0x94: USE_EXTRA_VOLT -- enable +1V LNB boost */
|
|
case USE_EXTRA_VOLT:
|
|
/* This would write to the LNB regulator; no-op for now */
|
|
return TRUE;
|
|
|
|
/* --- Custom commands --- */
|
|
|
|
/* 0xB0: SPECTRUM_SWEEP */
|
|
case SPECTRUM_SWEEP:
|
|
/* EP0 data phase: wait for 10 bytes from host */
|
|
EP0BCL = 0;
|
|
SYNCDELAY;
|
|
while (EP0CS & bmEPBUSY)
|
|
;
|
|
do_spectrum_sweep();
|
|
return TRUE;
|
|
|
|
/* 0xB1: RAW_DEMOD_READ -- read BCM4500 register */
|
|
case RAW_DEMOD_READ:
|
|
val = 0;
|
|
bcm_indirect_read((BYTE)wval, &val);
|
|
EP0BUF[0] = val;
|
|
EP0BCH = 0;
|
|
EP0BCL = 1;
|
|
return TRUE;
|
|
|
|
/* 0xB2: RAW_DEMOD_WRITE -- write BCM4500 register */
|
|
case RAW_DEMOD_WRITE: {
|
|
WORD widx;
|
|
widx = SETUP_INDEX();
|
|
bcm_indirect_write((BYTE)wval, (BYTE)widx);
|
|
return TRUE;
|
|
}
|
|
|
|
/* 0xB3: BLIND_SCAN */
|
|
case BLIND_SCAN:
|
|
/* EP0 data phase: wait for 16 bytes from host */
|
|
EP0BCL = 0;
|
|
SYNCDELAY;
|
|
while (EP0CS & bmEPBUSY)
|
|
;
|
|
do_blind_scan();
|
|
return TRUE;
|
|
|
|
/* 0xB4: I2C_BUS_SCAN -- probe all 7-bit addresses, return 16-byte bitmap */
|
|
case 0xB4: {
|
|
BYTE a, byte_idx, bit;
|
|
/* 128 addresses / 8 = 16 bytes bitmap */
|
|
for (byte_idx = 0; byte_idx < 16; byte_idx++)
|
|
EP0BUF[byte_idx] = 0;
|
|
|
|
for (a = 1; a < 0x78; a++) {
|
|
/* Try START + address + write, see if ACK comes back */
|
|
I2CS |= bmSTART;
|
|
I2DAT = a << 1; /* write direction */
|
|
while (!(I2CS & bmDONE))
|
|
;
|
|
if (I2CS & bmACK) {
|
|
/* Device responded at this address */
|
|
byte_idx = a >> 3;
|
|
bit = a & 0x07;
|
|
EP0BUF[byte_idx] |= (1 << bit);
|
|
}
|
|
I2CS |= bmSTOP;
|
|
while (I2CS & bmSTOP)
|
|
;
|
|
}
|
|
EP0BCH = 0;
|
|
EP0BCL = 16;
|
|
return TRUE;
|
|
}
|
|
|
|
/* 0xB5: I2C_RAW_READ -- read N bytes from any I2C address
|
|
* wValue = 7-bit I2C address, wIndex = register, wLength = bytes to read
|
|
* Uses combined write-read with repeated START */
|
|
case 0xB5: {
|
|
BYTE i2c_addr_b5 = (BYTE)wval;
|
|
BYTE i2c_reg_b5 = (BYTE)SETUP_INDEX();
|
|
BYTE i2c_len_b5 = (BYTE)SETUP_LENGTH();
|
|
BYTE ok;
|
|
|
|
if (i2c_len_b5 > 64) i2c_len_b5 = 64;
|
|
|
|
ok = i2c_combined_read(i2c_addr_b5, i2c_reg_b5, i2c_len_b5, EP0BUF);
|
|
if (!ok) {
|
|
BYTE fi;
|
|
for (fi = 0; fi < i2c_len_b5; fi++)
|
|
EP0BUF[fi] = 0xFF;
|
|
}
|
|
EP0BCH = 0;
|
|
EP0BCL = i2c_len_b5;
|
|
return TRUE;
|
|
}
|
|
|
|
/* 0xB6: I2C_DIAG -- step-by-step indirect register read diagnostic
|
|
* wValue = page/register to read
|
|
* Returns 8 bytes: [write_A6_ok, readback_A6, write_A8_ok, readback_A8,
|
|
* readback_A7, direct_read_A6, direct_read_A7, direct_read_A8] */
|
|
case 0xB6: {
|
|
BYTE target_reg = (BYTE)wval;
|
|
BYTE diag[8];
|
|
BYTE rb;
|
|
|
|
/* Step 1: Write target register to page select (0xA6) */
|
|
diag[0] = bcm_direct_write(BCM_REG_PAGE, target_reg) ? 0x01 : 0x00;
|
|
|
|
/* Step 2: Read back 0xA6 to verify write */
|
|
rb = 0xEE;
|
|
i2c_combined_read(BCM4500_ADDR, BCM_REG_PAGE, 1, &rb);
|
|
diag[1] = rb;
|
|
|
|
/* Step 3: Write read command (0x01) to 0xA8 */
|
|
diag[2] = bcm_direct_write(BCM_REG_CMD, BCM_CMD_READ) ? 0x01 : 0x00;
|
|
|
|
/* Step 4: Read back 0xA8 to check command status */
|
|
rb = 0xEE;
|
|
i2c_combined_read(BCM4500_ADDR, BCM_REG_CMD, 1, &rb);
|
|
diag[3] = rb;
|
|
|
|
/* Step 5: Small delay for command execution */
|
|
delay(2);
|
|
|
|
/* Step 6: Read 0xA7 (data register) — this is the result */
|
|
rb = 0xEE;
|
|
i2c_combined_read(BCM4500_ADDR, BCM_REG_DATA, 1, &rb);
|
|
diag[4] = rb;
|
|
|
|
/* Step 7: Read back all three control regs for final state */
|
|
rb = 0xEE;
|
|
i2c_combined_read(BCM4500_ADDR, BCM_REG_PAGE, 1, &rb);
|
|
diag[5] = rb;
|
|
rb = 0xEE;
|
|
i2c_combined_read(BCM4500_ADDR, BCM_REG_DATA, 1, &rb);
|
|
diag[6] = rb;
|
|
rb = 0xEE;
|
|
i2c_combined_read(BCM4500_ADDR, BCM_REG_CMD, 1, &rb);
|
|
diag[7] = rb;
|
|
|
|
EP0BUF[0] = diag[0];
|
|
EP0BUF[1] = diag[1];
|
|
EP0BUF[2] = diag[2];
|
|
EP0BUF[3] = diag[3];
|
|
EP0BUF[4] = diag[4];
|
|
EP0BUF[5] = diag[5];
|
|
EP0BUF[6] = diag[6];
|
|
EP0BUF[7] = diag[7];
|
|
EP0BCH = 0;
|
|
EP0BCL = 8;
|
|
return TRUE;
|
|
}
|
|
|
|
default:
|
|
return FALSE;
|
|
}
|
|
}
|
|
|
|
/* ---------- Required fx2lib callbacks ---------- */
|
|
|
|
BOOL handle_get_descriptor(void) {
|
|
return FALSE;
|
|
}
|
|
|
|
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc) {
|
|
if (ifc == 0) {
|
|
*alt_ifc = 0;
|
|
return TRUE;
|
|
}
|
|
return FALSE;
|
|
}
|
|
|
|
BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc) {
|
|
if (ifc == 0 && alt_ifc == 0) {
|
|
RESETTOGGLE(0x82);
|
|
RESETFIFO(0x02);
|
|
return TRUE;
|
|
}
|
|
return FALSE;
|
|
}
|
|
|
|
BYTE handle_get_configuration(void) {
|
|
return 1;
|
|
}
|
|
|
|
BOOL handle_set_configuration(BYTE cfg) {
|
|
return cfg == 1 ? TRUE : FALSE;
|
|
}
|
|
|
|
/* ---------- USB interrupt handlers ---------- */
|
|
|
|
void sudav_isr(void) __interrupt (SUDAV_ISR) {
|
|
got_sud = TRUE;
|
|
CLEAR_SUDAV();
|
|
}
|
|
|
|
void usbreset_isr(void) __interrupt (USBRESET_ISR) {
|
|
handle_hispeed(FALSE);
|
|
CLEAR_USBRESET();
|
|
}
|
|
|
|
void hispeed_isr(void) __interrupt (HISPEED_ISR) {
|
|
handle_hispeed(TRUE);
|
|
CLEAR_HISPEED();
|
|
}
|
|
|
|
/* ---------- Main ---------- */
|
|
|
|
void main(void) {
|
|
|
|
config_status = 0;
|
|
got_sud = FALSE;
|
|
|
|
REVCTL = 0x03; /* NOAUTOARM + SKIPCOMMIT */
|
|
SYNCDELAY;
|
|
|
|
RENUMERATE_UNCOND();
|
|
|
|
SETCPUFREQ(CLK_48M);
|
|
SETIF48MHZ();
|
|
|
|
USE_USB_INTS();
|
|
ENABLE_SUDAV();
|
|
ENABLE_HISPEED();
|
|
ENABLE_USBRESET();
|
|
|
|
/* Configure I2C: 400kHz */
|
|
I2CTL = bm400KHZ;
|
|
|
|
/* Configure GPIO output enables for LNB/tone/DiSEqC (v2.06 pin map) */
|
|
OEA |= (PIN_22KHZ | PIN_LNB_VOLT | PIN_DISEQC); /* P0.3, P0.4, P0.7 output */
|
|
|
|
/* Initial GPIO state: LNB off, tone off, DiSEqC idle */
|
|
IOA = 0x84; /* P0.7=1 (idle), P0.2=1 (BCM4500 control) */
|
|
IOD = 0xE1; /* P3.7:5=1 (controls idle), P3.0=1 */
|
|
|
|
/* EP2 is bulk IN (0x82), 512 byte, double-buffered */
|
|
EP2CFG = 0xE2; /* valid, IN, bulk, 512, double */
|
|
SYNCDELAY;
|
|
|
|
/* Disable unused endpoints */
|
|
EP1INCFG &= ~bmVALID;
|
|
SYNCDELAY;
|
|
EP1OUTCFG &= ~bmVALID;
|
|
SYNCDELAY;
|
|
EP4CFG &= ~bmVALID;
|
|
SYNCDELAY;
|
|
EP6CFG &= ~bmVALID;
|
|
SYNCDELAY;
|
|
EP8CFG &= ~bmVALID;
|
|
SYNCDELAY;
|
|
|
|
/* Reset all FIFOs */
|
|
RESETFIFOS();
|
|
|
|
/* IFCONFIG: internal 48MHz, GPIF master, async */
|
|
IFCONFIG = 0xEE;
|
|
SYNCDELAY;
|
|
|
|
/* EP2FIFOCFG: AUTOIN, ZEROLENIN, 8-bit */
|
|
EP2FIFOCFG = 0x0C;
|
|
SYNCDELAY;
|
|
|
|
/* Disable other FIFO configs */
|
|
EP4FIFOCFG = 0;
|
|
SYNCDELAY;
|
|
EP6FIFOCFG = 0;
|
|
SYNCDELAY;
|
|
EP8FIFOCFG = 0;
|
|
SYNCDELAY;
|
|
|
|
EA = 1; /* global interrupt enable */
|
|
|
|
while (TRUE) {
|
|
if (got_sud) {
|
|
handle_setupdata();
|
|
got_sud = FALSE;
|
|
}
|
|
}
|
|
}
|