2 Commits

Author	SHA1	Message	Date
Ryan Malloy	33b6aa92db	Update EEPROM recovery guide with I2C bus latch root cause ... Replaces speculative "corrupted boot data" with confirmed I2C bus latch diagnosis from 100+ failed power cycle attempts. Mark Option D (wait + watch) as exhausted. Add pending firmware fixes table for post-recovery testing.	2026-02-20 12:04:18 -07:00
Ryan Malloy	3d2cd477b2	Add EEPROM boot firmware (exp 0xDB) and supporting tools ... Firmware: Rewrite skywalker1.c for EEPROM boot experiment — tests whether I2C hardware controller works after FX2 boot ROM completes EEPROM load (bypassing the CPUCS restart that triggers BERR). Tools: - fw_load.py: Add I2C cleanup stub, pre-halt register flush, improved error handling and segment loading - eeprom_write.py: Add IHX→C2 EEPROM image converter (16KB format with length-prefixed segments, checksum) - eeprom_dump.py: Refactor for cleaner output, better hex display - skywalker_lib.py: Minor I2C register constant updates Docs: - EEPROM-RECOVERY.md: Four recovery options for soft-bricked device (SOIC clip, SDA pull-up, desolder, wait-for-timeout) - Master reference: Updated with EEPROM boot findings Status: EEPROM flash blocked — stock firmware I2C proxy returns pipe errors, host-side 0xA0 writes proven unable to drive peripheral bus. Device boot ROM intermittently hangs on EEPROM I2C read (~3-6% success).	2026-02-20 10:56:21 -07:00