birdcage/docs/K60-refman-vectors/K60-reference-manual_page_422.svg

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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="11.85" x="13.104 23.996003 33.334005 37.996004 44.212 50.428 54.320005 58.212007 65.212009 72.212009 75.712009 81.92801 85.42801 92.42801 98.64401 108.752017 112.252017 123.14401 129.36002 140.25202 147.25202 151.91402 158.91402 162.41402 167.07602 173.29203 180.29203 184.18402 191.18402 198.18402 212.18402 220.73802 227.73802 233.95403 240.95403 244.45403 248.34603 255.34603 261.562 265.062 271.278 278.278 285.278 289.94 296.94 303.94 308.602 312.494 318.71 322.602 328.818 332.318 336.97999 343.19599 350.19599 354.08799 361.08799 368.08799 371.58799 378.58799 384.804 390.25 396.466 401.128 405.02 412.02 415.912 422.912 427.57398 431.07398 434.96598 441.96598 445.85798 452.85798 456.35798 462.57398">&#x2022;Creating a new memory region&#x2014;Load the appropriate region descriptor into an</tspan><tspan y="27.85" x="23.99601 30.21201 37.21201 43.42801 47.32001 51.212015 57.428014 64.42801 68.32001 74.53601 78.03601 87.37401 97.48201">available RGD</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="27.85" x="114.59001 118.09001 121.59001 128.59001 134.03601 137.92801 144.92801 151.92801 155.42801 160.09001 167.09001 174.09001 178.75202 182.25202 187.69802 193.91402 200.91402 207.91402 214.13002 221.13002 225.02202 228.91402 235.13002 239.02202 242.52202 249.52202 256.52204 261.18403 268.18403 272.07603 275.96803 279.46803 289.57603 294.238 298.13 302.022 308.238 313.68403 317.18403 320.68403 329.238 336.238 342.454 345.954 352.954 359.17 363.832 370.832 380.94 387.156 391.818 398.034 401.534 407.75 413.196 418.64204 422.53404 427.98005 431.87205 437.31806 440.81806 444.71006 451.71006 455.21006 459.10206 466.10206">, using four sequential 32-bit writes. The hardware assists in the</tspan><tspan y="43.85" x="23.99601 34.888013 41.10401 44.996015 51.996015 55.888017 62.104017 69.10402 75.32002 82.32002 88.536029 94.75203 98.25203 105.25203 109.91403 113.41403 117.30603 124.30603 130.52204 134.02204 141.02204 147.23804 151.13004 155.02204 162.02204 165.52204 172.52204 176.41403 180.30603 183.80603 187.30603 192.75203 199.75203 203.25203 207.14403 211.80603 215.30603 219.19803 226.19803 230.09003 235.53603 239.03603 245.25203 252.25203 259.252 263.914 270.914 277.13 283.346 290.346 293.846 297.738 303.18403 306.68403 311.346 318.346 322.238 326.13 333.13 343.238 349.454 356.454 359.954 363.454 367.346 374.346 380.562 385.224 391.44 394.94 401.156 405.818 412.034 415.534 422.534 429.534 433.034 439.25 446.25 453.25 459.466 464.128 470.344 477.344 483.56">maintenance of the valid bit, so if this approach is followed, there are no coherency</tspan><tspan y="59.85" x="23.99601 27.88801 33.33401 38.78001 45.78001 51.99601 57.44201 60.94201 71.05001 74.94201 78.83401 85.83401 89.33401 93.226009 100.226009 106.44201 109.94201 120.83401 127.83401 131.72602 135.61801 139.51001 144.17201 150.38802 157.38802 163.60402 167.49602 173.71202 177.21202 184.21202 190.42803 195.87403 202.09003 206.75203 210.64403 217.64403 221.53603 228.53603 233.19803 236.69803 246.80603 251.46804 255.36003 259.25205 265.46806 270.91407 274.41407 277.91407 282.57606 291.91407 295.80607 302.02207 308.23808 312.90007 316.79206 323.79206 330.79206 334.29206 343.63008 353.73808">issues with the multi-cycle descriptor writes. (Clearing RGD</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="59.85" x="370.846 377.846 391.062 398.062 402.724 409.724 416.724 421.386 431.494 440.04798 450.15599 454.81797 458.31797 465.31797 471.53398 475.42597 481.64198 485.53398 491.74998 497.19599">_Word3[VLD] deletes/</tspan><tspan y="75.85" x="23.996003 28.658003 34.874006 45.766008 52.766008 59.766008 65.98201 71.42801 74.92801 81.14401 88.14401 91.64401 97.860019 104.860019 108.752017 114.19801 118.09001 121.98201 128.98201 135.98201 139.48201 150.37401 156.59001 167.48201 174.48201 179.14402 186.14402 189.64402 194.30602 200.52202 207.52202 211.41402 218.41402 225.41402 228.91402">removes an existing memory region.)</tspan><tspan y="100.25" x="13.104002 23.996003 34.104005 37.996007 41.88801 48.104009 52.766008 56.65801 63.65801 70.658008 74.158008 81.158008 88.158008 92.05 99.05 102.55 108.76601 114.98201 121.19801 127.41402 132.86002 138.30602 141.80602 148.80602 153.46802 157.36002 164.36002 168.25202 172.14402 178.36002 185.36002 191.57602 197.02202 211.02202 219.57602 226.57602 230.07602 237.07602 244.07602 247.96802 251.46802 257.68403 262.346 267.008 273.224 279.44 283.332 286.832 290.724 297.724 303.94 307.44 314.44 320.656 324.548 328.44 335.44 338.94 345.94 349.832 353.724 357.224 360.724 370.832 375.494 379.386 383.27799 389.494 392.994 396.886 403.886 407.386 411.27799 418.27799 424.494 427.994 434.21 438.102 441.994 448.21 452.87199 459.87199 466.08799 469.97999">&#x2022;Altering only access privileges&#x2014;To not affect the valid bit, write to the alternate</tspan><tspan y="116.25" x="23.996033 30.996033 37.212034 41.87403 47.32003 51.212034 58.212034 65.212039 68.712039 75.712039 80.37404 83.87404 87.76604 94.76604 100.98204 104.48204 110.698047 116.91405 123.13005 129.34606 134.79206 140.23805 143.73805 149.95406 156.95406 163.95406 167.84606 172.50806 179.50806 183.40006 186.90006 197.00806 204.00806 208.67006 215.67006 219.17006 223.83206 233.17006 243.27806 253.38607 263.49406 273.60206">version of the access control word (RGDAAC</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="116.25" x="289.94004 294.60203 298.10203 301.60203 307.04804 314.04804 317.54804 321.44004 328.44004 334.65605 339.31803 345.53404 349.03404 355.25004 359.91203 366.12803 369.62803 376.62803 383.62803 387.12803 393.34403 400.34403 407.34403 413.56004 418.22203 424.43803 431.43803 437.65403 444.65403 448.15403 452.04603 457.49205 462.93806 469.93806 476.15406">), so there are no coherency issues</tspan><tspan y="132.25" x="23.996064 27.888064 34.88806 41.88806 48.88806 52.780065 59.780065 65.99606 72.99606 76.49606 86.604068 90.49606 94.38806 101.38806 104.88806 108.78006 115.78006 121.99606 125.49606 132.49607 139.49607 146.49607 152.71207 156.60407 162.82007 166.32007 169.82007 183.03607 190.03607 196.25208 203.25208 206.75208 210.64408 217.64408 223.86008 227.36008 237.46808 242.13008 246.02208 249.91408 256.13008 259.63008 265.84608 272.84608 283.73808 290.73808 294.63008 300.84608 304.73808 310.95408 316.4001 319.9001 323.4001 327.29209 334.29209 340.5081 344.0081 354.9001 361.1161 372.0081 379.0081 383.67008 390.67008 394.17008 398.83207 405.04808 412.04808 415.94007 422.94007 429.94007 432.46006 437.90608 441.40608 447.62208 453.83808 460.05409 466.27009 471.7161">involved with the update. When the write completes, the memory region's access</tspan><tspan y="148.25" x="23.996064 28.658064 32.550065 39.550065 46.550065 50.442068 55.888067 59.388067 64.83407 74.94207 78.83407 82.72607 88.94207 95.94207 99.44207 103.33407 110.33407 115.78007 119.672069 125.88807 132.88806 136.78006 142.99607 149.99607 156.21207 163.21207 170.21207 175.65807 179.55007 186.55007 190.05007 193.94207 200.94207 204.44207 208.33406 215.33406 221.55007 225.05007 232.05007 238.26607 248.37407 251.87407 258.87409 265.0901 268.9821 275.9821 282.1981">rights switch instantaneously to the new value.</tspan><tspan y="172.65" x="13.104074 23.996075 33.334077 40.334077 46.550077 53.550077 60.550077 64.44208 71.44208 78.44208 81.94208 88.15808 91.65808 96.32008 102.53609 109.53609 113.428089 120.428089 127.428089 129.94809 135.39409 138.89409 144.34009 148.23209 154.44809 159.11009 163.00209 166.50209 172.7181 179.7181 186.7181 190.2181 196.4341 203.4341 210.4341 213.9341 220.1501 227.1501 234.1501 238.8121 245.0281 250.4741 255.9201 262.1361 267.58213 281.58213 294.79814 299.4601 303.3521 307.2441 313.4601 316.9601 323.17613 326.67613 337.5681 341.4601 348.4601 352.3521 363.2441 370.2441 381.1361 384.6361 391.6361 396.2981 399.7981 403.6901 410.6901 415.35209 421.56809 427.7841 431.2841 441.3921 448.3921 453.05409 460.05409 465.5001 469.0001 472.8921 479.8921 483.3921 487.2841 494.2841">&#x2022;Changing a region's start and end addresses&#x2014;Write a minimum of three words to the</tspan><tspan y="188.65" x="23.996064 28.658064 34.874067 41.874067 45.766069 52.766069 59.766069 63.266069 70.26607 76.48207 81.92807 88.14407 92.806079 96.698078 103.698078 107.59007 114.59007 119.252079 122.752079 127.41408 136.75208 146.86008">region descriptor (RGD</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="188.65" x="163.96807 170.96807 184.18407 191.18407 195.84607 202.84607 209.56607 216.56607 220.06607 227.06607 230.56607 237.56607 244.28607 248.94808 252.44808 255.94808 269.16407 276.16407 280.82606 287.82606 291.32606 298.32606 301.82606 308.04206 315.04206 322.04206 325.54206 332.54206 336.04206 340.70405 346.92005 353.92005 360.13606 364.79804 368.69004 375.69004 381.90605 385.40605 389.29804 396.29804 402.51405 406.01405 411.46006 415.35206 421.56806 426.23005 430.12205 433.62205 439.83805 446.83805 453.83805 457.33805 463.55406 470.55406">_Word{0,1,3}). Word 0 and 1 redefine the start and end</tspan><tspan y="204.65" x="23.996064 30.212063 37.212064 44.212064 48.87406 55.09006 60.53606 65.98206 72.19807 77.644069 81.144069 84.644069 89.30607 95.52207 100.96807 107.96807 114.184078 120.40008 124.292079 128.18408 135.18408 141.40009 145.29209 152.29209 155.79209 159.29209 172.50809 179.50809 184.17009 191.17009 194.67009 201.67009 205.17009 209.83209 216.0481 220.7101 226.9261 233.9261 240.1421 247.1421 251.0341 257.2501 262.6961 266.1961 270.0881 277.0881 283.3041 286.8041 291.4661 297.6821 304.6821 308.5741 315.5741 322.5741 326.0741 333.0741 339.2901 344.7361 350.95213 355.6141 359.5061 366.5061 370.3981 377.3981 382.0601 385.5601 392.5601 398.7761 402.6681 406.5601 413.5601 417.0601 424.0601 427.9521 431.8441 435.3441 438.8441 443.50608 450.50608 454.00608 464.89808 471.89808 477.3441">addresses, respectively. Word 3 re-enables the region descriptor valid bit. In most</tspan><tspan y="220.65" x="23.996064 29.442065 33.334066 37.226068 44.226068 50.442068 54.33407 58.22607 65.226078 72.226078 77.67207 81.17207 84.67207 90.88808 94.780078 98.67207 102.17207 106.834079 113.834079 120.834079 125.49608 128.99608 139.10408 146.10408 150.76609 157.76609 163.21208 166.71208 173.71208 178.37409 181.87409 185.76609 192.76609 198.98209 202.48209 207.14409 213.36009 220.36009 224.25209 231.25209 238.25209 241.75209 248.75209 254.9681 260.4141 266.6301 271.29209 275.18409 282.18409 286.07609 293.07609 297.73808 301.23808 307.45408 312.11607 318.33207 321.83207 326.49406 332.71006 342.81806 347.48005 351.37205 355.26405 359.15605 365.37205 372.37205">situations, all four words of the region descriptor are rewritten.</tspan><tspan y="245.04999" x="13.104074 23.996075 34.104078 40.320077 46.536077 52.752077 58.198076 63.644075 67.53607 74.53607 81.53607 85.03607 88.92807 95.92807 102.14407 105.64407 118.09007 125.87408 135.98207 149.98207 160.09008 163.98207 167.87407 174.87407 181.09008 187.30608 191.19808 197.41408 200.91408 207.13008 210.63008 215.29209 221.50809 228.50809 232.40009 239.40009 246.40009 249.90009 256.9001 263.1161 268.5621 274.7781 279.4401 283.3321 290.3321 294.2241 301.2241 305.88609 309.38609 313.27809 320.27809 323.77809 328.44007 334.65608 340.10209 343.99409 348.65608 352.54808 358.76408 362.65608 366.15608 378.60209 386.38609 396.49409 399.99409 406.21009 412.4261 418.6421 424.8581 430.3041 435.75013 439.25013 443.14213">&#x2022;Accessing the MPU&#x2014;Allocate a region descriptor to restrict MPU access to</tspan><tspan y="261.05" x="23.996064 29.442065 36.442064 43.442064 49.658063 54.32006 61.32006 65.21206 70.65806 77.65806 82.32006 85.82006 96.71206 103.71206 110.71206 116.92806 120.42806 125.090068 129.75206 136.75206 147.64406 151.14406 157.36006 160.86006 166.30606 173.30606 179.52207 185.73807 189.63007 194.29207 198.18407 204.40007 207.90007 218.79207 225.00807 230.45407 234.34607 240.56208 245.22408">supervisor mode from a specific master.</tspan><tspan y="285.44999" x="13.104074 23.996075 34.104078 40.320077 44.21208 50.428079 56.644079 60.53608 64.42808 71.42808 78.42808 81.92808 88.14408 95.14408 98.64408 104.860088 111.07609 117.29209 123.508098 128.9541 134.4001 137.9001 144.1161 148.7781 153.44011 160.44011 165.10211 179.10211 187.65612 194.65612 200.87212 204.37212 210.58812 217.58812 222.25012 226.91213 233.12813 240.12813 244.02013 247.52013 254.52013 261.52015 266.96617 270.46617 276.68217 283.68217 289.89817 293.79017 300.00617 303.50617 307.39817 312.84419 316.34419 320.23619 326.45219 331.11418 342.00617 345.89817 352.89817 359.11418 363.00617 369.22218 376.22218 379.72218 389.83018 393.72218 397.61418 404.61418 408.11418 414.33018 421.33018 424.83018 431.04618 435.70817 440.37016 447.37016">&#x2022;Detecting an access error&#x2014;The current bus cycle is terminated with an error</tspan><tspan y="301.44999" x="23.996094 28.658095 34.874097 40.320096 47.320096 54.320096 61.320096 66.7661 72.9821 76.4821 82.698108 89.698108 96.698108 100.198108 108.752109 118.86011">response and EAR</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="301.44999" x="135.19809 138.69809 144.9141 151.9141 158.9141 162.4141 170.9681 181.0761"> and EDR</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="301.44999" x="197.4141 200.9141 207.1301 213.3461 220.3461 224.2381 231.2381 235.9001 242.1161 245.6161 249.5081 256.50813 261.1701 268.1701 272.8321 283.7241 289.9401 293.8321 297.7241 304.7241 311.7241 315.2241 322.2241 329.2241 332.7241 336.6161 343.6161 349.8321 353.3321 357.99409 364.21009 371.21009 375.10209 378.99409 382.88609 389.88609 396.88609 400.38609 405.04808 411.26408 415.92607 422.14207 426.80406 433.02006 440.02006 446.23606 452.45207 455.95207 459.45207 468.00605 475.00605"> capture information on the faulting reference. The</tspan><tspan y="317.44999" x="23.996125 30.212124 34.874124 39.53612 46.53612 51.19812 55.86012 59.75212 65.968128 70.63013 81.522129 85.41412 92.41412 98.63013 102.522129 108.73813 115.73813 119.23813 126.23813 133.23813 138.68413 142.18413 148.40013 155.40013 161.61614 165.50814 171.72414 175.22414 179.11614 186.11614 193.11614 197.00814 203.22414 209.44014 213.33214 217.22414 224.22414 227.72414 231.61614 238.61614 242.50814 246.40013 250.29213 256.50813 260.40013 266.61613 272.06214 275.56214 281.77815 288.77815 292.27815 298.49415 303.15614 307.8181 314.8181 319.4801 322.9801 327.6421 333.8581 339.3041 346.3041 353.3041 360.3041 365.75013 371.96614 375.46614 379.35813 386.35813 389.85813 393.75013 400.75013 406.96614 410.46614 417.46614 422.1281 426.0201 433.0201 436.9121 443.9121 450.1281 454.0201 457.9121 464.9121 471.9121 475.4121 482.4121 489.4121">error-terminated bus cycle typically initiates an error response in the originating bus</tspan><tspan y="333.44999" x="23.996125 34.888128 41.104127 46.550127 50.442129 56.658128 61.320127 64.82013 68.32013 76.10413 83.10413 87.766139 91.266139 97.48214 104.48214 110.69814 121.59014 128.59015 132.48215 138.69815 142.19815 145.69815 151.91416 155.41416 162.41416 167.07616 174.07616 180.29216 186.50817 191.95417 197.40016 204.40016 209.06217 212.56217 218.77817 225.77817 230.44017 236.65618 240.15618 251.04817 257.26417 264.26417 267.76417 272.42616 278.64216 284.08818 291.08818 298.08818 305.08818 312.08818 315.58818 325.69618 329.58818 333.48017 340.48017 343.98017 350.19618 353.69618 360.69618 367.69618 373.14219 376.64219 382.8582 387.52018 392.18217 399.18217 403.84416 407.34416 413.56016 420.56016 426.77616 432.99217 439.99217 443.88417 447.77616 454.77616 461.77616 465.27616 468.77616 478.88417 485.88417 489.77616 493.66816">master. For example, a processor core may respond with a bus error exception, while</tspan><tspan y="349.44999" x="23.996125 30.212124 33.712125 40.712125 46.928125 50.820127 57.036127 60.536127 71.42812 78.42812 85.42812 91.64413 102.536128 108.75213 115.75213 119.64413 123.14413 130.14414 137.14414 142.59014 146.09014 156.98213 163.19814 168.64414 172.53614 178.75214 183.41414 186.91414 197.80614 204.02214 211.02214 214.52214 219.18415 225.40015 230.84615 237.84615 244.84615 251.84615 258.84614 262.34614 272.45414 276.34614 280.23814 287.23814 290.73814 296.95414 303.95414 307.45414 313.67015 318.33213 322.9941 329.9941 334.6561 338.1561 342.0481 349.0481 352.9401 359.1561 363.81809 368.48008 375.48008 382.48008 386.37208 389.87208 393.37208 401.92607 408.92607 415.14207 418.64207 425.64207 430.30406 437.30406 443.52006 449.73606 455.18208 460.62809 467.62809 472.29008 475.79008 482.00608 488.22209">a data movement bus master may respond with an error interrupt. The processor can</tspan><tspan y="365.44999" x="23.996184 28.658185 34.874185 38.766187 43.428186 47.320188 53.536188 60.536188 66.75219 70.25219 74.14419 81.14419 87.36019 90.86019 97.076198 103.2922 110.2922 114.1842 121.1842 125.8462 132.0622 139.0622 142.5622 148.7782 153.4402 158.1022 165.1022 169.7642 173.2642 179.48021 186.48021 193.48021 198.14221 204.35822 209.80422 215.25022 218.75022 224.96622 231.96622 238.96622 242.46622 249.46622 255.68222 259.57423 265.79023 269.68223 273.57423 277.07423 280.96623 287.96623 292.6282 299.6282 304.2902 315.1822 321.3982 325.2902 329.1822 336.1822 343.1822 346.6822 352.1282 356.0202 366.9122 373.9122 377.8042 384.8042 388.3042 395.3042 402.3042 405.8042 410.4662 416.6822 422.8982 429.8982 433.7902 440.7902">retrieve the captured error address and detail information simply by reading</tspan><tspan y="381.44999" x="23.996214 32.550214 39.270215 49.378217 52.878217 62.986219 69.706218">E{A,D}R</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="381.44999" x="86.04421 89.54421 93.04421 102.38222 110.93622 118.72022 128.05823 132.72023 140.50423 148.28823 156.84223 166.18022 175.51822 180.18022 183.68022 189.12622 193.01822 200.01822 207.01822 213.23423 217.12622 222.57222 226.07222 236.18022 243.18022 247.07222 253.28823 260.2882 263.7882 270.0042 274.6662 279.3282 286.3282 290.99018 294.49018 299.15217 305.36817 312.36817 316.26017 321.70619 325.59819 331.81419 336.47618 341.92219 345.42219 351.63819 358.63819 365.63819 369.53019 375.7462 379.63819 386.63819 390.13819 396.3542 402.5702 409.5702 413.4622 420.4622 425.12419 431.34019 438.34019 441.84019 446.50218 452.71818 459.71818 463.61018 467.50218 471.00218 478.00218 484.21818 488.11018 494.32618">. CESR[SPERR] signals which error registers contain captured fault data.</tspan><tspan y="405.84999" x="13.104271 23.996273 34.104276 41.104276 47.320276 51.982275 55.874277 62.090276 69.09027 76.09027 79.98227 86.98227 93.98227 97.48227 102.14427 108.360279 115.360279 119.25227 126.25227 133.25228 136.75228 143.75228 149.96828 155.41428 161.63028 166.29228 170.18428 177.18428 181.07628 188.07628 192.73828 198.18428 212.18428 222.29228 229.29228 236.29228 240.18428 247.18428 251.07628 258.0763 265.0763 268.5763 275.5763 282.5763 288.7923 293.45429 297.34629 303.5623 310.5623 317.5623 321.45429 328.45429 335.45429 338.95429 343.61628 349.83229 356.83229 360.72428 367.72428 374.72428 380.1703 383.6703 390.6703 395.33229 399.22428 405.44029 412.44029 415.94029 420.60227 426.81828 433.81828 440.81828 447.03428 453.25028 458.6963 462.1963 466.0883 473.0883">&#x2022;Overlapping region descriptors&#x2014;Applying overlapping regions often reduces the</tspan><tspan y="421.84999" x="23.99632 30.99632 37.996324 48.888326 55.888326 62.104326 66.76633 70.26633 77.26633 81.92833 85.42833 92.42833 98.64433 104.09033 110.306339 114.96834 118.86034 125.86034 129.75234 136.75234 141.41434 146.86034 150.36034 155.02234 161.23834 168.23834 175.23834 179.13034 183.79235 190.00835 197.00835 200.50835 205.17035 212.17035 216.83235 220.33235 226.54836 230.04836 237.04836 240.94036 247.94036 254.15636 261.15638 264.65638 270.1024 276.3184 280.2104 283.7104 290.7104 295.37239 298.87239 305.08839 311.30439 317.5204 323.7364 329.1824 334.62843 338.12843 344.34443 351.34443 358.34443 362.23643 366.8984 373.8984 377.7904 383.23643 386.73643 390.23643 394.8984 401.8984 405.3984 409.2904 416.2904 422.5064 426.0064 433.0064 440.0064 446.2224 450.8844 454.7764 460.9924 467.9924 474.9924 478.8844 485.8844">number of descriptors required for a given set of access controls. In the overlapping</tspan><tspan y="437.84999" x="23.996352 34.88835 41.10435 51.996355 58.996355 63.65835 70.658359 74.158359 79.604358 86.604358 92.82036 99.03636 105.252368 108.752368 112.252368 116.14436 123.14436 129.36037 132.86037 139.86037 144.52237 151.52237 155.41437 161.63037 167.84638 171.73838 175.63037 182.63037 189.63037 193.13037 197.79238 201.68437 208.68437 215.68437 219.57637 225.02237 228.52237 235.52237 240.18437 243.68437 247.57637 254.57637 260.79237 264.29237 270.50837 277.50837 282.17036 286.83235 293.04835 298.49436 305.49436 312.49436 319.49436 326.49436 330.38636 337.38636 344.38636 347.88636 352.54835 358.76435 365.76435 369.65635 376.65635 383.65635 387.15635 394.15635 400.37236 405.81837 412.03437 416.69636 420.58836 427.58836 431.48036 438.48036 443.14234 448.58836 452.08836 458.30436 462.96635">memory space, the protection rights of the corresponding region descriptors are</tspan><tspan y="453.84999" x="23.996382 27.888382 34.888383 41.888383 45.780385 51.996385 58.212385 62.104387 65.99638 72.99638 76.49638 81.94238 88.94238 99.83438 110.72638 116.94238 123.94238 127.44238 131.33438 138.33438 145.33438 151.55039 155.44239 162.44239 168.65839 173.32039 176.82039 181.48239 185.37439 192.37439 198.5904 202.0904 209.0904 216.0904 223.0904 226.98239 233.1984 239.4144 246.4144 249.9144 260.0224 269.3604 272.8604 279.8604 286.8604 293.07643 297.7384 303.9544 307.8464 314.8464 319.5084 324.17039">logically summed together (the boolean OR operator).</tspan><tspan y="478.24998" x="23.996413 32.55041 39.55041 45.76641 49.26641 53.92841 60.92841 64.82041 68.71241 75.71241 85.82041 89.71241 96.71241 103.71241 107.21241 114.21241 121.21241 127.42841 131.32042 135.98242 142.19843 149.19843 153.86043 160.07643 163.57643 169.02243 176.02243 181.46843 185.36043 191.57643 202.46843 205.96843 212.18444 219.18444 225.40044 236.29244 243.29244 247.18444 253.40044 256.90046 263.11647 270.11647 277.11647 281.00846 287.22447 291.11647 298.11647 303.56248 307.06248 311.72447 318.72447 325.72447 330.38645 333.88645 340.88645 347.88645 353.33247 356.83247 367.72447 373.94047 379.38648 383.27848 389.49449 394.15647 399.60249">The following dual-core system example contains four bus masters:</tspan><tspan y="502.64997" x="37.100404 48.006406 56.560407 63.560407 69.776409 73.276409 77.1684 87.276409 94.276409 97.776409 104.776409 109.43841 116.43841 122.65441 128.8704 134.3164 139.7624 146.7624 151.42441 156.8704 160.7624 164.2624 173.6004 181.3844 188.3844 191.8844 195.3844 204.7224 212.5064">&#x2022;The two processors: CP0, CP1</tspan><tspan y="518.64999" x="37.100404 48.006406 56.560407 66.6684 73.6684 77.1684 87.276409 99.722408 109.83041 113.33041 119.54641 126.54641 133.54642 137.43842 144.43842 150.65442 156.10042 159.99242 163.49242 173.60042 186.04642 196.15442 203.15442 206.65442 210.15442 216.37042 219.87042 223.76242 228.42443 234.64043 241.64043 245.53243 249.42443 253.31642 260.3164 267.3164 273.5324 277.4244 280.9244 287.9244 294.1404 298.0324 304.2484 307.7484 318.6404 325.6404 332.6404 338.8564 349.7484 355.96443 362.96443 366.8564 370.3564 376.57243 383.57243 390.57243 394.46443 401.46443 407.68043 411.18043 415.07243 419.7344 425.9504 432.9504 438.39643 443.0584 449.2744 453.9364 458.5984 462.4904 469.4904 476.4904 479.9904 486.9904 493.2064 497.0984">&#x2022;Two DMA engines: DMA1, a traditional data movement engine transferring data</tspan><tspan y="534.6499" x="48.006425 55.006425 61.222425 65.114429 75.22243 81.43843 87.654438 94.654438 98.154438 107.49243 117.60043 130.04644 133.54644 139.76244 146.76244 153.76244 157.26244 164.26244 170.47844 175.14044 179.03244 186.03244 193.03244 199.24845 203.91045 210.12645 214.01845 219.46445 222.96445 229.18045 236.18045 243.18045 246.68045 256.78846 269.23448 279.34248 286.34248 289.84248 293.34248 299.55848 303.05848 308.5045 314.7205 320.9365 327.9365 334.9365 341.9365 345.4365 351.6525 358.6525 365.6525 369.5445 376.5445 382.7605 386.2605 390.1525 394.81449 401.0305 408.0305 413.4765 418.1385 424.3545 429.01649 433.67848 437.57048 444.57048 451.57048 455.07048 462.07048 468.28648 472.17848 478.39448 481.89448 485.78648 492.78648">between RAM and peripherals and DMA2, a second engine transferring data to/</tspan><tspan y="550.6499" x="48.006456 52.668455 57.330453 64.33045 75.22245 78.72245 82.61445 89.61445 95.83045 99.33045 108.66846 118.77646 131.22246 134.72246 141.72246 148.72246 152.61446">from the RAM only</tspan><tspan y="575.0499" x="23.996464 33.334466 40.334466 47.334466 52.780466 56.672468 63.672468 69.888469 74.55047 78.05047 81.94247 88.94247 95.15847 98.65847 103.32047 110.32047 114.21247 118.10447 125.10447 135.21247 139.10446 146.10446 153.10446 156.60446 161.26647 167.48247 174.48247 178.37447 185.37447 192.37447 195.87447 202.87447 209.09047 214.53647 220.75247 225.41448 229.30648 236.30648 240.19847 247.19847 251.86048 255.36048 261.57649 267.0225 272.4685 276.3605 283.3605 290.3605 301.2525 307.4685 314.4685 318.3605 323.80653">Consider the following region descriptor assignments:</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 734.93869)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="130.007 137.227 142.787 148.347 151.127 157.797 163.907 170.017 173.347 179.457 185.017 193.907 196.687 199.467 205.027 207.80699 215.027 220.58699 223.91699 229.47699 233.36699 238.92699 245.03699 250.59699 256.15699 258.93699 267.26698 272.82698 278.93696 285.04695 290.60694 293.38694 296.16694 298.94694 306.16694 311.72694 317.28694 320.06694 322.84693 328.40693 331.18693 336.74693 342.8569 348.9669 351.7469 357.3069 362.86689 368.42689">K60 Sub-Family Reference Manual, Rev. 2 Jun 2012</tspan></text>
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