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birdcage/docs/K60-refman-vectors/K60-reference-manual_page_215.svg
Ryan Malloy 5252d1d73c Add hardware reference docs (A3981, K60, RYS352A) 
Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint,
3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep.

NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference
manual. Cortex-M4 96MHz MCU running the G2 firmware.

Reyax RYS352A GPS module: datasheet and PAIR command guide.
GPS receiver on the G2 board (used for auto-location/satellite lookup).

All extracted as markdown + page images + vector SVGs for LLM context.
Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.
2026-02-14 18:36:42 -07:00

125 lines
37 KiB (Stored with Git LFS)
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 87.8)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x="0 9.452001 14.178001">7.5</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 91.80322 87.8)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x="0 11.339001 21.726002 34.952005 44.404005 51.017004 55.743005 70.856 81.243007 91.630008 101.08201 110.53401 115.26001 124.71201 135.09902 145.48601 151.147 161.534 171.92099 185.14699 195.53398 200.25998 209.71198 219.16397 229.55097 239.93796 249.38996 259.77696 269.22895 273.95497 284.34196">Power modes shutdown sequencing</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 54.000005)" font-size="14" font-family="TimesLTStd"><tspan y="71.05" x=".00101 13.2170109 20.21701 26.43301 33.43301 36.93301 43.14901 50.14901 54.04101 60.25701 64.919017 68.81101 75.81101 82.81101 86.31101 91.75701 95.64901 102.64901 109.64901 113.14901 120.14901 124.81101 128.311 135.311 139.203 146.203 152.419 157.08101 160.58101 164.473 171.473 181.58101 186.24301 193.24301 200.24301 210.35102 216.56702 221.22902 224.72902 235.62102 242.62102 249.62102 255.83702 261.28303 264.78303 268.28303 272.17503 279.17503 285.39103 288.89103 295.10704 298.99903 305.99903 312.21504 319.21504 324.66105 328.16105 334.37705 339.03904 345.25505 348.75505 354.20106 361.20106 368.20106 372.09306 375.59306 382.59306 387.25505 391.91703 395.41703 399.30903 406.30903 409.80903 416.02503 423.02503 426.52503 433.52503 438.187 445.187 451.403 456.065 459.957">When entering stop or other low-power modes, the clocks are shut off in an orderly</tspan><tspan y="87.049999" x=".00104 5.4470407 11.663041 18.66304 25.66304 31.87904 38.87904 45.09504 51.31104 54.81104 58.70304 65.70304 69.20304 74.64904 80.86504 85.52705 91.74305 95.63505 102.63505 106.13505 113.13505 117.02705 123.24305 129.45905 135.67505 139.17505 143.06705 150.06705 156.28305 159.78305 165.99906 172.99906 176.89105 183.89105 187.39105 191.28305 198.28305 201.78305 205.67505 212.67505 218.89105 222.39105 226.28305 232.49906 237.16106 244.16106 250.37706 254.26906 260.48506 267.48506 270.98506 274.87705 281.87705 291.98506 296.64704 303.64704 310.64704 320.75505 326.97105 331.63304 335.13304 340.57905 344.47105 350.68705 354.57905 360.79505 364.29505 367.79505 377.90306 381.79505 385.68705 389.18705 393.07905 400.07905 410.18705 414.84904 421.84904 428.84904 438.95704 445.17304 449.83503 453.33503 459.55104 466.55104 470.44303 475.105">sequence to safely place the chip in the targeted low-power state. All low-power entry</tspan><tspan y="103.049999" x=".00104 5.4470407 11.663041 18.66304 25.66304 31.87904 38.87904 45.09504 51.31104 56.75704 60.25704 66.47304 71.13504 77.35104 80.85104 84.74304 91.74304 95.63504 99.52704 103.41904 109.63504 113.52704 119.74304 126.74304 130.24304 137.24304 144.24304 147.74304 151.63504 158.63504 164.85105 168.35105 174.56705 181.56705 186.22905 192.44506 195.94506 202.16106 209.16106 215.37706 221.59307 228.59307 232.48506 236.37706 243.37706 250.37706 253.87706 260.09306 267.09306 270.59306 283.80906 291.59306 296.25505 299.75505 303.64704 310.64704 316.09306 319.98506 324.64704 331.64704 337.86305 341.75505 345.64704 352.64704 359.64704 363.14704 366.64704 375.20103 382.20103 388.41703 391.91703 402.02503 411.36305 423.80906 427.30906 433.52507 440.52507 445.18705 451.40306 453.92304">sequences are initiated by the core executing an WFI instruction. The ARM core's</tspan><tspan y="119.049999" x=".00104 7.00104 14.0010399 17.89304 24.89304 31.89304 35.78504 41.23104 44.73104 48.23104 56.01504 64.56904 73.12304 81.67704 89.461048 99.569049 108.12305 116.67705 124.46105 127.96105 134.17705 141.17705 148.17705 151.67705 159.46105 168.01505 176.56905 185.12305 192.90705 197.56905 207.67705 217.78505 221.28505 224.78505 228.67705 233.33905 237.23105 244.23105 251.23105 257.44706 262.10905 265.60905 271.82505 278.82505 282.71705 287.37904 294.37904 297.87904 301.77104 308.77104 312.27104 316.16304 323.16304 329.37904 332.87904 339.87904 346.09504 350.75703 354.64903 361.64903 368.64903 374.09504 377.59504 381.48704 388.48704 398.59504 403.25703 410.25703 417.25703 427.36503 433.58103 438.243 441.743 452.635 459.635 466.635 472.851 478.29704">outputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes:</tspan><tspan y="143.45" x="13.10503 23.997033 31.781033 38.781034 44.22703 48.119035 54.335035 65.227039 68.727039 72.61903 78.83504 85.83504 92.05104 95.94304 99.44304 109.55104 115.767047 119.65904 123.55104 127.05104 133.26705 140.26705 147.26705 150.76705 160.87505 169.42905 177.21305 190.42905 193.92905 204.82105 211.82105 218.82105 225.03705 230.48305 233.98305 240.19905 247.19905 254.19905 260.41505 264.30705 270.52305 274.02305 277.91505 284.91505 288.80705 292.30705 300.09104 308.64503 317.199 325.753 333.537 338.19898 348.30699 358.41499 361.91499 372.80699">&#x2022;System level wait and VLPW modes equate to: SLEEPING &#x0026; </tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 54.000005)" font-size="14" font-family="TimesLTStd"><tspan y="143.45" x="376.30705 384.09104 392.64503 401.199 409.753 417.537 427.645 436.19898 444.75297">SLEEPDEEP</tspan><tspan y="159.45" x="13.105072 23.997075 34.105077 37.997079 41.88908 45.38908 52.38908 56.281084 63.281084 69.497089 74.15909 77.65909 81.55109 88.55109 98.65909 102.15909 109.15909 116.15909 126.26709 132.4831 137.1451 140.6451 151.5371 158.5371 165.5371 171.7531 177.1991 180.6991 186.9151 193.9151 200.9151 207.1311 211.0231 217.2391 220.7391 224.6311 231.6311 235.5231 239.0231 246.8071 255.3611 263.9151 272.4691 280.25309 284.91508 295.02308 305.13108 308.63108 319.52308 323.02308 330.80708 339.36106 347.91505 356.46903 364.25303 374.36103 382.915 391.469">&#x2022;All other low power modes equate to: SLEEPING &#x0026; SLEEPDEEP</tspan><tspan y="185.45" x=".0010919571 13.2170929 20.217093 26.433094 33.433095 36.933095 43.149095 50.149095 54.041097 60.257097 64.9191 68.8111 75.8111 82.8111 86.3111 90.203098 97.203098 103.4191 106.9191 113.9191 120.9191 127.9191 132.5811 142.6891 148.9051 152.7971 156.6891 160.1891 171.0811 178.0811 185.0811 191.2971 196.7431 200.2431 203.7431 207.6351 214.6351 220.8511 224.3511 230.56711 237.56711 241.4591 248.4591 251.9591 258.9591 265.1751 269.8371 274.49909 281.49909 286.16108 297.05308 302.49909 305.99909 309.89109 316.89109 323.1071 326.6071 331.26908 338.26908 342.16108 346.05308 353.05308 363.16108 367.05308 374.05308 381.05308 384.55308 389.99909 396.2151 403.2151 410.2151 416.4311 423.4311 429.6471 435.8631">When entering the non-wait modes, the chip performs the following sequence:</tspan><tspan y="209.84999" x="13.105112 23.997113 31.781113 38.781114 45.781114 49.673116 55.119115 58.619115 65.61911 70.28111 74.943119 78.443119 87.78111 94.78111 99.443119 105.65912 109.15912 118.497119 122.389118 129.38912 135.60512 142.60512 146.10512 152.32112 159.32112 166.32112 169.82112 177.60512 184.60512 190.05112 193.94312 200.15912 211.05112 214.55112 223.88912 227.78112 234.78112 240.99712 247.99712 251.49712 255.38912 262.3891 265.8891 269.7811 276.7811 282.9971 286.4971 296.6051 305.9431 318.38914 321.88914 331.22715 338.22715 342.88914 346.78114 352.99714 359.99714 364.65913 377.10514 384.10514 387.60514 393.82115 400.82115 405.48313 411.69914 415.19914 419.09114 429.98313 440.87513 447.09114 454.09114 457.98313 464.19914 468.09114 474.30714 478.19914 485.19914">&#x2022;Shuts off Core Clock and System Clock to the ARM Cortex-M4 core immediately.</tspan><tspan y="225.84999" x="13.1050829 23.997084 31.781085 38.781084 42.673086 46.565088 52.011087 55.511087 60.957086 64.84908 71.84908 78.84908 82.34908 88.56509 94.78109 101.78109 108.78109 115.78109 125.88909 129.7811 135.9971 142.9971 149.9971 156.2131 159.7131 163.6051 170.6051 177.6051 181.4971 187.7131 193.92911 197.8211 201.7131 208.7131 215.7131 221.1591 224.6591 229.3211 233.98311 240.98311 251.8751 255.3751 259.26713 266.26713 272.48313 275.98313 282.98313 289.98313 296.98313 301.6451 307.8611 314.8611 319.5231 325.7391 329.2391 335.4551 340.1171 347.1171 352.5631 358.00914 365.00914 371.22514 375.88713 379.38713 390.2791 396.49513 401.94114 405.83314 412.04914 416.71113 422.15715 425.65715 430.31913 440.42713 452.87315 462.98115">&#x2022;Polls stop acknowledge indications from the non-core crossbar masters (DMA,</tspan><tspan y="241.84999" x="23.997094 32.551095 36.443098 43.443098 49.659097 54.321096 61.321096 67.537097 71.42909 76.091098 79.591098 83.091098 88.537097 95.537097 102.537097 109.537097 116.537097 121.1991 125.091098 128.9831 135.9831 142.9831 146.4831 153.4831 159.6991 164.3611 168.2531 175.2531 182.2531 188.4691 193.1311 199.3471 203.2391 208.6851 212.1851 216.8471 224.6311 232.4151 237.0771 240.5771 244.0771 251.8611 256.5231 265.0771 268.5771 272.0771 281.4151 291.5231 301.6311 306.2931 309.7931 316.0091 323.0091 330.0091 333.5091 337.4011 344.4011 350.6171 354.1171 361.9011 365.7931 372.0091 377.4551 384.4551 387.9551 397.29313 404.29313 411.29313 415.18513 419.8471 426.8471 430.7391 434.6311 440.8471 445.5091 449.0091 453.67109 460.67109">Ethernet), supporting peripherals (SPI, PIT, RNG) and the Flash Controller for</tspan><tspan y="257.84999" x="23.997094 27.889094 34.88909 41.88909 45.781095 51.997095 58.213094 62.105096 65.99709 72.99709 79.99709 85.44309 88.94309 92.83509 99.83509 106.051097 109.94309 113.44309 121.2271 128.2271 133.6731 137.5651 143.7811 154.6731 158.1731 167.5111 171.40309 178.40309 184.6191 191.6191 197.0651 200.5651 204.0651 213.40309 220.40309 225.84909 229.34909 238.68709 242.57909 249.57909 255.79509 262.7951 266.2951 272.5111 279.5111 286.5111 290.4031 297.4031 302.0651 305.5651 313.3491 317.2411 323.4571 328.9031 335.9031 339.4031 348.74113 352.63313 359.63313 365.84913 372.84913 376.34913 383.34913 389.56513 395.78114 402.78114 406.28114 410.17314 417.17314 420.67314 427.67314 433.88914 437.38914 441.28114 447.49714 452.15913 456.05113 459.55113 465.76713 472.76713 478.98313 485.98313 489.87513 496.09114">indications that System Clocks, Bus Clock and/or Flash Clock need to be left enabled</tspan><tspan y="273.85" x="23.997094 27.889094 34.88909 38.38909 44.60509 51.60509 62.497095 69.49709 73.38909 79.605098 83.49709 89.7131 93.2131 99.4291 102.9291 109.9291 114.5911 120.807109 127.807109 131.69911 138.69911 145.69911 151.14511 155.03711 162.03711 165.53711 169.42911 176.42911 180.3211 184.2131 188.1051 194.3211 198.2131 204.42911 211.42911 214.92911 221.92911 228.92911 235.14511 239.80712 246.02312 249.91512 253.80712 260.80714 267.80714 271.30714 274.80714 281.02314 285.68513 290.3471 296.5631 302.7791 306.6711 310.5631 317.5631 323.7791 327.6711 334.6711 338.1711 343.61714 347.50914 353.72514 357.61714 361.50914 365.40113 372.40113 379.40113 382.90113 389.11714 396.11714 400.00914 404.6711 411.6711 415.1711 419.0631 426.0631 429.5631 433.4551 440.4551 446.6711 450.1711 454.0631 460.2791 464.9411 471.9411 478.1571 482.0491 488.2651">to complete a previously initiated operation, effectively stalling entry to the targeted</tspan><tspan y="289.85" x="23.997094 27.889094 34.88909 44.997095 48.497095 55.497095 62.497095 72.605098 78.8211 83.4831 86.9831 97.8751 104.8751 111.8751 118.0911 121.5911 125.0911 138.3071 145.3071 151.5231 158.5231 162.0231 168.2391 172.1311 176.0231 179.5231 185.7391 191.95511 198.95511 205.95511 212.95511 223.06311 226.95511 233.17111 240.17111 247.17111 253.38712 258.83314 262.33314 268.54914 273.21113 279.42713 282.92713 289.92713 296.14314 300.03514 306.25114 312.46714 316.35914 322.57514 329.57514 333.07514 336.57514 344.35914 351.35914 356.80516 360.69715 366.91316 377.80516 381.30516 390.64317 394.53517 401.53517 407.75117 414.75117 418.25117 421.75117 431.08918 438.08918 443.5352 447.0352 456.3732 460.2652 467.2652 473.4812">low power mode. When all acknowledges are detected, System Clock, Bus Clock</tspan><tspan y="305.85" x="23.997124 30.213124 37.213125 44.213125 47.713125 55.497125 59.389127 65.605129 71.051128 78.051128 81.551128 90.88913 94.78113 101.78113 107.99713 114.99713 118.49713 124.713138 129.37514 135.59114 139.09114 142.98314 149.98314 154.64514 161.64514 167.86115 174.86115 178.36115 185.36115 190.02315 194.68515 198.18515 204.40116 208.29315 211.79315 215.68515 222.68515 228.90116 232.40116 237.84716 244.06316 254.95516 261.17115 264.67115 268.56315 272.45515 283.34715 289.56315">and Flash Clock are turned off at the same time.</tspan><tspan y="321.85" x="13.105134 23.997136 36.44314 45.78114 55.88914 59.38914 65.60514 72.60514 79.60514 83.10514 95.55114 102.55114 109.55114 115.76714 119.26714 128.60515 135.60515 142.60515 146.49715 151.15915 158.15915 162.05115 165.94315 172.15915 176.82115 180.32115 185.76715 192.76715 199.76715 203.65915 207.15915 214.15915 218.82115 223.48316 226.98316 233.19916 237.09116 244.09116 250.30716 257.30717 260.80717 266.25318 273.25318 280.25318 284.91517 291.13117 297.34718 302.79319 306.29319 312.5092 319.5092 326.5092 330.40119 337.40119 342.06318 345.56318 349.45518 356.45518 362.67118 366.17118 370.06318 377.06318 380.95518 387.17118 391.83317 398.83317 405.04917 408.94117 412.44117 417.88719 424.88719 431.88719 438.88719 442.77919 446.67118 452.88719 458.3332 461.8332 468.8332 473.49519 477.38719 484.38719 490.60319">&#x2022;MCG and Mode Controller shut off clock sources and/or the internal supplies driven</tspan><tspan y="337.85" x="23.997155 28.659155 33.321157 40.321157 51.213159 54.713159 58.60516 65.60516 71.82117 75.32117 82.32117 89.32117 93.98317 100.19917 107.19917 111.09117 118.09117 121.59117 126.253177 132.46918 139.46918 146.46918 150.36118 156.57718 160.46918 167.46918 172.13118 175.63118 181.84719 187.29319 190.79319 197.79319 204.00919 208.67119 212.56319 219.56319 225.77919 232.77919 236.27919 240.9412 247.9412 252.6032 256.1032 259.9952 266.9952 273.2112 276.7112 280.6032 286.8192 291.4812 298.4812 304.6972 308.5892 314.8052 321.8052 325.3052 329.1972 336.1972 346.3052 349.8052 356.8052 363.8052 373.9132 380.1292 384.7912 388.2912 399.1832 406.1832 413.1832 419.3992">from the on-chip regulator as defined for the targeted low power mode.</tspan><tspan y="363.85" x=".0011749268 4.663175 11.663176 15.163176 25.271176 31.487175 35.379179 39.27118 42.77118 53.66318 60.66318 67.66318 73.87918 79.32518 82.82518 86.32518 97.21718 104.21718 109.66318 113.555179 117.055179 124.055179 128.71718 132.21718 136.10918 143.10918 149.32518 152.82518 158.27118 165.27118 170.71718 174.60918 180.82518 191.71718 195.21718 201.43318 205.32518 212.32518 218.54119 225.54119 230.98719 234.48719 240.70319 245.36519 251.58119 255.08119 262.08119 269.08119 272.97319 276.47319 282.68919 287.35118 292.01316 298.22917 304.44517 308.33717 314.55317 321.55317 325.05317 332.05317 339.05317 342.55317 346.44517 353.44517 359.66117 363.16117 367.05317 374.05317 384.16117 387.66117 394.66117 401.66117 411.76918 417.98518 422.64717 426.14717 437.03916 444.03916 451.03916 457.25517 460.75517 466.97117 473.97117 477.86317 482.52516 489.52516">In wait modes, most of the system clocks are not affected by the low power mode entry.</tspan><tspan y="379.85" x=".0012049268 8.555204 15.555204 21.771206 25.271206 34.609209 41.609209 46.271207 52.487207 55.987207 65.32521 69.21721 76.21721 82.43321 89.43321 92.93321 96.82521 103.82521 107.32521 111.21721 118.21721 124.43321 127.93321 138.04122 147.37921 159.82521 163.32521 172.66321 179.66321 184.32521 188.21721 194.43321 201.43321 206.09522 218.54122 225.54122 229.04122 235.25722 242.25722 246.91922 253.13523 256.63523 260.52723 265.97325 269.47325 274.91926 281.91926 288.91926 292.81126 296.31126 303.31126 307.97325 312.63523 316.13523 319.63523 327.41923 334.41923 345.31123 351.52723 355.02723 365.91923 372.91923 379.91923 386.91923 390.81123 397.02723 402.47325 405.97325 411.41926 418.41926 425.41926 432.41926 439.41926 444.08125 447.97325 451.47325 456.91926 460.81126 467.81126 474.81126 479.47325 483.36524 490.36524">The Core Clock to the ARM Cortex-M4 core is shut off. Some modules support stop-in-</tspan><tspan y="395.85" x=".0012049268 10.109205 16.325207 20.217207 24.109208 27.609208 32.271207 39.271207 46.271207 52.487207 56.379209 60.27121 67.27121 74.27121 80.48721 84.37921 88.27121 92.16321 99.16321 102.66321 108.87921 115.87921 122.87921 126.37921 133.37921 139.59522 146.59522 152.81122 156.31122 160.20322 167.20322 173.41922 177.31122 181.97322 185.47322 191.68923 195.58123 202.58123 208.79723 215.79723 221.24323 224.74323 231.74323 235.63523 241.08123 247.29723 254.29723 258.18925 264.40525 271.40525 274.90525 281.90525 288.90525 295.90525 302.12126 306.78324 310.28324 314.17524 321.17524 327.39125 332.83726 339.05326 342.55326 348.76927 355.76927 362.76927 367.43125 371.32325 378.32325 385.32325 389.98524 396.20124 400.09324 403.98524 410.98524 417.98524 423.43125">wait functionality and have their clocks disabled under these configurations.</tspan><tspan y="420.25" x=".0012049268 8.555204 15.555204 21.771206 25.271206 32.271207 38.487207 45.487207 52.487207 59.487207 66.487209 72.70321 77.36521 80.86521 91.75721 98.75721 105.75721 112.75721 116.64921 122.86521 128.31122 131.81122 137.25722 144.25722 151.25722 158.25722 165.25722 169.91922 173.81122 177.31122 183.52722 187.02722 190.91922 195.58123 201.79723 208.79723 214.24323 218.13523 222.02722 225.91922 232.91922 239.91922 243.41922 248.08123 252.74323 259.74324 270.63523 274.13523 279.58125 283.47325 290.47325 297.47325 300.97325 304.47325 314.58125 320.79725 324.68925 328.58125 332.08125 335.58125 345.68925 354.24324 362.02723 369.81123 373.31123 376.81123 383.02723 390.02723 397.02723 400.52723 410.63523 419.1892 426.9732 440.1892 443.6892 450.6892 456.9052 463.12123 470.12123 473.62123 477.5132 484.5132 488.0132">The debugger modules support a transition from stop, wait, VLPS, and VLPW back to a</tspan><tspan y="436.25" x=".0012049268 7.001205 13.217205 17.109206 21.001206 27.217206 34.217206 37.717206 43.163206 47.055208 53.271207 57.163209 63.379209 66.87921 76.98721 83.98721 90.20322 97.20322 100.70322 104.595218 111.595218 117.81122 121.31122 128.31122 134.52722 141.52722 148.52722 155.52722 162.52722 168.74323 173.40523 176.90523 180.79723 186.24323 189.74323 195.95923 202.95923 209.17523 216.17523 220.06723 226.28324 233.28324 236.78324 240.28324 248.83724 255.83724 259.72926 265.17527 268.67527 272.56727 277.22926 283.44526 290.44526 295.89128 299.78327 303.67527 307.56727 314.56727 321.56727 325.06727 328.95927 334.40528 337.90528 341.79728 348.79728 352.68928 356.58128 360.47328 366.68928 370.58128 376.79728 383.79728 387.29728 394.29728 401.29728 404.79728 410.2433 416.4593 420.3513 424.2433 428.13529 435.13529 442.13529 445.63529 449.52729 456.52729 462.7433 466.2433 476.3513 482.5673 489.5673 496.5673">halted state when the debugger is enabled. This transition is initiated by setting the Debug</tspan><tspan y="452.25" x=".0012049268 9.339206 15.555206 22.555207 29.555207 35.771207 41.217206 45.109209 48.609209 55.609209 59.50121 63.39321 66.89321 70.78521 77.78521 81.28521 93.73121 103.83921 116.28521 120.94721 131.0552 138.8392 142.3392 148.5552 155.5552 162.5552 166.4472 171.1092 178.1092 182.0012 185.5012 190.16321 196.37921 203.37921 207.27121 212.71721 216.6092 222.82521 227.48722 230.98722 234.48722 244.59522 250.04122 253.54122 260.5412 266.7572 271.4192 275.3112 278.8112 285.8112 290.47319 293.97319 297.86518 304.86518 308.75718 314.2032 317.7032 321.59519 326.25718 332.47319 339.47319 344.9192 348.8112 352.7032 356.59519 363.59519 370.59519 374.09519 377.59519 383.0412 390.0412 395.4872 399.3792 405.5952 416.4872 419.9872 426.20323 430.0952 437.0952 443.31123 450.31123 454.20323 461.20323 468.20323 471.70323 475.5952 481.04124 484.54124 489.20323 495.41923">Request bit in MDM-AP control register. As part of this transition, system clocking is re-</tspan><tspan y="468.25" x=".0012049268 6.2172057 11.663206 15.555206 21.771206 28.771206 32.663209 36.55521 42.00121 49.00121 55.21721 62.21721 65.71721 71.93321 78.93321 85.93321 89.43321 93.32521 98.77121 102.27121 108.48721 115.48721 122.48721 126.37921 133.37921 139.59522 143.48722 149.70322 156.70322 160.59522 164.09522 167.98722 174.98722 178.48722 185.48722 192.48722 197.14922 208.04122 214.25722 218.14922 221.64922 226.31122 233.31122 240.31122 244.20322 254.31122 262.8652 270.6492 279.9872 283.4872 294.3792 301.3792 308.3792 314.5952 318.0952 324.31123 328.20323 335.20323 341.41923 348.41923 352.31123 359.31123 366.31123 369.81123 376.02723 383.02723 390.02723 394.6892 398.5812 405.5812 412.5812 417.2432 423.4592 427.3512 431.2432 438.2432 445.2432">established and is equivalent to normal run/VLPR mode clocking configuration.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 568.6)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x="-.00578 9.44622 14.17222">7.6</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 91.80322 568.6)" font-size="17" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.91602" x="-.00578 14.155221 24.542222 34.929224 45.316225 50.042226 59.494226 64.22022 77.44622 87.83322 97.285228 103.898227 113.35023 119.01123 123.73723 134.12422 144.51122 149.23722 153.96321 164.3502 169.0762 179.4632 189.85019 203.07619 207.80219 219.14119 229.52819 242.75418 252.20618 258.81919 263.5452 277.7062 288.0932 298.4802 307.9322">Module Operation in Low Power Modes</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 54)" font-size="14" font-family="TimesLTStd"><tspan y="551.85" x=".00427 8.5582699 15.5582699 21.77427 25.27427 29.93627 36.93627 40.828275 44.720277 51.720277 61.828279 65.720279 72.720279 79.720279 83.220279 87.112277 93.32828 100.32828 104.220279 110.43628 113.93628 117.82828 121.720279 125.612277 132.61228 138.05828 141.95027 146.61228 152.82828 156.72028 162.93628 168.38228 171.88228 175.77428 182.77428 188.99028 192.49028 197.15229 204.15229 211.15229 217.36829 221.26029 225.15229 232.15229 239.15229 245.36829 249.26029 253.15229 257.04429 264.04429 267.54429 274.54429 279.20628 282.70628 288.92228 295.13829 301.35429 308.35429 311.85429 322.74629 329.74629 336.74629 343.74629 347.63829 353.85429 357.35429 367.46229 374.46229 378.35429 382.24629 388.46229 391.96229 395.85429 402.85429 409.07029 412.57029 418.7863 425.7863 429.67829 436.67829 440.17829 444.07029 449.5163 453.0163 456.9083 463.9083 467.4083 473.6243 479.8403 486.0563">The following table illustrates the functionality of each module while the chip is in each</tspan><tspan y="567.85" x=".00427 7.00427 11.66627 15.16627 19.058272 26.058272 32.274274 35.774274 39.666276 46.666276 56.774278 60.274278 67.27428 74.27428 84.38228 90.59828 95.260288 98.760288 109.65228 116.65228 123.65228 129.86829 135.31429 138.81429 142.31429 146.97629 157.08429 163.3003 170.3003 177.3003 184.3003 187.8003 198.69229 205.69229 212.69229 219.69229 223.58429 229.8003 235.24629 238.74629 244.9623 249.6243 255.8403 259.3403 266.3403 270.2323 275.6783 281.89433 288.89433 294.34034 299.78636 306.00236 313.00236 316.50236 321.94837 328.16438 335.16438 341.38038 346.04237 352.25837 356.15037 362.36637 366.25837 373.25837 377.15037 380.65037 386.09638 392.31239 398.52839">of the low power modes. (Debug modules are discussed separately; see </tspan></text>
<text fill="#0000ff" xml:space="preserve" transform="matrix(1 0 0 1 54.000005 54)" font-size="14" font-family="TimesLTStd"><tspan y="567.85" x="402.02827 412.13627 418.35227 425.35227 432.35227 439.35227 442.85227 446.74427 453.74427 457.24427 465.79826 472.79826">Debug in Low</tspan><tspan y="583.85" x=".004272461 7.7882735 14.788273 24.896275 31.112275 35.774274 39.274274 51.720277 58.720277 65.720279 71.93628">Power Modes</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 54)" font-size="14" font-family="TimesLTStd"><tspan y="583.85" x="77.38226 80.88226 85.544269 89.044269 99.15227 106.15227 117.044269 124.044269 130.26027 134.92227 138.42227 143.08428 149.30028 153.19228 157.08428 164.08428 171.08428 176.53028 180.03028 184.69228 190.13828 197.13828 203.35428 210.35428 213.85428 220.07028 225.51628 229.01628 236.01628 239.51628 251.96228 262.07029 268.2863 271.7863 278.0023 285.0023 292.0023 295.5023 302.5023 306.0023 318.4483 325.4483 332.4483 337.89433 342.5563 346.0563 350.7183 356.9343 363.9343 368.59629 374.8123 380.2583 386.4743 393.4743 397.3663 400.8663 404.7583 411.7583 417.9743 421.4743 432.3663 438.5823 445.5823 449.4743 460.3663 467.3663">.) Number ratings (such as 2 MHz and 1 Mbps) represent the maximum</tspan><tspan y="599.85" x=".0042648317 4.666265 9.328265 15.544266 22.544266 29.544266 35.760267 42.760267 48.976266 52.868268 59.084268 64.530269 68.030269 75.030269 79.69227 83.19227 94.08427 100.30027 107.30027 111.19227 122.08427 129.08426 139.97626 143.47626 150.47626 156.69226 160.58426 166.80027 170.30027 174.96227 181.17827 185.07027 191.28627 196.73227 200.23227 207.23227 213.44828 218.11028 221.61028 232.50228 239.50228 246.50228 252.71828 256.21827 259.71827 269.82627 273.71827 279.16429 286.16429 289.66429 293.16429 297.05628 304.05628 310.27229 315.7183 321.9343 325.4343 329.3263 335.5423 340.20429 351.09629 356.5423 360.0423 366.2583 370.9203 377.1363 380.6363 387.6363 393.0823 399.2983 406.2983">frequencies or maximum data rates per mode. Also, these terms are used:</tspan><tspan y="624.25" x="13.094285 24.000287 31.784287 39.568288 43.068288 50.964288 54.464288 62.248289 69.24829 73.14029 77.03229 80.53229 85.19429 92.19429 99.19429 105.41029 109.30229 113.19429 120.19429 127.19429 133.4103 137.30229 141.19429 145.08629 152.08629 155.58629 159.08629 163.74829 170.74829 174.24829 184.3563 192.9103 200.69429 210.03229 213.53229 219.74829 226.74829 233.74829 237.24829 247.3563 255.9103 263.6943 276.9103 280.4103 284.3023 291.3023 297.5183 301.0183 306.46434 313.46434 318.91035 322.80235 329.01835 339.91035 343.41035 348.07234 352.7343 358.95033 365.95033 372.95033 379.16633 386.16633 392.38233 399.38233 402.88233 406.77433 412.22035 415.72035 419.61235 423.50434 434.39634 438.28834 442.18034 448.39634 455.39634 458.89634 462.39634 469.39634 476.39634 480.28834 483.78834 487.68034 492.34233 495.84233">&#x2022;FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a</tspan><tspan y="640.25" x="24.000325 34.892328 41.892328 48.892328 55.892328 59.78433 66.00033 69.50033 76.50033 83.50033 89.71633 95.16233 98.66233 105.66233 112.66233 116.55433 120.05433 127.05433 133.27033 140.27033 146.48633 149.98633 156.20233 159.70233 163.59433 167.48633 178.37833 182.27033 186.16233 192.37833 196.27033 200.16233 207.16233 214.16233 217.66233 221.55432 228.55432 232.05432 235.94632 239.83832 245.28432 248.78432 253.44632 260.44633 267.44633 273.66233 277.55433 281.44633 288.44633 295.44633 301.66233 305.55433 309.44633 313.33833 320.33833 323.83833 327.33833 331.23033 335.1223 338.6223 342.5143 347.96034 351.46034 356.90635 360.79835 364.69035 368.58235 372.47434 375.97434 379.86634 383.75834 389.20436 393.09635 399.31236 406.31236 409.81236 416.02836 421.47438 424.97438 432.75837 440.54237">module does not have a limitation in its functionality, it is still listed as FF.</tspan><tspan y="656.25" x="13.094335 24.000336 29.446337 33.338338 39.554338 43.44634 47.33834 53.55434 57.05434 64.95034 68.45034 80.89634 87.89634 94.89634 101.89634 105.78834 112.00434 115.50434 120.16634 126.38235 133.38236 137.27436 142.72035 146.61235 152.82836 157.49036 160.99036 166.43636 170.32836 176.54436 180.43636 186.65236 192.09836 195.59836 201.81436 208.81436 215.81436 219.31436 225.53037 230.97637 236.42237 243.42237 249.63837 253.53037 259.74638 263.63838 269.85438 276.85438 280.35438 291.24638 297.46238 308.35438 315.35438 320.01637 323.90837 330.12437 335.57038 339.07038 345.28639 349.94837 356.16438 359.66438 364.32637 370.54237 374.43437 380.65037 384.54237 391.54237 397.75837 404.75837">&#x2022;static = Module register states and associated memories are retained.</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 18)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="26.01031" x="375.47099 381.96897 387.46797 392.47196 397.97096 400.96797 405.97196 409.47297 411.97499 416.97898 419.481 425.48399 430.98298 437.985 442.98899 446.49 448.992 456.489 461.493 466.992 471.996 477.495 482.499 490.5 495.504 501.003">Chapter 7 Power Management</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54.000005 751.756)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x=".00401 5.5030105 8.5000109 13.504011 18.50801 23.00801 27.50801 32.512014 34.510015 39.514017 42.016016 48.019014 53.023015 60.520017 62.518018 67.01802 72.02202 77.02602 82.030017 87.03401 91.53401 94.03601 99.04001 102.03701 104.53901 107.04101 109.54301 114.547008 119.047008">Freescale Semiconductor, Inc.</tspan></text>
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<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 54 763.756)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="180.87 188.65 194.20999 200.31999 205.87999 209.76999 215.32999 218.10999 220.88999 228.10999 234.21999 239.77999 242.55998 248.66999 254.22998 259.78999 265.34999 268.12998 270.90998 277.01997 280.34996 286.45994 290.34996 299.23997 304.79997 308.12995 310.90995 317.01994">General Business Information</tspan></text>
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