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birdcage/docs/K60-refman-vectors/K60-reference-manual_page_163.svg
Ryan Malloy 5252d1d73c Add hardware reference docs (A3981, K60, RYS352A) 
Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint,
3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep.

NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference
manual. Cortex-M4 96MHz MCU running the G2 firmware.

Reyax RYS352A GPS module: datasheet and PAIR command guide.
GPS receiver on the G2 board (used for auto-location/satellite lookup).

All extracted as markdown + page images + vector SVGs for LLM context.
Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.
2026-02-14 18:36:42 -07:00

128 lines
29 KiB (Stored with Git LFS)
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Raw Blame History

<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" version="1.1" width="612" height="777.60006" viewBox="0 0 612 777.60006">
<defs>
<clipPath id="clip_1">
<path transform="matrix(1,0,0,1,54,24.56926)" d="M0 0H504V8.50394H0Z" clip-rule="evenodd"/>
</clipPath>
<clipPath id="clip_2">
<path transform="matrix(1,0,0,1,54,748.5559)" d="M0 0V-1.61732H166.42002V0 1.61732H0" clip-rule="evenodd"/>
</clipPath>
<clipPath id="clip_3">
<path transform="matrix(1,0,0,1,54,748.5559)" d="M166.22 0V-1.61732H337.78V0 1.61732H166.22" clip-rule="evenodd"/>
</clipPath>
<clipPath id="clip_4">
<path transform="matrix(1,0,0,1,54,748.5559)" d="M337.58 0V-1.61732H504V0 1.61732H337.58" clip-rule="evenodd"/>
</clipPath>
</defs>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.13672" x="0 7.784001 11.676002 19.460003 23.352004 31.136004 35.028005 42.812005 46.704008">3.9.8.2.1</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 122.66138 54)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.13672" x="0 10.108001 18.662 27.216 31.108 39.662 43.554 55.216005 63.000005 70.784008 75.44601 83.23001 88.67601 92.56801 102.67601 106.56801 115.12201 122.90601">Audio Master Clock</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="35.25" x="0 8.554 15.554 21.77 25.27 31.486 38.486 45.486 49.378004 56.378004 59.878004 70.770008 76.98601 82.43201 86.324008 92.54001 97.20201 100.70201 106.918018 110.81001 117.81001 124.02602 131.02602 134.52602 139.18802 151.63402 160.97202 169.52602 179.63402 184.29602 187.79602 191.68802 197.13402 200.63402 207.63402 213.08002 219.29602 226.29602 229.79602 233.68802 240.68802 244.18802 251.18802 257.40403 264.40403 270.62004 275.282 281.49803 285.39 291.60603 295.10603 298.99803 305.99803 312.21403 315.71403 322.71403 326.60603 330.49803 333.99803 340.21403 344.10603 351.10603 357.32203 364.32203 367.82203 377.93003 384.93003 391.14604 398.14604 401.64604 405.53804 412.53804 418.75404 422.25404 426.91603 433.13203 439.34803 445.56404 449.45603 456.45603 462.67204 467.334 470.834 477.834">The audio master clock (MCLK) is used to generate the bit clock when the receiver or</tspan><tspan y="51.25" x="0 3.8920005 8.554001 14.770001 21.77 27.216002 38.108 42.000005 45.892007 49.784009 56.000009 60.662008 64.162 68.054 73.5 77 83.216 90.216 97.216 101.878009 105.770008 112.770008 119.770008 124.43201 130.64801 137.64801 141.14801 145.81002 152.81002 157.47202 160.97202 167.18802 174.18802 177.68802 181.58002 188.58002 192.47202 198.68802 203.35002 210.35002 216.56603 220.45803 224.35002 231.35002 234.85002 241.85002 248.06603 255.06603 261.282 265.944 272.16 276.052 282.268 289.268 292.768 299.768 303.66 307.552 311.052 317.268 321.16 328.16 334.376 341.376 344.876 348.376 356.93 363.93 370.146 373.646 379.862 386.862 393.862 397.754 404.754 408.254 419.146 425.362 430.808 434.7 440.91603 445.578 449.078 455.294 459.186 466.186 472.402 479.402 482.902 489.118 495.334">transmitter is configured for an internally generated bit clock. The audio master clock can</tspan><tspan y="67.25" x=".00005 6.2160508 10.108051 15.554052 22.554053 26.054053 33.054056 39.270055 42.770055 49.770055 56.770055 60.662057 67.662059 74.662059 78.554058 82.054058 85.94605 92.94605 96.44605 103.44605 108.108058 111.608058 115.50005 122.50005 129.50006 136.50006 140.39206 143.89206 148.55406 153.21607 160.21607 171.10807 174.60807 180.82407 184.32407 191.32407 195.21607 202.21607 205.71607 209.21607 217.77007 224.77007 230.98607 234.48607 238.37807 243.04007 249.25608 256.25608 261.7021 272.5941 276.48609 280.37809 284.27009 290.48609 295.14808 298.64808 304.86408 311.86408 318.86408 322.36408 327.02607 333.24208 339.45808 345.67408 349.56608 356.56608 362.78208 367.44407 370.94407 377.94407 384.16007 391.16007 397.37608 400.87608 404.76808 411.76808 417.98408 421.48408 426.93009 433.1461 444.0381 450.2541 453.7541 459.9701 466.9701 473.9701 477.8621">also be output to or input from a pin. The transmitter and receiver have the same audio</tspan><tspan y="83.25" x=".00005 10.892051 17.108052 22.554053 26.446053 32.662054 37.32405 40.82405 47.04005 50.932054 57.932054 64.148059 71.148059 74.648059 78.540058 85.540058 92.540058 99.540058 103.43205 108.87805">master clock inputs.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 165.8)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.13672" x=".00005 7.784051 11.676051 19.460053 23.352053 31.136054 35.028055 42.812055 46.704057">3.9.8.2.2</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 122.66138 165.8)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.13672" x=".00005 10.10805 14.000051 18.66205 22.55405 32.662054 36.554056 45.108057 52.892057">Bit Clock</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="147.05" x=".00005 8.5540499 15.5540499 21.77005 25.27005">The I</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="10.5" font-family="TimesLTStd"><tspan y="142.38333" x="29.932049">2</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="147.05" x="35.18205 42.96605 46.85805 54.64205 64.75005 69.412059 72.912059 76.804058 81.46606 87.68206 94.68206 100.12806 111.02006 114.912059 118.804058 122.69605 128.91205 133.57405 137.07405 143.29006 150.29006 157.29006 160.79006 165.45206 171.66806 177.88407 184.10007 187.99207 194.99207 201.20807 205.87007 209.37007 214.81607 221.81607 228.81607 235.81607 242.81607 247.47808 251.37007 254.87007 261.08607 266.53208 273.53208 280.53208 286.74809 293.74809 298.41007 305.41007 312.41007 319.41007 326.41007 331.85609 335.35609 342.35609 346.24809 350.14009 353.64009 359.85609 363.74809 370.74809 376.96409 383.96409 389.4101 392.9101 397.57209 406.9101 416.2481 424.8021 434.9101 440.3561 445.0181 448.5181 452.4101 459.4101 465.6261 469.5181 473.0181 479.2341 485.4501">S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can</tspan><tspan y="163.05" x=".00011062622 7.0001108 13.216111 16.71611 23.71611 29.93211 36.93211 43.14811 47.81011 54.026109 57.91811 64.13411 71.13411 74.63411 78.52611 85.52611 89.418109 95.63411 100.29611 107.29611 113.512119 117.40411 121.29611 128.29611 131.79611 136.45812 141.12012 148.12012 159.01212 162.51212 166.40412 173.40412 179.62012 183.12012 189.33612 196.33612 203.33612 207.22812 214.22812 217.72812 228.62012 234.83612 240.28212 244.17412 250.39012 255.05213 258.55213 264.76814 268.66014 275.66014 281.87614 288.87614 292.37614 299.37614 304.03813 307.53813 312.98414 319.98414 326.98414 333.98414 337.87614 341.76814 347.98414 354.98414 358.48414 364.70014 371.70014 375.59214 381.80815 386.47013 393.47013 399.68614 403.57814 407.47013 414.47013 417.97013 421.47013 430.0241 437.0241 443.2401 446.7401 457.6321 464.6321 471.6321 478.6321 482.5241">be generated internally from the audio master clock or supplied externally. The module</tspan><tspan y="179.05" x=".00011062622 6.216111 10.108111 15.5541119 22.554112 26.054112 31.500113 38.500116 45.500116 52.500116 59.500116 64.16212 68.054119 73.500118 77.000118 80.89211 87.89211 94.108119 97.608119 104.608119 111.608119 115.500118 119.39211 126.39211 133.39212 136.89212 141.55413 148.55413 153.21613 156.71613 162.16213 169.16213 176.16213 182.37813 189.37813 194.04013 201.04013 208.04013 215.04013 222.04013 227.48613 230.98613 237.98613 244.98613 251.20214 255.86414 262.08015 265.97215 269.86415 276.86415 283.86415 287.36415 294.36415 300.58015 304.47215 314.58015 320.79615 327.01216 334.01216 337.51216 341.40415 348.40415 354.62016 358.12016 362.78215 368.99815 375.21415 381.43016 385.32215 392.32215 398.53816 403.20014 406.70014 412.91615 419.91615">also supports the option for synchronous operation between the receiver and</tspan><tspan y="195.05" x=".00011062622 3.892111 8.5541119 14.770112 21.770112 27.216113 38.108114 42.000116 45.892118 49.78412 56.00012 60.662118 67.66212 72.32412 79.32412 86.32412 93.32412 99.54012 103.43212">transmitterproduct.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 277.59999)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.13672" x=".00011 7.784111 11.676111 19.460112 23.352112 31.136113 35.028116 42.812116 46.704118">3.9.8.2.3</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 122.66138 277.59999)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.13672" x=".00011 10.10811 18.66211 26.44611 30.33811 40.44611 44.33811 52.892114 60.676115">Bus Clock</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 53.999986)" font-size="14" font-family="TimesLTStd"><tspan y="258.84999" x=".00012 8.55412 15.55412 21.77012 25.27012 32.27012 39.27012 44.716119 48.216119 54.432119 58.32412 65.32412 71.54012 78.54012 82.04012 85.93212 91.37812 94.87812 101.87812 107.32412 113.54012 120.54012 124.04012 131.04013 138.04013 141.54013 145.43213 152.43213 158.64813 162.14813 168.36414 175.36414 182.36414 186.25614 190.91814 197.91814 201.81014 205.31014 209.97214 216.18814 223.18814 227.08014 232.52614 236.41814 242.63414 247.29615 252.74214 256.24214 262.45814 269.45814 276.45814 279.95814 283.85014 290.85014 294.35014 301.35014 307.56614 314.56614 320.78215 325.44413 331.66014 335.55213 341.76814 345.26814 350.71415 357.71415 364.71415 370.93016 377.93016 382.59214 389.59214 396.59214 403.59214 410.59214 416.03816 419.53816 423.43016 430.43016 434.32215 440.53816 445.20014 449.86213 456.86213 463.86213 467.75413 473.20014 476.70014 482.91615 489.91615">The bus clock is used by the control registers and to generate synchronous interrupts and</tspan><tspan y="274.85" x=".00012 10.108121 22.554123 32.662126 36.162126 40.824125 47.040124 54.040124 61.040124 67.25613 72.702129 76.594127 82.04012">DMA requests.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 357.39997)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.13672" x=".00011 7.784111 11.676111 19.460112 23.352112 31.136113 35.028116 42.812116 46.704118">3.9.8.2.4</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 122.66138 357.39997)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.13672" x=".00011">I</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 122.66138 357.39997)" font-size="10.5" font-family="HelveticaLTStd" font-weight="bold"><tspan y="6.47005" x="3.8921099">2</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 122.66138 357.39997)" font-size="14" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.13672" x="9.73011 19.068112 22.960112 32.29811 42.406114 46.298116 50.190118 57.974119 61.86612 70.42012 78.204128 85.98813 89.88013 98.43413 106.21813 114.77213 122.55614 128.00214 135.78614 140.44814 144.34014 152.89414">S/SAI clock generation</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 53.99997)" font-size="14" font-family="TimesLTStd"><tspan y="338.65" x=".00011 8.55411 14.77011 20.98611 27.98611 31.48611 39.27011 49.378114 54.04011 57.54011 64.540119 70.75612 75.41812 79.31012 86.31012 93.31012 99.52612 104.188129 110.40413 114.29613 117.79613 124.01213 130.22814 137.22814 140.72814 146.94414 153.94414 160.94414 164.83614 169.49814 176.49814 180.39014 183.89014 187.78214 194.78214 200.99814 204.49814 208.39014 215.39014 222.39014 229.39014 233.28214 236.78214 242.99814 246.89014 253.89014 260.10615 267.10615 270.60615 276.05216 282.26817 286.16017 292.37617 298.59217 302.48417 306.37617 313.37617 320.37617 323.87617 327.37617 334.37617 338.26817 345.26817 348.76817 355.76817 359.66017 364.32215 370.53816 376.75416 380.64616 384.53816 391.53816 398.53816 402.03816 408.25416 415.25416 422.25416 425.75416 432.75416 436.64616 443.64616 447.53816 454.53816 460.75416 464.25416 468.91615 475.13215 479.02415 482.91615">Each SAI peripheral can control the input clock selection, pin direction and divide ratio</tspan><tspan y="354.65" x=".00011 7.00011 11.66211 15.16211 22.16211 29.16211 35.37811 38.87811 45.09411 52.09411 59.09411 62.98611 69.986118 73.486118 84.37811 90.59412 96.040119 99.93211 106.14812 110.81012 114.31012 120.52612 124.41812 131.41812 137.63413 144.63413">of one audio master clock.</tspan><tspan y="379.05" x=".00011 8.55411 15.55411 21.770112 25.270112 37.71611 47.05411 55.608114 65.71611 69.21611 73.87811 80.87811 87.87811 94.87811 98.77011 102.27011 111.60811 115.50011 122.50011 128.71611 135.71611 139.21611 147.0001 153.21611 157.10811 163.32411 169.54012 173.43212 176.93212 183.93212 187.82411 191.71611 195.21611 202.21611 206.87812 210.37812 214.27011 221.27011 227.48612 230.98612 243.43212 252.77011 261.3241 271.4321 274.9321 284.2701 291.2701 298.2701 302.1621 306.8241 313.8241 317.7161 321.2161 330.5541 336.7701 343.7701 347.6621 353.10813 357.00013 363.21614 367.8781 371.3781 376.0401 388.4861 397.82414 407.16215 411.82414 424.27015 428.93214 438.27015 446.05415 450.71614 455.3781 458.8781 464.32414 470.54014 474.43214 480.64814 486.86415 490.75614">The MCLK Input Clock Select bit of the MCLK Control Register (MCR[MICS]) selects</tspan><tspan y="395.05" x=".00011 3.8921104 10.892111 17.108113 20.608113 26.824112 30.716113 37.71611 43.93211 50.93211 54.43211 58.324113 65.32411 72.32411 79.32411 83.21611 86.71611 90.60811 97.60811 101.10811 105.00011 112.00011 118.21611 121.71611">the clock input to the I</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 53.99997)" font-size="10.5" font-family="TimesLTStd"><tspan y="390.38334" x="126.378108">2</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 53.99997)" font-size="14" font-family="TimesLTStd"><tspan y="395.05" x="131.6281 139.4121 143.3041 151.08809 161.19609 165.8581 169.3581 180.25009 187.25009 194.25009 201.25009 205.14209 211.3581 216.0201 221.4661 224.9661 237.4121 246.75009 255.3041 265.41209 268.91209 275.91209 279.80409 286.80409 290.69609 297.69609 303.91209 308.57408">S/SAI module&#x2019;s MCLK divider.</tspan><tspan y="419.44999" x=".00010681152 8.554107 15.554107 21.770108 25.270108 36.16211 43.16211 50.16211 57.16211 61.05411 67.27011 69.79011 75.23611 78.73611 91.182109 100.52011 109.07411 119.18211 122.68211 132.79012 136.68212 143.68212 147.57411 154.57411 160.79012 164.29012 173.62812 179.84412 186.84412 190.73612 196.18212 200.07411 206.29012 210.95212 214.45212 219.11412 231.56012 241.66812 251.00612 255.66812 259.16813 265.38414 272.38414 279.38414 284.0461 287.9381 294.9381 301.9381 306.6001 312.8161 318.26213 321.76213 325.6541 332.6541 338.87013 342.37013 354.81614 364.15415 372.70814 382.81614 386.31614 393.31614 397.20814 404.20814 408.10014 415.10014 421.31614 424.81614 429.47813 435.69413 439.58613 443.47813 450.47813">The module's MCLK Divide Register (MDR) configures the MCLK divide ratio.</tspan><tspan y="443.84999" x=".00013681152 8.554136 15.554136 21.770138 25.270138 36.16214 43.16214 50.16214 57.16214 61.054143 67.27014 69.79014 75.23614 78.73614 91.18214 100.52014 109.07414 119.182147 122.682147 132.79015 139.79015 143.68215 150.68215 157.68215 161.57415 165.07415 173.62815 180.62815 186.84415 193.84415 197.73615 203.95215 207.45215 214.45215 218.34415 222.23615 225.73615 232.73615 237.39815 240.89815 244.79015 251.79015 258.00614 261.50614 273.95216 283.29017 291.84416 301.95216 305.45216 314.79017 321.79017 328.79017 332.68217 337.34416 344.34416 348.23616 351.73616 361.07417 367.29017 374.29017 378.18217 383.62818 387.52018 393.73619 398.39817 401.89817 406.56016 419.00617 428.34419 437.6822 442.34419 454.7902 464.8982 473.45219 478.11418">The module's MCLK Output Enable bit of the MCLK Control Register (MCR[MOE])</tspan><tspan y="459.84999" x=".00016681152 6.2161676 13.216167 20.216168 24.108168 28.770169 35.77017 39.66217 45.10817 48.60817 52.50017 59.50017 65.71617 69.21617 76.21617 80.10817 84.77017 90.986179 97.20218 101.09418 104.986179 111.986179 118.986179 122.486179 129.48618 134.14818 137.64818 141.54018 148.54018 154.75618 158.25618 170.70218 180.04018 188.59418 198.70218 202.20218 209.20218 213.09418 220.09418 223.59418 227.09418 235.64818 242.64818 248.86418 252.36418 259.3642 263.2562 270.2562 273.7562 277.6482 283.0942 286.5942 290.4862 297.4862 303.7022 307.2022 311.0942 318.0942 325.0942 332.0942 335.9862 339.4862 344.1482 348.81019 355.81019 366.70219 370.20219 374.09419 381.09419 387.31019 390.81019 397.81019 401.70219 408.70219 412.20219 422.31019 429.31019 435.52619 442.52619 446.02619 458.4722 468.5802 477.1342 480.6342 484.52619 489.9722 493.4722 500.4722">controls the direction of the MCLK pin. The pin is the input from the pin when MOE is 0,</tspan><tspan y="475.84999" x=".00016681152 6.2161676 13.216167 20.216168 23.716168 27.608168 34.60817 40.82417 44.32417 51.32417 55.21617 62.21617 65.71617 69.60817 75.05417 78.55417 82.44617 89.44617 95.66217 99.16217 106.16217 113.16217 117.05417 124.05417 131.05417 134.94617 138.44617 143.10817 147.77017 154.77017 165.66217 169.16217 173.05417 180.05417 186.27017 189.77017 195.98618 199.87818 206.87818 213.09418 220.09418 223.59418 230.59418 234.48618 241.48618 245.37818 252.37818 258.59419 263.25617 266.75617 276.86418 283.86418 290.08018 297.08018 300.58018 313.02619 323.1342 331.68818 335.18818 339.08018 344.52619 348.02619 355.02619">and the pin is the output from the clock divider when MOE is 1.</tspan><tspan y="500.24998" x=".00016681152 8.554167 15.554167 21.770169 25.270169 29.162169 33.82417 40.04017 47.04017 52.486169 63.37817 67.27017 71.16217 75.05417 81.27017 85.932178 89.432178 95.64818 102.64818 109.64818 113.14818 117.81018 124.026187 130.24219 136.45819 140.35019 147.35019 153.5662 158.2282 161.7282 167.9442 174.1602 181.1602 184.6602 188.5522 195.5522 202.5522 208.7682 215.7682 221.9842 228.9842 235.9842 242.20021 249.20021 253.09221 256.98423 263.98423 267.48423 272.93025 279.14625 283.03825 289.25425 295.47026 299.36225 302.86225 309.86225 316.07826 319.97026 330.07826 336.29426 342.51026 349.51026 353.01026 356.90226 363.90226 370.11827 373.61827 380.61827 387.61827 393.06428 396.56428 402.78028 406.67228 413.67228 419.88829 426.88829 430.38829 436.60429 443.60429 450.60429 454.10429 457.99629 464.99629">The transmitter and receiver can independently select between the bus clock and the</tspan><tspan y="516.24996" x=".00016681152 6.2161676 13.216167 20.216168 24.108168 31.108168 34.60817 45.50017 51.71617 57.16217 61.054174 67.27017 71.932178 75.432178 81.64818 85.54018 92.54018 98.75618 105.75618 109.25618 113.14818 120.14818 123.64818 130.64818 136.86418 143.86418 150.08019 154.74219 160.95819 164.85019 171.0662 174.5662 178.45819 185.45819 191.6742 195.1742 202.1742 206.0662 209.95819 213.45819 219.6742 223.5662 230.5662 236.7822 243.7822 247.2822 250.7822 259.33619 265.5522 271.7682 278.7682 282.2682 293.1602 300.1602 307.1602 314.1602 318.0522 324.2682 326.78819 332.2342 335.7342 345.0722 348.9642 355.9642 362.1802 369.1802 373.0722 380.0722 387.0722 390.5722 403.01823 410.01823 417.01823 423.23423 426.73423 431.3962 435.2882 441.5042 445.3962 452.3962 455.8962 462.8962 467.5582 471.0582 474.9502 481.9502">audio master clock to generate the bit clock. Each module's Clocking Mode field of the</tspan><tspan y="532.24996" x=".00016681152 8.554167 13.216167 19.432168 26.432168 31.878169 42.77017 46.66217 50.554174 54.054174 63.392175 70.39217 77.39217 82.05418 85.946178 92.946178 99.946178 104.60818 110.82418 114.71618 118.60818 125.60818 132.60819 136.10819 143.10819 146.60819 155.94618 162.16219 169.16219 173.05419 178.50019 182.39218 188.60819 193.27019 196.77019 202.98619 209.98619 216.98619 220.48619 229.82419 236.04019 242.2562 248.4722 252.3642 259.3642 265.5802 269.0802 278.4182 285.4182 292.4182 297.0802 300.9722 307.9722 314.9722 319.6342 325.8502 329.7422 333.6342 340.6342 347.6342 351.1342 358.1342 361.6342 370.9722 377.1882 384.1882 388.0802 393.5262 397.4182 403.63423 408.2962 411.7962 416.4582 425.01219 434.3502 443.6882 450.6882 455.3502 467.7962 475.5802 484.1342 492.68818">Transmit Configuration 2 Register and Receive Configuration 2 Register (TCR2[MSEL]</tspan><tspan y="548.24996" x=".00016681152 6.2161676 13.216167 20.216168 23.716168 33.05417 42.39217 51.73017 58.73017 63.39217 75.83817 83.62218 92.17618 100.73018 105.39218 110.054187 113.554187 119.00018 125.21619 129.10819 135.32419 141.54019 145.43219 150.87819 154.37819 158.27019 165.27019 171.48619 174.98619 185.87819 192.0942 197.54019 201.43219 207.6482 212.3102 215.8102 222.0262 225.9182 232.9182 239.1342 246.1342">and RCR2[MSEL]) selects the master clock.</tspan></text>
<g clip-path="url(#clip_1)">
<path transform="matrix(1,0,0,1,54,24.56926)" d="M0 0H504L488 16H0V0Z" fill="#666666"/>
<path transform="matrix(1,0,0,1,54,24.56926)" stroke-width=".8" stroke-linecap="butt" stroke-miterlimit="4" stroke-linejoin="miter" fill="none" stroke="#666666" d="M0 0H504L488 16H0V0Z"/>
</g>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 17.99997)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="26.01031" x="378.495 384.99299 390.49198 395.49598 400.99497 403.99198 408.99598 412.49699 414.999 420.003 422.505 429.003 434.50199 437.004 442.503 445.005 451.503 457.00199 462.50099 465.498 468 473.499 478.998 482.499 487.503 490.5 493.002 498.501">Chapter 3 Chip Configuration</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 734.9386)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="130.01 137.23 142.79 148.34999 151.12999 157.79999 163.90999 170.01999 173.34999 179.45999 185.01999 193.90999 196.68999 199.46999 205.02999 207.80998 215.02999 220.58998 223.91999 229.47998 233.36998 238.92998 245.03998 250.59998 256.15998 258.93998 267.26997 272.82997 278.93995 285.04994 290.60993 293.38993 296.16993 298.94993 306.16993 311.72993 317.28993 320.06993 322.8499 328.4099 331.1899 336.7499 342.8599 348.96989 351.74989 357.30989 362.86988 368.42988">K60 Sub-Family Reference Manual, Rev. 2 Jun 2012</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 751.7559)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x=".00401 5.5030105 8.5000109 13.504011 18.50801 23.00801 27.50801 32.512014 34.510015 39.514017 42.016016 48.019014 53.023015 60.520017 62.518018 67.01802 72.02202 77.02602 82.030017 87.03401 91.53401 94.03601 99.04001 102.03701 104.53901 107.04101 109.54301 114.547008 119.047008">Freescale Semiconductor, Inc.</tspan></text>
<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 220.32 751.7559)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="58.45 65.12 69.01 74.57 77.35 80.13 89.02 91.799999 97.909999 103.46999 107.35999">Preliminary</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 391.68 751.7559)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="151.308 156.312 161.316">163</tspan></text>
<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 54 763.7559)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="180.87 188.65 194.20999 200.31999 205.87999 209.76999 215.32999 218.10999 220.88999 228.10999 234.21999 239.77999 242.55998 248.66999 254.22998 259.78999 265.34999 268.12998 270.90998 277.01997 280.34996 286.45994 290.34996 299.23997 304.79997 308.12995 310.90995 317.01994">General Business Information</tspan></text>
<g clip-path="url(#clip_2)">
<path transform="matrix(1,0,0,1,54,748.5559)" stroke-width=".4" stroke-linecap="round" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#000000" d="M0 0H166.42002"/>
</g>
<g clip-path="url(#clip_3)">
<path transform="matrix(1,0,0,1,54,748.5559)" stroke-width=".4" stroke-linecap="round" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#000000" d="M166.22 0H337.78"/>
</g>
<g clip-path="url(#clip_4)">
<path transform="matrix(1,0,0,1,54,748.5559)" stroke-width=".4" stroke-linecap="round" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#000000" d="M337.58 0H504"/>
</g>
<g transform="matrix(.26,0,0,.26,0,-.000019073487)">
<image id="image_5" width="288" height="154" xlink:href="data:image/png;base64,
iVBORw0KGgoAAAANSUhEUgAAASAAAACaCAIAAACGxwJwAAAACXBIWXMAAA7EAAAO
xAGVKw4bAAAM5klEQVR4nO2d22sd1xWHDYYaDC0uxaWUlogGAn4wCFroq/8E/wl+
aaFvAj009EBEm0JoSeKA01BTtQ5VLjg4luP2GFxfiyMaxfcYy0ZFvqqyghzZMr4o
RmW6rFMfjs6Z2bMv6zf7zMzvYz3r7Dlnf5rZa63Ze11CCIGxLvYACKkyFIwQIBSM
ECAUjBAgFIwQIBSMECAUjBAgFIwQIBSMECAUjBAgFIwQIBSMECAUjBAgFIwQIBSM
ECAUjBAgFIwQIBSMECAUjBAgFIwQIBSMECAUjBAgFIwQIBSMECAUjBAgFIwQIBSM
ECAUjBAgFIwQIBSMECAUjBAgFIwQIBSMECAYwW7vSaZH1OLaTsggnbh74vN//kkx
jl39qh0TM/eKuYi5+8udn3vki1OHT+/WismpnbPzI1HizsLOpYcnWlHMN2kPRrDP
tiXNdZoR3bHpkc///IM//PanWtH45N+dUYxjb5+81fmhv3z/teE//lglXh4dPH76
G5NfrOuHOHN505WZbTfnhhYW9zx6cr6AL9ZASQSTkLtiRKZHlg+u/+vvB0GCvXpo
5snT/0KvQG5ZXR+qKNhfmt+P7lVWXLg6MHN7x+LSOPTrzaI8gkksxftvJE+qzXXX
Pvg2SDCJj899iRv+4qOn4jBIsFf2bI1ukaVp8jy5slLQA3mLUgn2j03RHFsVTOLQ
rpdAgklcW3gMGv7oxGzvx2kJ9vdPvxldHvuQB8giNSuVYBKnBpOnhf4H+j/PBXsw
vmH0tZ+ABHv9yA3E2KfuPEz9OBXBdu0fiO6M392smIxI2QRrOVY8zwWTUMl2pM54
CVkp6Q5clnbiLUiwl0cHPz23Prot3iG3Mt1vu5cSCiZxcQdk2AY6BJPY+8ZWkGAS
sl5SHHjz0kLWB4ULNnb4u9ElCYyZ29i5VE7BJGTGF8lawf6z91s4wWS9pDXqufvL
hg8KFOx3H74UXY/+d6y0gjWLTdyvFUzi2Ds/AgkmcfbWksqouwpfuoId/tfG6G5o
xc25IZUvvJcyC9YsMHHfI9jywfUh2Q6zYCplsYmZe+ZPCRFs9yc/jG6FboAKZSUX
rLDEfY9gElfGNoMEawSXxVILX1qClT23kRpnLm9C5O5LLpjE8YEiEvdpgkkceGsL
SLBGWFnsvcm53L/vLdj+k5ui+4AIRFKx/II1CymOZQi2sG8jTjDvslhW4UtFsMrk
NlJj+evrqvOmGoI18Yn7DMEkTu1+ASRYw6ssZih8qQjWP029iFC/iVVFMIkpVCLo
GdmC+TUBWwrWcC+LGQpf4YL1c1OvSshKTHfiVEiwJjJxny1Y4tUEbC+YU1nMXPgK
FKwsTb2BoZtOrJZgEndPQK7IKFjinu2w16DhUhYzF74CBStXU6936NadKycYKHGf
J5hrE7CTYJZlsdzCV4hgb370YvSpX0xcuDqgOHEqJ1gTk7jPEyxxbAJ2MqFhURaz
KXx5C1bJwpchFHOJVRSsCUjcWwgmYZ/tcBWskVcWsyl8eQtWgaZep1BchlVUsKZ2
4t5OMPsmYA/BDGUxy8KXn2Cvjm2xnJdXZrahQ57fChBMMVlfXcF0HbMTLLFuAvbw
oZFRFrMvfPkJZt/Uq/ZtW/DoyfmFxT3TN7YjBFPMc1RasKZe4t5aMMsmYD/BGmll
MfvCl4dgTk29Ol+1I7JekjubrmDyB7WGV3XBJOY1nqetBZO4+O73cIJ1lcWcCl+u
grnmNhS+Z1/knqMo2KVptbfmayCYSuLeRbDE4pVnbyskZMXVHpdT4ctVsL1Hv+M0
L0O/5ABWVu7pLs+0BlYDwVqOBSYVHQXLbQIOEaxdFnMtfDkJ5tHUqzN5fJElGQWL
F4GJe0fBkrwm4BAxJGTdJY65Fr6cBPNo6tWbQJ6cuaz2Ho3WkGojmMSZ7f5X5C6Y
OdsRKJhEyMNhrmB+Tb16E8gTxWyH1pDqJFgzIHHvLlhibAIOFyw8sgR7Zc9Wv74N
1Tnkw825IQoWO/wS916CJdlNwNHtMgjm3dSrPIvcmZ0foWB9EB6O+Qr2YHxDuQQL
aerVn0iOULD+CI/Eva9gSUYTcHS7UgULPIUIMpdcoGB9E+LY4+sOVxQgWJLWBBzd
rlTBApt6IXPJBQrWT+GUuA8TrLcJOLpdvYLZN/VSMHvKIJj8tYs7II59Zt1yFiZY
0nPuUXS7egULf2EZMpdcoGABGsgNB+GYZeI+WLCuslh0u7oEU9mpFzKXXFDsSNQa
UnkEk8c5kGM2B0AHC5asbQKOblenYFovLEPmkgssNAcIJiydf5acQDiWm7jXECzp
aAKOblenYK5NvX0rmJZddRUsWXUMIVhu4l5JsHa2I7pdbcEUd+qFzCVrFpfGKViw
YILcbUCOGRL3SoIlz5uAo9vVFkzxFCLIXLJG95UwrVGVULBEc7qvCUPiXu8TW9mO
6Ha1BNPdqRcyl+xY/vq64oXUXjABlLjPOgBaVekrY5uj2yXxm32/1t2MDTKX7FDf
NUBrYKUVLCk2ca8q2MK+jdHtknjjb7/qz0npiu7D4aTqDvVlFgyXuO89AFpVsANv
bYluV2P1EVH3pC/IXDKC2PFmsnab3hj6LR5fLyhxrydYqxoW3a6WYLpb9i49PFFM
LC6Nz86PgPZso2BrwRXHOhP3SoK1+zmi29V4nkWs3mnL4VGzjUdzOwZxifu2Y0qC
tbcljW5Xo6PQrJipr0bUbOtsm5bcazshjrUT9xqCdfbUR7erU7DwPvqKRc0Of7Ds
eYcm7jUE63wrLLpdjbXNvnU73sEQ9Tu+yP6lEtB7aKJusGBd7zVHt6tLsLodUGSI
+h3AZy8YLnEflkfpPZ4vul2NnvfBdu0fiD65+yHqd4SsvWAJMnEfEF1vW/anYCrv
XJY9ankIupNgCTJx7xWpuyNGtytVsJocc26Im3NDuipUUTBhfjy6V61YPrg+9djL
6HalCua9p29lQjF/2KKigiWw4phjZB3cHN2uLMECd24rdeimN1pUV7AElri3DsMZ
K9HtyhJM9xXMEoWsvlZWVM/1XqXSgglntkcULGvf7D4XTEK3CbgUcWfBYmsWd6ou
GC5xnxdXxjbjji8anZi9tvAYJ5j3+Q8lDcXu3i6qLliy6ljhScXck5oD3Zi7vyxX
9vG5L0GC1aoJ+NL0IOLhsEUNBEsiJO7bTb0IwZqXFlqXFXgGX+4RsnVoApal16Mn
wScMZ1MPwZJCE/e9G2UrCvb6kRut82NbnL21hBOs8tmOC1cHoHYlNRIsKS5xn3sC
eohgnSegt5D1GEiwajcBy7oL92TYpk6CJUUk7rMKXyqCvTc513tNi4+e4gSrZBOw
PBaCcoa91EywBOtYb1OvomCy3BKXUq/p2NWvQIJVrAlY1Jq5vaOAG1eb+gmGTNz3
NvUqCjYxY5oWsjYDCVaNJuBL04Ny1ypSrRb1EyxZdez4gLpdNrkNb8HePnnLfE0e
ZTF7wcr4yrMssSRm50cWl8aL96pNLQVL9BP3WU29WoK1Cl9mXMti9oIN2zUB6/9M
5aeuggl3TygO0jK34SdYu/BlxrUs5iSYTRMw5GcqOTUWLFFL3D8Y3+Bkl5NgXYUv
M05lMSfBJN786EUK5kq9BROmhsJHaGjqDRest/Blxr4s5irYcF4TMOgnKjW1FywJ
Tdybm3oDBUstfJmxL4t5CGZuAkb8OGWHggUl7nObekMEMxS+zFiWxTwEM2c71H+Z
CkDBVvF1rHWaHkgwc+HLjE1ZzE+w4ewmYMUfpDJQsOe4J+6dCl+uguUWvszYlMW8
BctqAtb6KaoEBevA8QBom6Zeb8FsCl9mcsti3oINZ5ybrvIjVAwKthbrxH3rFCKQ
YJaFLzO5ZbEQwVKbgMPHXD0oWA8Wu2TbN/V6COZU+DJjLouFCDac1gSsMuaKQcHS
yEvc2zf1egjmWvgyYyiLBQo23NMErDjsykDBMshOKobkNnIF8yh8mZG1HE6wriZg
3ZFXAwqWQXbi3qmp10kw78KXmayyWLhgw2tfeVYfeQWgYNmkJe5dm3qdBBMTENch
K7rUspiKYJ1NwIjBlx0KZmRt4t6jqddesMDCl5nUspiKYMMdTcC48ZcXCpZHR+Le
o6nXXjBxAHodsroDCdbOdkDHX1IomAWrB0CnnkKkJZhK4ctMb1lMUbBWEzD6EsoI
RrCpoWdWaMWU8pFNfld06IOfHRj7hVaMTsx2hlbhy8zZW0udH7r76PvvHPy5Vhw9
vb2ASygdvK0TAoSCEQKEghEChIIRAoSCEQKEghEChIIRAoSCEQKEghEChIIRAoSC
EQKEghEChIIRAoSCEQKEghEChIIRAoSCEQKEghEChIIRAoSCEQKEghEChIIRAoSC
EQKEghEChIIRAoSCEQKEghEChIIRAoSCEQKEghEChIIRAoSCEQKEghEChIIRAuR/
5TMAQ7zJBDQAAAAASUVORK5CYII="/>
</g>
</svg>
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