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Ryan Malloy 5252d1d73c Add hardware reference docs (A3981, K60, RYS352A) 
Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint,
3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep.

NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference
manual. Cortex-M4 96MHz MCU running the G2 firmware.

Reyax RYS352A GPS module: datasheet and PAIR command guide.
GPS receiver on the G2 board (used for auto-location/satellite lookup).

All extracted as markdown + page images + vector SVGs for LLM context.
Binary assets (PDFs, PNGs, SVGs, STEP, WRL) stored via git-lfs.
2026-02-14 18:36:42 -07:00

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34 KiB (Stored with Git LFS)
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="15" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.89648" x="0 8.340001 16.680003 20.850003 29.190003 33.360006 41.700006 45.870008">25.4.1.2</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 122.3833 54)" font-size="15" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.89648" x="0 12.495001 23.325 34.995004 39.165006 52.500009 61.66501 70.83001 79.17001 83.34001 91.680019 103.35001 107.52001 112.515018 120.85502 130.02002 134.19002 143.35501">MCG mode switching</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="36.25" x=".00401 8.55801 15.55801 21.77401 25.27401 34.61201 41.61201 46.27401 50.93601 60.27401 68.82801 76.612018 84.39602 89.05802 92.55802 99.55802 103.45002 107.34202 110.84202 117.05802 123.274028 130.27402 133.77402 140.77402 146.99002 150.49002 156.70603 163.70603 169.92203 176.92203 183.92203 190.13803 197.13803 200.63803 206.85404 210.74604 214.24604 220.46204 227.46204 234.46204 237.96204 241.85404 245.74604 256.63804 262.85404 266.35404 269.85404 276.85404 283.85404 287.74604 291.24604 295.13804 302.13804 308.35404 311.85404 318.07005 324.28605 328.17805 335.17805 341.39405 345.28605 348.78605 354.23207 364.34007 368.23207 372.12406 378.34007 385.34007 388.84007 392.73207 399.73207 403.23207 407.12406 414.12406 420.34007 423.84007 430.84007 437.05607 447.16407 451.05607">The C1[IREFS] bit can be changed at any time, but the actual switch to the newly</tspan><tspan y="52.25" x=".00402 5.450021 11.666021 15.558022 21.774022 27.99002 31.88202 38.098024 45.098024 48.598024 53.26002 59.47602 64.13802 70.35403 75.01603 81.23203 88.23203 94.44804 100.66404 104.16404 110.38004 114.27204 121.27204 127.488048 134.48804 139.93404 143.43404 147.32604 152.77204 156.27204 161.71804 168.71804 175.71804 185.82604 192.82604 196.32604 203.32604 210.32604 213.82604 217.71804 224.71804 230.93404 234.43404 242.21804 246.88004 251.54204 260.88005 269.43403 277.21803 285.002 293.556 298.218 301.718 308.718 312.61 316.50199 320.00199 323.50199 336.718 343.718 349.934 356.934 360.434 365.88 375.988 379.88 383.772 389.988 396.988 400.88 407.88 414.88 418.38 425.38 431.596 435.488 445.596 451.812 458.028">selected reference clocks is shown by the S[IREFST] bit. When switching between</tspan><tspan y="68.25" x=".00405 6.2200505 13.220051 20.22005 26.43605 33.43605 39.65205 46.65205 50.15205 54.044054 61.044054 64.93605 71.152057 75.81406 82.81406 89.03006 92.92206 96.42206 102.63806 109.63806 116.63806 120.13806 126.354068 133.35407 140.35407 146.57007 153.57007 159.78607 166.78607 170.28607 176.50208 183.50208 187.39408 193.61008 198.27208 205.27208 211.48809 215.38008 218.88008 229.77208 236.77208 243.77208 249.98809 255.43408 258.93409 262.43409 266.32609 273.32609 279.54209 283.04209 290.82609 299.38008 307.93406 311.43406 321.54206 325.43406 329.32606 333.21806 336.71806 343.71806 349.93406 356.93406 360.82606 367.82606 371.32606 375.21806 382.21806 388.43406 395.43406 399.32606 406.32606 413.32606 416.82606 423.04206 430.04206 436.25807 440.15007 447.15007 450.65007 456.86607 461.52806 465.42005 471.63606 476.29804 479.79804 483.69004 490.69004">engaged internal and engaged external modes, the FLL will begin locking again after the</tspan><tspan y="84.25" x=".0041 5.4501006 15.558102 19.450102 23.342103 29.558102 36.5581 40.0581 43.950105 49.396104 52.896104 59.112104 66.11211 77.004108 84.004108 87.8961 94.11211 98.004108 104.22011 111.22011">switch is completed.</tspan><tspan y="108.65" x=".00411 8.55811 15.55811 21.77411 25.27411 34.612115 41.612115 46.274114 55.612115 64.166118 74.27412 82.05812 86.72012 90.22012 97.22012 101.11212 105.00412 110.45012 113.95012 120.16612 126.382129 133.38213 136.88213 143.09813 146.99013 152.43613 159.43613 162.93613 169.93613 176.15213 179.65213 185.86814 192.86814 199.08414 206.08414 213.08414 219.30014 226.30014 229.80014 236.01615 239.90814 243.40814 249.62415 256.62416 263.62416 267.12416 271.01615 274.90815 285.80015 292.01615 295.51615 299.01615 306.01615 313.01615 316.90815 320.40815 324.30015 331.30015 337.51615 341.01615 347.23216 353.44816 357.34016 364.34016 370.55616 374.44816 377.94816 383.39418 393.50218 397.39418 401.28617 407.50218 414.50218 418.00218 421.89418 428.89418 432.39418 436.28617 443.28617 449.50218 453.00218 460.00218 466.21818 476.32618 480.21818">The C1[CLKS] bits can also be changed at any time, but the actual switch to the newly</tspan><tspan y="124.65" x=".0041 5.4501006 11.666101 15.558102 21.774102 27.9901 31.882102 38.098104 45.098104 48.598104 54.814104 58.706106 65.7061 71.922107 78.922107 82.422107 86.3141 91.7601 95.2601 100.7061 107.7061 114.7061 124.8141 131.8141 135.3141 142.3141 149.3141 152.8141 156.7061 163.7061 169.9221 173.4221 181.2061 185.8681 195.2061 203.7601 213.8681 221.6521 230.2061 234.8681 238.3681 245.3681 249.2601 253.1521 258.5981 262.0981 265.5981 270.2601 274.9221 278.4221 282.3141 289.3141 295.5301 299.0301 306.0301 312.2461 322.3541 326.2461 333.2461 336.7461 342.1921 348.4081 352.3001 358.5161 364.73213 368.6241 374.84013 381.84013 385.34013 391.55613 395.44813 402.44813 408.66413 415.66413 419.16413 423.05613 428.50215 432.00215 439.00215 446.00215">selected clock is shown by the S[CLKST] bits. If the newly selected clock is not</tspan><tspan y="140.65001" x=".0041300004 6.2201306 13.220131 19.43613 23.32813 27.22013 33.43613 40.43613 44.328134 50.544134 54.044134 57.544134 61.436136 68.436138 74.65214 78.15214 85.15214 89.81414 96.03014 103.03014 106.92214 113.92214 120.92214 126.36814 129.86814 136.08414 139.97614 146.97614 153.19214 160.19214 163.69214 173.80014 177.69214 181.58414 185.47614 188.97614 193.63814 199.85414 210.74614 216.96215 220.85414 227.85414 231.35414 236.80014 243.01615 246.90814 253.12415 259.34016 263.23216 269.44816 276.44816">available, the previous clock will remain selected.</tspan><tspan y="165.05" x=".0041300004 8.55813 15.55813 21.774132 25.274132 34.612134 41.612134 46.27413 56.382135 65.72014 73.50414 82.05814 89.05814 99.166149 108.50415 116.288158 120.95016 124.45016 134.55815 139.22016 143.11215 147.00415 153.22016 156.72016 163.72016 167.61215 171.50415 176.95015 180.45015 186.66616 192.88216 199.88216 203.38216 210.38216 216.59816 220.09816 226.31417 233.31417 239.53017 246.53017 253.53017 259.74617 266.74617 270.24617 276.46217 280.35417 283.85417 290.07017 297.07017 304.07017 307.57017 311.46217 315.35417 326.24617 332.46217 335.96217 342.17817 349.17817 355.39418 361.61018 368.61018 372.50218 376.00218 386.11018 393.11018 399.32618 406.32618 409.82618 419.16419 426.16419 430.82618 439.38017 447.16416 451.82615 455.32615 462.32615 466.21815 470.11015 473.61015 477.50215 482.94816 486.44816 493.44816">The C4[DRST_DRS] write bits can be changed at any time except when C2[LP] bit is 1.</tspan><tspan y="181.05" x=".0041600007 4.66616 9.32816 12.82816 16.720162 23.720162 29.936161 33.43616 42.774164 49.774164 54.43616 64.54416 73.88216 81.66616 90.22016 97.22016 107.32816 116.66617 124.45017 129.11217 132.61217 142.72017 147.38217 151.27417 155.16617 161.38217 164.88217 171.88217 175.77417 179.66617 185.11217 188.61217 194.82817 199.49018 205.70618 209.20618 215.42218 222.42218 228.63819 235.63819 242.63819 248.85419 255.85419 259.3542 269.4622 276.4622 280.3542 284.2462 290.4622 293.9622 297.8542 304.8542 308.3542 316.13819 324.69218 333.24617 336.74617 342.96217 349.96217 356.96217 363.17817 370.17817 376.39418 383.39418 386.89418 390.78617 397.78617 401.67817 407.89418 412.55616 419.55616 425.77217 429.66416 433.16416 437.82615 445.61015 454.16413 458.8261 463.4881 466.9881 473.9881">If the C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or</tspan><tspan y="197.05" x=".0041600007 7.788161 16.342162 24.89616 28.39616 34.61216 41.61216 48.61216 54.82816 61.82816 68.04416 75.04416 78.54416 84.76016 91.76016 95.65216 101.868167 106.53017 113.53017 119.74617 123.63817 127.13817 131.80017 139.58417 148.13817 156.69217 161.35417 164.85417 168.35417 172.24617 179.24617 185.46218 188.96218 201.40818 210.74617 220.85417 230.96218 241.07018 249.62418 258.9622 267.51618 277.62419 281.12419 291.23219 295.12419 299.01618 302.90818 306.40818 311.8542 321.9622 325.8542 329.7462 335.9622 342.9622 346.4622 350.3542 357.3542 360.8542 364.7462 371.7462 377.9622 381.4622 388.4622 394.6782 404.7862 408.2862 413.7322 419.9482 423.8402 430.0562 436.27223 440.1642 446.38023 453.38023 456.88023 466.98823 476.32624">FLL engaged external (FEE), the MCGOUTCLK will switch to the new selected DCO</tspan><tspan y="213.05" x=".0041600007 4.66616 10.88216 17.88216 24.88216 31.09816 34.59816 44.70616 48.598165 52.490167 59.490167 63.382169 70.38217 73.88217 77.77417 84.77417 89.43617 95.652179 101.86818 105.36818 111.58418 115.47618 122.47618 128.69219 135.69219 141.13819 144.63819 151.63819 156.30019 159.80019 163.69219 170.69219 176.90819 180.40819 185.85419 192.07019 195.96219 202.17819 208.3942 212.2862 218.5022 225.5022 229.0022 239.1102 248.4482 258.55619 262.05619 268.2722 272.16419 279.16419 285.3802 292.3802 295.8802 299.3802 309.4882 314.15019 318.04219 324.25819 328.92018 332.42018 337.86619 347.97419 351.86619 355.75819 361.97419 368.97419 372.86619 379.86619 386.86619 390.36619 394.25819 401.25819 404.75819 408.65019 415.65019 421.86619 425.36619 432.36619 438.58219 448.6902 452.1902 462.2982 471.6362 481.7442">range within three clocks of the selected DCO clock. After switching to the new DCO,</tspan><tspan y="229.05" x=".0041600007 3.8961604 10.89616 17.11216 20.61216 28.39616 36.95016 45.50416 49.00416 53.66616 59.88216 70.77416 76.990169 80.882167 87.882167 93.32816 96.82816 103.82816 110.82816 114.72016 121.72016 127.936168 134.93616 141.15216 148.15216 151.65216 156.31417 163.31417 167.97617 171.47617 176.92217 183.13817 190.13817 196.35417 201.01618 207.23218 211.12418 214.62418 219.28618 225.50218 230.16419 236.38019 241.04219 247.2582 254.2582 260.47419 266.6902 270.1902 276.4062 283.4062 289.6222 293.5142 299.7302 305.1762 308.6762 312.1762 322.2842 331.62223 341.73023 345.23023 350.67625 354.56825 360.78425 365.44624 369.33824 376.33824 383.33824 386.83824 390.73023 394.62223 405.51423 411.73023 415.23023 419.12223 424.56825 428.06825 434.28425 441.28425 448.28425 454.50025 458.39225 461.89225 465.78425 472.78425 476.28425 480.17625 487.17625">the FLL remains unlocked for several reference cycles. DCO startup time is equal to the</tspan><tspan y="245.05" x=".0041600007 7.788161 16.342162 24.89616 28.39616 34.61216 40.82816 47.82816 54.82816 58.72016 64.16616 68.05816 71.95016 75.842159 82.842159 89.842159 93.342159 97.23415 101.12615 112.01815 118.23415 121.73415 125.23415 135.34215 140.00415 143.89615 150.11215 154.77416 158.27416 162.16616 169.16616 175.38216 178.88216 184.32816 190.54416 194.43616 200.65216 206.86817 210.76016 216.97617 223.97617 227.47617 237.58417 246.92217 257.03016 260.53016 265.97618 269.86817 276.08418 280.74617 284.63816 291.63816 298.63816 302.13816 306.03016 309.92216 320.81416 327.03016 330.53016 334.42216 339.86817 343.36817 350.36817 357.36817 363.58418 368.24617 371.74617 375.24617 379.13816 386.13816 392.35417 395.85417 403.63816 412.19215 420.74613 424.24613 428.13813 433.58415 437.08415 440.97615 447.97615 454.19215 461.19215 467.40815 474.40815 477.90815 481.40815 489.96214 496.96214">FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The</tspan><tspan y="261.05" x=".0041600007 6.2201607 13.2201609 24.112162 31.112162 35.00416 41.22016 45.112165 49.004167 56.004167 63.004167 66.504169 73.504169 78.16617 81.66617 85.55817 92.55817 98.77417 102.27417 107.72017 117.82817 121.72017 125.61217 131.82817 138.82817 142.32817 146.22017 151.66617 155.16617 160.61217 167.61217 174.61217 184.72017 191.72017 195.22017 202.22017 209.22017 212.72017 216.61217 223.61217 229.82817 233.32817 242.66617 249.66617 254.32817 264.43617 273.77418 281.55818 290.11216 297.11216 307.22016 316.55818 324.34217 329.00416 332.50416 337.16615 343.38215 349.59815 356.59815 360.09815 367.09815 370.99015 374.88215 380.32817">completion of the switch is shown by the C4[DRST_DRS] read bits.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 355.6)" font-size="16" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.15625" x=".00416 8.900161 17.796162 22.244162 31.140164 35.588167">25.4.2</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 112.65332 355.6)" font-size="16" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.15625" x=".00416 9.78016 19.55616 32.00416 36.452165 47.124166 56.900167 69.34817 78.24417 84.46817 88.91617 100.46817 104.91617 110.24417 114.69217 126.24417 135.14017 144.03617 153.81217">Low Power Bit Usage</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="337.85" x=".00015 8.55415 15.55415 21.77015 25.27015 34.60815 41.60815 46.27015 54.82415 62.60815 67.27015 70.77015 77.77015 81.66215 85.554149 89.054149 92.946147 98.39214 101.89214 108.89214 113.554149 120.554149 127.554149 131.44615 138.44615 144.66216 151.66216 155.16216 159.05416 166.05416 169.55416 175.77016 179.66216 183.55416 190.55416 200.66216 204.16216 208.05416 215.05416 221.27016 224.77016 232.55416 241.10816 249.66216 253.16216 260.16218 264.82417 268.32417 276.10816 284.66215 293.21614 296.71614 300.60813 307.60813 311.10813 318.10813 324.32414 327.82414 334.82414 338.71614 344.16215 350.37815 357.37815 361.27015 367.48616 374.48616 377.98616 384.20216 391.20216 398.20216 401.70216 405.59416 412.59416 419.59416 425.04017 428.54017 434.75617 441.75617 448.75617 454.20219 460.41819 465.08018 472.08018">The C2[LP] bit is provided to allow the FLL or PLL to be disabled and thus conserve</tspan><tspan y="353.85" x=".00016000001 7.00016 14.00016 24.108162 30.324162 34.98616 38.48616 48.594163 55.594163 61.81016 68.810169 72.310169 76.20216 83.20216 89.41817 94.86417 101.08017 104.58017 110.02617 117.02617 122.47217 126.36417 132.58017 143.47217 148.91817 152.41817 158.63417 163.29618 169.51218 173.01218 180.01218 187.01218 190.90418 194.40418 201.40418 207.62018 211.51218 218.51218 225.51218 229.01218 236.01218 241.45818 247.67418 254.67418 258.1742 261.6742 270.22819 277.22819 283.44419 286.94419 296.2822 303.2822 307.94419 318.0522 327.3902 335.1742 343.72819 350.72819 360.83619 370.1742 377.9582 382.62019 386.12019 392.33619 398.5522 405.5522 409.0522 416.0522 423.0522 426.94419 430.44419 437.44419 443.6602 447.1602 457.2682 461.93019 465.82218 469.71418 473.60618 479.82218">power when these systems are not being used. The C4[DRST_DRS] can not be written</tspan><tspan y="369.85" x=".00016000001 10.108161 17.108162 21.000163 24.892163 31.108162 34.608163 43.946165 50.946165 55.608163 64.16216 71.94617 76.60817 80.10817 87.10817 91.00017 94.892169 98.392169 102.284168 107.73016 111.23016 118.23016 121.73016 125.23016 135.33817 142.33817 152.44617 158.66217 165.66217 171.87818 176.54018 180.04018 183.54018 187.43218 194.43218 197.93218 203.37818 210.37818 221.27017 227.48618 230.98618 237.20218 244.20218 251.20218 255.09418 258.98619 265.20219 271.41819 275.31019 279.20219 286.20219 293.20219 298.6482 302.1482 305.6482 309.5402 313.4322 316.9322 327.8242 334.0402 341.0402 344.5402 351.5402 357.7562 361.2562 368.2562 374.4722 379.9182 383.8102 388.4722 394.6882 401.6882 405.5802 411.7962 415.2962 419.1882 426.1882 429.6882 435.9042 442.9042 449.1202 456.1202 460.0122 466.2282 469.7282 473.6202 480.6202">while C2[LP] bit is 1. However, in some applications, it may be desirable to enable the</tspan><tspan y="385.85" x=".00016000001 7.784161 16.338162 24.892163 28.392163 35.392164 40.05416 43.55416 51.33816 59.892164 68.44616 71.94616 78.16216 85.16216 92.16216 95.66216 101.87817 105.770168 109.66216 116.66216 126.770168 130.27017 134.16217 138.05417 141.55417 145.44617 152.44617 155.94617 159.83817 166.83817 173.05417 180.05417 183.55417 188.21617 195.21617 199.87818 203.37818 214.27017 220.48618 227.48618 231.37818 242.27017 249.27017 260.16218 263.66218 269.87818 276.09419 282.31019 289.31019 293.97218 300.18818 306.40419 313.40419 316.90419 323.90419 330.12019 334.78218 341.78218 346.44416 352.66017 356.16017 361.60618 371.71418 375.60618 379.49818 385.71418 392.71418 396.60618 403.60618 410.60618 414.10618 417.99818 424.99818 428.49818 434.71418 441.71418 445.21418 451.43019 458.43019 465.43019 471.64619 478.64619 484.86219">FLL or PLL and allow it to lock for maximum accuracy before switching to an engaged</tspan><tspan y="401.85" x=".00016000001 10.892161 17.892163 24.892163 31.108162 34.608163 38.108163 48.216165 55.216165 58.716165 62.608167 69.60817 73.50017 78.94617 82.44617 89.44617 96.44617 99.94617 110.05417 114.71617 118.60817 122.50017 126.392169 133.39217 140.39217 143.89217 153.23017 160.23017 164.89217 173.44617 181.23017 185.89217 189.39217 193.28417 200.28417 203.78417 210.78417">mode. Do this by writing C2[LP] to 0.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 496.4)" font-size="16" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.15625" x="-.00383 8.892171 17.788172 22.236172 31.132172 35.580175">25.4.3</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 112.65332 496.4)" font-size="16" font-family="HelveticaLTStd" font-weight="bold"><tspan y="12.15625" x="-.00383 13.324171 24.876172 37.324174 41.772176 46.220178 55.996179 61.324178 70.22018 76.444179 86.22018 95.11618 99.56418 104.01218 115.56418 124.46018 129.78818 138.68418 144.90818 153.80417 163.58017 172.47617 181.37216 185.82016 197.37216 201.82016 211.59616 220.49216 229.38816">MCG Internal Reference Clocks</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="478.65" x=".00418 8.55818 15.55818 19.45018 24.896182 28.396182 39.28818 46.28818 53.28818 60.28818 64.18018 70.39619 73.89619 79.342189 86.342189 93.342189 100.342189 107.342189 112.00419 115.89619 121.342189 124.842189 128.73419 138.8422 145.8422 149.3422 153.23419 160.23419 164.12619 170.3422 175.0042 182.0042 188.2202 192.1122 195.6122 200.2742 206.4902 211.1522 217.36821 222.03022 228.24622 235.24622 241.46222 247.67823 251.17823 257.39424 261.28623 268.28623 274.50224 281.50224 286.94825 290.44825 300.55625 304.44825 308.34025 315.34025 318.84025 325.84025 332.84025 343.73225 347.62425 354.62425 360.84025 364.73225 368.23225 372.89424 377.5562 383.77223 390.77223 397.77223 403.98823 410.98823 417.20423 421.09623 427.31224 432.75825 436.25825 443.25825 447.92024 451.42024 458.42024 465.42024 468.92024 475.92024 486.02824">This module supports two internal reference clocks with nominal frequencies of 32 kHz</tspan><tspan y="494.65" x=".0042100006 4.66621 10.112211 14.004211 21.004212 31.112214 34.612215 39.27421 48.612215 57.950216 62.612215 66.11221 72.32822 79.32822 86.32822 89.82822 96.82822 100.32822 112.774219 122.88222 129.09822 132.59822 137.26023 141.92223 148.13823 153.58423 157.47623 160.97623 165.63823 174.97623 184.31423 188.97623 192.47623 195.97623 204.53023 211.53023 217.74623 221.24623 225.90824 232.12424 237.57024 241.46224 244.96224 249.62424 258.96226 268.30027 271.80027 276.46226 281.12425 287.34025 294.34025 301.34025 307.55625 314.55625 320.77226 327.77226 331.27226 337.48826 343.70426 350.70426 354.20426 361.20426 367.42027 370.92027 377.92027 381.81227 388.81227 392.70426 399.70426 405.92027 412.92027 416.42027 423.42027 430.42027 440.52827 447.52827 451.02827 458.02827">(slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by</tspan><tspan y="510.65" x=".0042100006 7.00421 11.66621 18.66621 25.66621 30.32821 36.544214 47.436216 58.328218 62.22022 69.220218 76.220218 79.720218 86.720218 91.38222 94.88222 98.774219 105.774219 111.99022 115.49022 123.27422 132.61223 141.95023 152.05823 156.72023 166.82823 170.32823 174.22023 181.22023 184.72023 191.72023 196.38224 203.38224 210.38224 217.38224 223.59824 229.81424 233.31424 239.53025 243.03025 247.69225 252.35425 258.57026 265.57026 272.57026 278.78627 285.78627 292.00227 299.00227 302.50227 307.16426 313.38026 320.38026 327.38026 333.59626 337.09626 344.09626 348.75825 352.25825 359.25825 366.25825 369.75825 376.75825 386.86625 393.08226 396.58226 400.47425 407.47425 410.97425 417.97425 421.47425 433.92027 444.02827 450.24427">programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz.</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 605.2)" font-size="15" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.89648" x="-.00583 8.334171 16.674172 20.844172 29.184174 33.354177 41.694177 45.864179">25.4.3.1</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 122.3833 605.2)" font-size="15" font-family="HelveticaLTStd" font-weight="bold"><tspan y="11.89648" x="-.00583 12.489171 23.319172 34.989175 39.159177 43.329179 52.49418 57.489179 65.82918 71.66418 80.82918 89.16918 93.33918 97.50918 108.33918 116.679187 121.67419 130.01419 135.8492 144.1892 153.35419 161.69419 170.03418 174.20418 185.03418 189.20418 198.36917 206.70917">MCG Internal Reference Clock</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 54)" font-size="14" font-family="TimesLTStd"><tspan y="587.45" x="-.00483 8.54917 15.54917 21.765172 25.265172 37.711175 47.049177 57.157178 60.657178 65.319179 72.319179 76.211177 82.42718 87.08918 94.08918 100.30518 104.19718 107.69718 117.03519 123.25119 127.91319 134.1292 138.7912 145.0072 152.0072 158.2232 164.43921 167.93921 177.2772 181.1692 188.1692 194.38521 201.38521 204.88521 209.54721 221.99321 231.3312 241.43921 246.10121 255.43921 264.77723 273.3312 283.4392 288.1012 291.6012 298.6012 303.26319 310.26319 317.26319 321.15519 328.15519 334.3712 339.8172 343.3172 349.5332 353.0332 359.2492 363.1412 370.1412 376.3572 383.3572 386.8572 392.30323 399.30323 406.30323 410.9652 417.1812 423.39723 426.89723 431.5592 438.5592 443.2212 446.7212 453.7212 457.6132 464.6132 470.8292 475.49119 478.99119 485.99119 492.99119">The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other on-</tspan><tspan y="603.45" x="-.00482 6.2111809 13.211181 17.103182 24.103182 27.603182 34.60318 40.81918 45.48118 49.37318 56.37318 63.37318 69.58918 74.25118 80.467189 84.359188 89.80518 93.30518 99.52119 106.52119 113.52119 117.02119 120.913188 126.359188 129.85919 136.0752 143.0752 149.2912 156.2912 160.1832 166.3992 173.3992 176.8992 187.0072 194.0072 200.2232 207.2232 210.7232 220.0612 227.0612 231.7232 236.38521 245.7232 255.0612 263.6152 273.7232 282.2772 292.3852 297.04719 304.94319 311.94319 315.44319 318.94319 332.15919 339.15919 345.37519 352.37519 355.87519 362.0912 369.0912 375.3072 382.3072 386.1992 392.4152 399.4152 402.9152 406.4152 418.8612 428.19923 438.30723 442.9692 452.30723 461.64524 470.19923 480.30723 483.80723 487.69923">chip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is</tspan><tspan y="619.45" x="-.00482 6.99518 11.657181 15.549181 22.549181 28.765183 35.765184 39.265184 46.265184 53.265184 56.765184 62.981184 66.873188 70.76518 77.76518 83.981189 88.64319 92.14319 96.03519 103.03519 109.25119 112.75119 117.41319 123.629199 129.0752 132.9672 136.4672 140.35919 147.35919 151.25119 157.4672 162.1292 169.1292 175.3452 179.2372 182.7372 187.3992 193.6152 198.2772 204.49321 209.15522 215.37122 222.37122 228.58722 234.80323 238.30323 244.51923 248.41123 255.41123 261.62724 268.62724 272.12724 276.7892 283.7892 287.2892 299.73524 309.84324 316.05924 319.55924 324.22123 333.55924 342.89726 346.39726 356.50526 363.50526 367.39726 373.61326 380.61326 384.11326 390.32926 396.54527 403.54527 407.04527 414.04527 420.26127 423.76127 430.76127 434.65327 441.65327 445.54527 452.54527 458.76127 465.76127 469.26127 476.26127 483.26127 493.36927">driven by either the fast internal reference clock (4 MHz IRC which can be divided down</tspan><tspan y="635.45" x="-.00482 6.99518 13.99518 17.49518 21.38718 28.38718 34.60318 38.10318 45.88718 55.22518 65.33318 69.995189 80.10319 83.60319 88.26519 94.48119 100.6972 104.589199 111.589199 116.2512 121.6972 126.3592 129.85919 136.85919 141.5212 145.0212 148.9132 155.9132 162.1292 165.6292 171.0752 174.9672 181.9672 192.0752 195.5752 199.4672 206.4672 210.35919 216.5752 221.2372 228.2372 234.4532 238.3452 241.8452 246.5072 252.7232 257.3852 263.6012 268.26319 274.4792 281.4792 287.6952 293.9112 297.4112 303.6272 307.5192 314.5192 320.7352 327.7352 331.2352 335.8972 342.8972 349.8972 353.3972 360.3972 370.5052 376.7212 380.2212 384.88319 394.2212 403.5592 408.2212 411.7212 415.2212 423.77519 430.77519 436.99119 440.49119 445.15318 454.49119 463.8292">by the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS</tspan><tspan y="651.45" x="-.00482 6.2111809 10.103181 17.10318 23.31918 30.31918 33.81918 38.48118 43.143178 49.359178 56.359178 63.359178 69.57518 76.57518 82.79118 89.79118 93.29118 99.50719 105.72319 112.72319 116.22319 123.22319 129.4392 132.9392 137.6012 143.8172 148.4792 152.3712 158.5872 163.2492 170.2492 176.46521 180.35721 186.57321 193.57321 197.07321 204.07321 211.07321 214.57321 218.46521 223.12722 227.01921 237.91121 248.8032 252.6952 259.6952 266.6952 270.1952 274.0872 281.0872 287.3032 290.8032 297.8032 304.0192 308.68119 312.57319 319.57319 326.57319 330.07319 337.07319 341.73518 345.23518 349.12718 353.01918 358.46519 361.96519 366.62718 375.96519 385.3032 393.0872 396.5872 402.0332 408.2492 412.1412 418.3572 424.5732 428.4652 434.6812 441.6812 445.1812 449.0732 456.0732 459.9652 466.1812 470.8432 477.8432 484.0592">clock frequency can be re-targeted by trimming the period of its IRCS selected internal</tspan></text>
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<text xml:space="preserve" transform="matrix(1 0 0 1 54 18)" font-size="9" font-family="HelveticaLTStd" font-weight="bold"><tspan y="26.01031" x="296.469 302.96699 308.46598 313.46998 318.96897 321.96598 326.96998 330.47099 332.973 337.977 342.981 345.483 352.98 358.479 360.98103 363.97804 366.48005 371.97904 377.47804 380.97904 386.47804 391.97703 396.98103 401.98503 404.48704 410.98503 413.48704 418.98603 423.99003 428.99403 431.49604 438.49806 443.50205 449.00105 454.00505 457.50605 462.51005 465.50706 471.00605 474.50706 477.00907 480.00608 487.50309 494.00108 501.00309">Chapter 25 Multipurpose Clock Generator (MCG)</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 734.93869)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="130.01 137.23 142.79 148.34999 151.12999 157.79999 163.90999 170.01999 173.34999 179.45999 185.01999 193.90999 196.68999 199.46999 205.02999 207.80998 215.02999 220.58998 223.91999 229.47998 233.36998 238.92998 245.03998 250.59998 256.15998 258.93998 267.26997 272.82997 278.93995 285.04994 290.60993 293.38993 296.16993 298.94993 306.16993 311.72993 317.28993 320.06993 322.8499 328.4099 331.1899 336.7499 342.8599 348.96989 351.74989 357.30989 362.86988 368.42988">K60 Sub-Family Reference Manual, Rev. 2 Jun 2012</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 54 751.756)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x=".00401 5.5030105 8.5000109 13.504011 18.50801 23.00801 27.50801 32.512014 34.510015 39.514017 42.016016 48.019014 53.023015 60.520017 62.518018 67.01802 72.02202 77.02602 82.030017 87.03401 91.53401 94.03601 99.04001 102.03701 104.53901 107.04101 109.54301 114.547008 119.047008">Freescale Semiconductor, Inc.</tspan></text>
<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 220.32 751.756)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="58.45 65.12 69.01 74.57 77.35 80.13 89.02 91.799999 97.909999 103.46999 107.35999">Preliminary</tspan></text>
<text xml:space="preserve" transform="matrix(1 0 0 1 391.68 751.756)" font-size="9" font-family="HelveticaLTStd"><tspan y="7.83789" x="151.308 156.312 161.316">587</tspan></text>
<text fill="#ff0000" xml:space="preserve" transform="matrix(1 0 0 1 54 763.756)" font-size="10" font-family="HelveticaLTStd" font-weight="bold"><tspan y="8.59766" x="180.87 188.65 194.20999 200.31999 205.87999 209.76999 215.32999 218.10999 220.88999 228.10999 234.21999 239.77999 242.55998 248.66999 254.22998 259.78999 265.34999 268.12998 270.90998 277.01997 280.34996 286.45994 290.34996 299.23997 304.79997 308.12995 310.90995 317.01994">General Business Information</tspan></text>
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