606 lines
23 KiB
Python
Executable File
606 lines
23 KiB
Python
Executable File
#!/usr/bin/env python3
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import os
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from dataclasses import dataclass, field
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from typing import Any, List
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import yaml
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from graphviz import Graph
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COLOR_CODES = {
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'DIN': ['WH','BN','GN','YE','GY','PK','BU','RD','BK','VT'], # ,'GYPK','RDBU','WHGN','BNGN','WHYE','YEBN','WHGY','GYBN','WHPK','PKBN'],
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'IEC': ['BN','RD','OG','YE','GN','BU','VT','GY','WH','BK'],
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'BW': ['BK','WH']
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}
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color_hex = {
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'BK': '#000000',
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'WH': '#ffffff',
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'GY': '#999999',
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'PK': '#ff66cc',
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'RD': '#ff0000',
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'OG': '#ff8000',
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'YE': '#ffff00',
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'GN': '#00ff00',
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'TQ': '#00ffff',
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'BU': '#0066ff',
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'VT': '#8000ff',
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'BN': '#666600',
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}
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color_full = {
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'BK': 'black',
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'WH': 'white',
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'GY': 'grey',
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'PK': 'pink',
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'RD': 'red',
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'OG': 'orange',
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'YE': 'yellow',
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'GN': 'green',
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'TQ': 'turquoise',
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'BU': 'blue',
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'VT': 'violet',
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'BN': 'brown',
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}
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color_ger = {
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'BK': 'sw',
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'WH': 'ws',
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'GY': 'gr',
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'PK': 'rs',
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'RD': 'rt',
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'OG': 'or',
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'YE': 'ge',
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'GN': 'gn',
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'TQ': 'tk',
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'BU': 'bl',
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'VT': 'vi',
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'BN': 'br',
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}
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class Harness:
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def __init__(self):
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self.color_mode = 'SHORT'
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self.nodes = {}
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self.cables = {}
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def add_node(self, name, *args, **kwargs):
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self.nodes[name] = Node(name, *args, **kwargs)
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def add_cable(self, name, *args, **kwargs):
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self.cables[name] = Cable(name, *args, **kwargs)
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def loop(self, node_name, from_pin, to_pin):
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self.nodes[node_name].loop(from_pin, to_pin)
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def connect(self, from_name, from_pin, via_name, via_pin, to_name, to_pin):
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self.cables[via_name].connect(from_name, from_pin, via_pin, to_name, to_pin)
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def create_graph(self):
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dot = Graph()
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dot.body.append('// Graph generated by WireViz')
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dot.body.append('// https://github.com/formatc1702/WireViz')
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font = 'arial'
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dot.attr('graph', rankdir='LR',
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ranksep='2',
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bgcolor='white',
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nodesep='0.33',
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fontname=font)
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dot.attr('node', shape='record',
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style='filled',
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fillcolor='white',
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fontname=font)
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dot.attr('edge', style='bold',
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fontname=font)
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# prepare ports on connectors depending on which side they will connect
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for k, c in self.cables.items():
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for x in c.connections:
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if x.from_port is not None: # connect to left
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self.nodes[x.from_name].ports_right = True
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if x.to_port is not None: # connect to right
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self.nodes[x.to_name].ports_left = True
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for k, n in self.nodes.items():
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if n.category == 'ferrule':
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infostring = '{type} {color}'.format(type=n.type,
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color=translate_color(n.color, self.color_mode) if n.color else '')
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infostring_l = infostring if n.ports_right else ''
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infostring_r = infostring if n.ports_left else ''
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dot.node(k, shape='none',
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style='filled',
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margin='0',
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orientation = '0' if n.ports_left else '180',
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label='''<
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<TABLE BORDER="1" CELLBORDER="0" CELLSPACING="0" CELLPADDING="2"><TR>
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<TD PORT="p1l"> {infostring_l} </TD>
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{colorbar}
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<TD PORT="p1r"> {infostring_r} </TD>
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</TR></TABLE>
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>'''.format(infostring_l=infostring_l,
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infostring_r=infostring_r,
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colorbar='<TD BGCOLOR="{}" BORDER="1" SIDES="LR" WIDTH="4"></TD>'.format(translate_color(n.color, 'HEX')) if n.color else ''))
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# dot.node(k, label='{<p1l>A|B|{C|<p1r>D|E}}')
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else:
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# a = attributes
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a = [n.type,
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n.gender,
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'{}-pin'.format(len(n.pinout)) if n.show_num_pins else '']
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# p = pinout
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p = [[],[],[]]
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p[1] = list(n.pinout)
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for i, x in enumerate(n.pinout, 1):
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if n.ports_left:
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p[0].append('<p{portno}l>{portno}'.format(portno=i))
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if n.ports_right:
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p[2].append('<p{portno}r>{portno}'.format(portno=i))
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# l = label
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l = [n.name if n.show_name else '', a, p, n.notes]
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dot.node(k, label=nested(l))
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if len(n.loops) > 0:
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dot.attr('edge',color='#000000')
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if n.ports_left:
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loop_side = 'l'
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loop_dir = 'w'
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elif n.ports_right:
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loop_side = 'r'
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loop_dir = 'e'
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else:
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raise Exception('No side for loops')
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for loop in n.loops:
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dot.edge('{name}:p{port_from}{loop_side}:{loop_dir}'.format(name=n.name, port_from=loop[0], port_to=loop[1], loop_side=loop_side, loop_dir=loop_dir),
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'{name}:p{port_to}{loop_side}:{loop_dir}'.format(name=n.name, port_from=loop[0], port_to=loop[1], loop_side=loop_side, loop_dir=loop_dir))
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for k, c in self.cables.items():
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# a = attributes
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a = ['{}x'.format(len(c.colors)) if c.show_num_wires else '',
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'{} mm\u00B2{}'.format(c.mm2, ' ({} AWG)'.format(awg_equiv(c.mm2)) if c.show_equiv else '') if c.mm2 is not None else '',
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'{} AWG'.format(c.awg) if c.awg else '',
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'+ S' if c.shield else '',
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'{} m'.format(c.length) if c.length > 0 else '']
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# print(a)
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a = list(filter(None, a))
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# print(a)
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html = '<table border="0" cellspacing="0" cellpadding="0"><tr><td>' # main table
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html = html + '<table border="0" cellspacing="0" cellpadding="3" cellborder="1">' # name+attributes table
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if (not c.show_name) or c.type != 'bundle':
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html = html + '<tr><td colspan="{colspan}">{name}</td></tr>'.format(colspan=len(a), name=c.name)
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html = html + '<tr>' # attribute row
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for attrib in a:
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html = html + '<td>{attrib}</td>'.format(attrib=attrib)
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html = html + '</tr>' # attribute row
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html = html + '</table></td></tr>' # name+attributes table
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html = html + '<tr><td> </td></tr>' # spacer between attributes and wires
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html = html + '<tr><td><table border="0" cellspacing="0" cellborder="0">' # conductor table
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for i, x in enumerate(c.colors,1):
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p = []
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p.append('<!-- {}_in -->'.format(i))
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p.append(translate_color(x, self.color_mode))
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p.append('<!-- {}_out -->'.format(i))
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html = html + '<tr>'
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for bla in p:
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html = html + '<td>{}</td>'.format(bla)
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html = html + '</tr>'
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html = html + '<tr><td colspan="{colspan}" cellpadding="0" height="6" bgcolor="{bgcolor}" border="2" sides="tb" port="{port}"></td></tr>'.format(colspan=len(p), bgcolor=translate_color(x, 'hex'), port='w{}'.format(i))
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if c.shield:
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p = ['<!-- s_in -->', 'Shield', '<!-- s_out -->']
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html = html + '<tr><td> </td></tr>' # spacer
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html = html + '<tr>'
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for bla in p:
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html = html + '<td>{}</td>'.format(bla)
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html = html + '</tr>'
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html = html + '<tr><td colspan="{colspan}" cellpadding="0" height="6" border="2" sides="b" port="{port}"></td></tr>'.format(colspan=len(p), bgcolor=translate_color(x, 'hex'), port='ws')
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html = html + '<tr><td> </td></tr>' # spacer at the end
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html = html + '</table>' # conductor table
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html = html + '</td></tr>' # main table
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if c.notes:
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html = html + '<tr><td cellpadding="3">{}</td></tr>'.format(c.notes) # notes table
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html = html + '<tr><td> </td></tr>' # spacer at the end
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# html = html + '<tr><td> </td></tr>' # spacer at the end
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html = html + '</table>' # main table
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# print(html)
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# connections
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for x in c.connections:
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if isinstance(x.via_port, int): # check if it's an actual wire and not a shield
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search_color = c.colors[x.via_port-1]
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if search_color in color_hex:
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dot.attr('edge',color='#000000:{wire_color}:#000000'.format(wire_color=color_hex[search_color]))
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else: # color name not found
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dot.attr('edge',color='#000000')
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else: # it's a shield connection
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dot.attr('edge',color='#000000')
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if x.from_port is not None: # connect to left
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from_ferrule = self.nodes[x.from_name].category is 'ferrule'
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code_left_1 = '{from_name}{from_port}:e'.format(from_name=x.from_name, from_port=':p{}r'.format(x.from_port) if not from_ferrule else '')
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code_left_2 = '{via_name}:w{via_wire}:w'.format(via_name=c.name, via_wire=x.via_port, via_subport='i' if c.show_pinout else '')
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dot.edge(code_left_1, code_left_2)
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from_string = '{}:{}'.format(x.from_name, x.from_port) if not from_ferrule else ''
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html = html.replace('<!-- {}_in -->'.format(x.via_port), from_string)
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if x.to_port is not None: # connect to right
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to_ferrule = self.nodes[x.to_name].category is 'ferrule'
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code_right_1 = '{via_name}:w{via_wire}:e'.format(via_name=c.name, via_wire=x.via_port, via_subport='o' if c.show_pinout else '')
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code_right_2 = '{to_name}{to_port}:w'.format(to_name=x.to_name, to_port=':p{}l'.format(x.to_port) if not to_ferrule else '')
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dot.edge(code_right_1, code_right_2)
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to_string = '{}:{}'.format(x.to_name, x.to_port) if not to_ferrule else ''
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html = html.replace('<!-- {}_out -->'.format(x.via_port), to_string)
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dot.node(c.name, label='<{html}>'.format(html=html), shape='box', style='filled,dashed' if c.type=='bundle' else '', margin='0', fillcolor='white')
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return dot
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def output(self, filename, directory='_output', view=False, cleanup=True, format='pdf'):
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d = self.create_graph()
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for f in format:
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d.format = f
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d.render(filename=filename, directory=directory, view=view, cleanup=cleanup)
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d.save(filename='{}.gv'.format(filename), directory=directory)
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@dataclass
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class Node:
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name: str
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category: str = None
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type: str = None
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gender: str = None
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num_pins: int = None
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notes: str = None
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pinout: List[Any] = field(default_factory=list)
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color: str = None
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show_name: bool = True
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show_num_pins: bool = True
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def __post_init__(self):
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self.ports_left = False
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self.ports_right = False
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self.loops = []
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if self.pinout:
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if self.num_pins is not None:
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raise Exception('You cannot specify both pinout and num_pins')
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else:
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if not self.num_pins:
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self.num_pins = 1
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self.pinout = ['',] * self.num_pins
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def loop(self, from_pin, to_pin):
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self.loops.append((from_pin, to_pin))
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@dataclass
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class Cable:
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name: str
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type: str = None
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mm2: float = None
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awg: int = None
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show_equiv: bool = False
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length: float = 0
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num_wires: int = None
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shield: bool = False
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notes: str = None
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colors: List[Any] = field(default_factory=list)
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color_code: str = None
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show_name: bool = True
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show_pinout: bool = False
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show_num_wires: bool = True
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def __post_init__(self):
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if self.mm2 and self.awg:
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raise Exception('You cannot define both mm2 and awg!')
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self.connections = []
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if self.num_wires: # number of wires explicitly defined
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if self.colors: # use custom color palette (partly or looped if needed)
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pass
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elif self.color_code: # use standard color palette (partly or looped if needed)
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if self.color_code not in COLOR_CODES:
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raise Exception('Unknown color code')
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self.colors = COLOR_CODES[self.color_code]
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else: # no colors defined, add dummy colors
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self.colors = [''] * self.num_wires
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# make color code loop around if more wires than colors
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if self.num_wires > len(self.colors):
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m = self.num_wires // len(self.colors) + 1
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self.colors = self.colors * int(m)
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# cut off excess after looping
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self.colors = self.colors[:self.num_wires]
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else: # num_wires implicit in length of color list
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if not self.colors:
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raise Exception('Unknown number of wires. Must specify num_wires or colors (implicit length)')
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self.num_wires = len(self.colors)
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def connect(self, from_name, from_pin, via_pin, to_name, to_pin):
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from_pin = int2tuple(from_pin)
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via_pin = int2tuple(via_pin)
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to_pin = int2tuple(to_pin)
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if len(from_pin) != len(to_pin):
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raise Exception('from_pin must have the same number of elements as to_pin')
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for i, x in enumerate(from_pin):
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# self.connections.append((from_name, from_pin[i], via_pin[i], to_name, to_pin[i]))
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self.connections.append(Connection(from_name, from_pin[i], via_pin[i], to_name, to_pin[i]))
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@dataclass
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class Connection:
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from_name: Any
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from_port: Any
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via_port: Any
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to_name: Any
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to_port: Any
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def nested(input):
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l = []
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for x in input:
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if isinstance(x, list):
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if len(x) > 0:
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n = nested(x)
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if n != '':
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l.append('{' + n + '}')
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else:
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if x is not None:
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if x != '':
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l.append(str(x))
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s = '|'.join(l)
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return s
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def int2tuple(input):
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if isinstance(input, tuple):
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output = input
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else:
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output = (input,)
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return output
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def translate_color(input, color_mode):
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if input == '':
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output = ''
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else:
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if color_mode == 'full':
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output = color_full[input].lower()
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elif color_mode == 'FULL':
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output = color_full[input].upper()
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elif color_mode == 'hex':
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output = color_hex[input].lower()
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elif color_mode == 'HEX':
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output = color_hex[input].upper()
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elif color_mode == 'ger':
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output = color_ger[input].lower()
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elif color_mode == 'GER':
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output = color_ger[input].upper()
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elif color_mode == 'short':
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output = input.lower()
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elif color_mode == 'SHORT':
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output = input.upper()
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else:
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raise Exception('Unknown color mode')
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return output
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def awg_equiv(mm2):
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awg_equiv_table = {
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'0.09': 28,
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'0.14': 26,
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'0.25': 24,
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'0.34': 22,
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'0.5': 21,
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'0.75': 20,
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'1': 18,
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'1.5': 16,
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'2.5': 14,
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'4': 12,
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'6': 10,
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'10': 8,
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'16': 6,
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'25': 4,
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}
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k = str(mm2)
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if k in awg_equiv_table:
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return awg_equiv_table[k]
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else:
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return None
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def parse(file_in, file_out=None):
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file_in = os.path.abspath(file_in)
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if not file_out:
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file_out = file_in
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pre, ext = os.path.splitext(file_out)
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file_out = pre # extension will be added by graphviz output function
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file_out = os.path.abspath(file_out)
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with open(file_in, 'r') as stream:
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try:
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input = yaml.safe_load(stream)
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except yaml.YAMLError as exc:
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print(exc)
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def expand(input):
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# input can be:
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# - a singleton (normally str or int)
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# - a list of str or int
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# if str is of the format '#-#', it is treated as a range (inclusive) and expanded
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output = []
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if not isinstance(input, list):
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input = [input,]
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for e in input:
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e = str(e)
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if '-' in e: # list of pins
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a, b = tuple(map(int, e.split('-')))
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if a < b:
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for x in range(a,b+1):
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output.append(x)
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elif a > b:
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for x in range(a,b-1,-1):
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output.append(x)
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elif a == b:
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output.append(a)
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else:
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try:
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x = int(e)
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except:
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x = e
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output.append(x)
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return output
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def check_designators(what, where):
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for i, x in enumerate(what):
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# print('Looking for {} in {}'.format(x,where[i]))
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if x not in input[where[i]]:
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return False
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return True
|
|
|
|
h = Harness()
|
|
|
|
# add items
|
|
sections = ['nodes','wires','ferrules','connections']
|
|
types = [dict, dict, dict, list]
|
|
for sec, ty in zip(sections, types):
|
|
if sec in input and type(input[sec]) == ty:
|
|
if len(input[sec]) > 0:
|
|
if ty == dict:
|
|
for k, o in input[sec].items():
|
|
if sec == 'nodes':
|
|
h.add_node(name=k, **o)
|
|
elif sec == 'wires':
|
|
h.add_cable(name=k, **o)
|
|
elif sec == 'ferrules':
|
|
pass
|
|
# h.add_node(name=k, category='ferrule', **o)
|
|
else:
|
|
print('{} section empty'.format(sec))
|
|
else:
|
|
print('No {} section found'.format(sec))
|
|
if ty == dict:
|
|
input[sec] = {}
|
|
elif ty == list:
|
|
input[sec] = []
|
|
|
|
# add connections
|
|
ferrule_counter = 0
|
|
for con in input['connections']:
|
|
if len(con) == 3: # format: connector -- wire -- conector
|
|
|
|
for c in con:
|
|
if len(list(c.keys())) != 1: # check that each entry in con has only one key, which is the designator
|
|
raise Exception('Too many keys')
|
|
|
|
from_name = list(con[0].keys())[0]
|
|
via_name = list(con[1].keys())[0]
|
|
to_name = list(con[2].keys())[0]
|
|
|
|
if not check_designators([from_name,via_name,to_name],('nodes','wires','nodes')):
|
|
raise Exception('Bad connection definition (3)')
|
|
|
|
from_pins = expand(con[0][from_name])
|
|
via_pins = expand(con[1][via_name])
|
|
to_pins = expand(con[2][to_name])
|
|
|
|
if len(from_pins) != len(via_pins) or len(via_pins) != len(to_pins):
|
|
raise Exception('List length mismatch')
|
|
|
|
for (from_pin, via_pin, to_pin) in zip(from_pins, via_pins, to_pins):
|
|
h.connect(from_name, from_pin, via_name, via_pin, to_name, to_pin)
|
|
|
|
elif len(con) == 2:
|
|
|
|
for c in con:
|
|
if type(c) is dict:
|
|
if len(list(c.keys())) != 1: # check that each entry in con has only one key, which is the designator
|
|
raise Exception('Too many keys')
|
|
|
|
# hack to make the format for ferrules compatible with the formats for connectors and wires
|
|
if type(con[0]) == str:
|
|
name = con[0]
|
|
con[0] = {}
|
|
con[0][name] = name
|
|
if type(con[1]) == str:
|
|
name = con[1]
|
|
con[1] = {}
|
|
con[1][name] = name
|
|
|
|
from_name = list(con[0].keys())[0]
|
|
to_name = list(con[1].keys())[0]
|
|
|
|
n_w = check_designators([from_name, to_name],('nodes','wires'))
|
|
w_n = check_designators([from_name, to_name],('wires','nodes'))
|
|
n_n = check_designators([from_name, to_name],('nodes','nodes'))
|
|
|
|
|
|
f_w = check_designators([from_name, to_name],('ferrules','wires'))
|
|
w_f = check_designators([from_name, to_name],('wires','ferrules'))
|
|
|
|
if not n_w and not w_n and not n_n and not f_w and not w_f:
|
|
raise Exception('Wrong designators')
|
|
|
|
from_pins = expand(con[0][from_name])
|
|
to_pins = expand(con[1][to_name])
|
|
|
|
if n_w or w_n or n_n:
|
|
if len(from_pins) != len(to_pins):
|
|
raise Exception('List length mismatch')
|
|
|
|
if n_w or w_n:
|
|
for (from_pin, to_pin) in zip(from_pins, to_pins):
|
|
if n_w:
|
|
h.connect(from_name, from_pin, to_name, to_pin, None, None)
|
|
else: # w_n
|
|
h.connect(None, None, from_name, from_pin, to_name, to_pin)
|
|
elif n_n:
|
|
con_name = list(con[0].keys())[0]
|
|
from_pins = expand(con[0][from_name])
|
|
to_pins = expand(con[1][to_name])
|
|
|
|
for (from_pin, to_pin) in zip(from_pins, to_pins):
|
|
h.loop(con_name, from_pin, to_pin)
|
|
if f_w or w_f:
|
|
from_pins = expand(con[0][from_name])
|
|
to_pins = expand(con[1][to_name])
|
|
|
|
if f_w:
|
|
ferrule_name = from_name
|
|
wire_name = to_name
|
|
wire_pins = to_pins
|
|
else:
|
|
ferrule_name = to_name
|
|
wire_name = from_name
|
|
wire_pins = from_pins
|
|
|
|
ferrule_params = input['ferrules'][ferrule_name]
|
|
for wire_pin in wire_pins:
|
|
ferrule_counter = ferrule_counter + 1
|
|
ferrule_id = 'F{}'.format(ferrule_counter)
|
|
h.add_node(ferrule_id, category='ferrule', **ferrule_params)
|
|
|
|
if f_w:
|
|
h.connect(ferrule_id, 1, wire_name, wire_pin, None, None)
|
|
else:
|
|
h.connect(None, None, wire_name, wire_pin, ferrule_id, 1)
|
|
|
|
|
|
else:
|
|
raise Exception('Wrong number of connection parameters')
|
|
|
|
h.output(filename=file_out, format=('png','svg'), view=False)
|
|
|
|
if __name__ == '__main__':
|
|
import argparse
|
|
ap = argparse.ArgumentParser()
|
|
ap.add_argument('file_input', nargs='?', default='_test/test.yml')
|
|
ap.add_argument('file_output', nargs='?', default=None)
|
|
args = ap.parse_args()
|
|
|
|
parse(args.file_input, args.file_output)
|