warehack.ing/WireViz
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Loop index by name, add loop_color to Connector

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This commit is contained in:
Visa Tuominen 2022-08-08 14:11:10 +03:00
parent a6efd28124
commit e6dc146882
2 changed files with 11 additions and 3 deletions
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1
src/wireviz/DataClasses.py
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@ -142,6 +142,7 @@ class Connector:
hide_disconnected_pins: bool = False hide_disconnected_pins: bool = False
autogenerate: bool = False autogenerate: bool = False
loops: List[List[Pin]] = field(default_factory=list) loops: List[List[Pin]] = field(default_factory=list)
loop_color: Optional[Color] = "WH"
ignore_in_bom: bool = False ignore_in_bom: bool = False
additional_components: List[AdditionalComponent] = field(default_factory=list) additional_components: List[AdditionalComponent] = field(default_factory=list)

13
src/wireviz/Harness.py
View File

@ -178,7 +178,8 @@ class Harness:
fillcolor=translate_color(self.options.bgcolor_connector, "HEX")) fillcolor=translate_color(self.options.bgcolor_connector, "HEX"))
if len(connector.loops) > 0: if len(connector.loops) > 0:
dot.attr('edge', color='#000000:#ffffff:#000000') loop_color_hex = translate_color(connector.loop_color, "hex")
dot.attr('edge', color=f'#000000:{loop_color_hex}:#000000')
if connector.ports_left: if connector.ports_left:
loop_side = 'l' loop_side = 'l'
loop_dir = 'w' loop_dir = 'w'
@ -188,8 +189,14 @@ class Harness:
else: else:
raise Exception('No side for loops') raise Exception('No side for loops')
for loop in connector.loops: for loop in connector.loops:
dot.edge(f'{connector.name}:p{loop[0]}{loop_side}:{loop_dir}', if type(loop[0]) == str:
f'{connector.name}:p{loop[1]}{loop_side}:{loop_dir}') i_loop_0 = connector.pins.index(loop[0])
i_loop_1 = connector.pins.index(loop[1])
else:
i_loop_0 = loop[0]
i_loop_1 = loop[1]
dot.edge(f'{connector.name}:p{i_loop_0}{loop_side}:{loop_dir}',
f'{connector.name}:p{i_loop_1}{loop_side}:{loop_dir}')
# determine if there are double- or triple-colored wires in the harness; # determine if there are double- or triple-colored wires in the harness;