Improve shield wiring, fix and expand example 1
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34
src/test.py
34
src/test.py
@ -8,12 +8,16 @@ COLORS_I2C = ('BK', 'RD', 'YE', 'GN')
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PINOUT_SPI_DATAONLY = ('MISO','MOSI','SCK')
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# example 1
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# X1 = wireviz.Node("X1", pinout=PINOUT_SERIAL, ports_right=True)
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# X2 = wireviz.Node("X2", num_pins=6, ports_left=True)
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# W1 = wireviz.Cable("W1", show_name=True, num_wires=3, color_code="DIN", shield=True)
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# W1.connect(X1,(2,3,5),(1,2,3),X2,(1,3,2))
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# X2.loop(5,6)
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# objects = [X1, X2, W1]
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X1 = wireviz.Node("X1", pinout=PINOUT_SERIAL, ports_right=True)
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X2 = wireviz.Node("X2", num_pins=6, ports_left=True)
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W1 = wireviz.Cable("W1", show_name=True, num_wires=3, color_code="DIN", shield=True)
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# Option 1: define wires and shield in one line
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# W1.connect(X1,(5,2,3,5),(1,2,3,'s'),X2,(1,3,2,None))
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# Option 2: define wires and shield separately
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W1.connect(X1,(5,2,3),'auto',X2,(1,3,2)) # wires
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W1.connect(X1,(5,),('s',),X2,(None,)) # shield
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X2.loop(5,6)
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objects = [X1, X2, W1]
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# example 2
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# X1 = wireviz.Node("X1", pinout=(
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@ -41,15 +45,15 @@ PINOUT_SPI_DATAONLY = ('MISO','MOSI','SCK')
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# objects = [X1, X2, X3, X4, X5, W1, W2, W3, W4]
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# example 3
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X1 = wireviz.Node("X1", num_pins=10, ports_right=True)
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X2 = wireviz.Node("X2", num_pins=10, ports_left=True)
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W1 = wireviz.Cable("W1", num_wires=10, color_code="IEC")
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W1.connect_all_straight(X1,X2)
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X3 = wireviz.Node("X3", num_pins=10, ports_right=True)
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X4 = wireviz.Node("X4", num_pins=10, ports_left=True)
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W2 = wireviz.Cable("W2", num_wires=10, color_code="DIN")
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W2.connect_all_straight(X3,X4)
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objects = [X1, X2, W1, X3, X4, W2]
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# X1 = wireviz.Node("X1", num_pins=10, ports_right=True)
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# X2 = wireviz.Node("X2", num_pins=10, ports_left=True)
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# W1 = wireviz.Cable("W1", num_wires=10, color_code="IEC")
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# W1.connect_all_straight(X1,X2)
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# X3 = wireviz.Node("X3", num_pins=10, ports_right=True)
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# X4 = wireviz.Node("X4", num_pins=10, ports_left=True)
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# W2 = wireviz.Cable("W2", num_wires=10, color_code="DIN")
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# W2.connect_all_straight(X3,X4)
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# objects = [X1, X2, W1, X3, X4, W2]
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with open('output/output.dot','w') as f:
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with open('input/header.dot','r') as infile:
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@ -93,6 +93,7 @@ class Cable:
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def __init__(self, name, show_name=False, num_wires=None, colors=None, color_code=None, shield=False):
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self.name = name
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self.show_name = show_name
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self.shield = shield
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self.connections = []
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if color_code is None and colors is None:
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self.colors = ("",) * num_wires
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@ -113,8 +114,8 @@ class Cable:
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self.colors = colors
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else:
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self.colors = colors[:num_wires]
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if shield == True:
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self.colors = self.colors + ('Shield',)
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# if shield == True:
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# self.colors = self.colors + ('Shield',)
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def connect(self, from_name, from_pin, via, to_name, to_pin):
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if from_pin == 'auto':
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@ -161,10 +162,14 @@ class Cable:
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for i,x in enumerate(self.colors,1):
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l.append('<w{wireno}i>{wireno}'.format(wireno=i))
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s = s + '|'.join(l)
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if self.shield == True:
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s = s + '|<wsi>'
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s = s + '} | '
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s = s + '{'
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s = s + '|'.join(self.colors)
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if self.shield == True:
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s = s + '|Shield'
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s = s + '}'
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s = s + ' | {'
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@ -172,6 +177,8 @@ class Cable:
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for i,x in enumerate(self.colors,1):
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l.append('<w{wireno}o>{wireno}'.format(wireno=i))
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s = s + '|'.join(l)
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if self.shield == True:
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s = s + '|<wso>'
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s = s + '}'
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s = s + '}}"]'
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@ -179,11 +186,16 @@ class Cable:
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s = s + '\n\n{edge[style=bold]\n'
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for x in self.connections:
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s = s + '{'
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search_color = self.colors[x[2]-1]
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if search_color in color_dict:
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s = s + 'edge[color="#000000:{wire_color}:#000000"] '.format(wire_color=color_dict[search_color])
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t = '{from_name}:p{from_port} -> {via_name}:w{via_wire}i; {via_name}:w{via_wire}o -> {to_name}:p{to_port}'.format(from_name=x[0],from_port=x[1],via_name=self.name, via_wire=x[2],to_name=x[3],to_port=x[4])
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s = s + t
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if isinstance(x[2], int):
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search_color = self.colors[x[2]-1]
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if search_color in color_dict:
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s = s + 'edge[color="#000000:{wire_color}:#000000"] '.format(wire_color=color_dict[search_color])
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if x[1] is not None:
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t = '{from_name}:p{from_port} -> {via_name}:w{via_wire}i; '.format(from_name=x[0],from_port=x[1],via_name=self.name, via_wire=x[2])
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s = s + t
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if x[4] is not None:
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t = '{via_name}:w{via_wire}o -> {to_name}:p{to_port}'.format(via_name=self.name, via_wire=x[2],to_name=x[3],to_port=x[4])
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s = s + t
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s = s + '}\n'
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s = s + '}'
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