Improve shield wiring, fix and expand example 1

This commit is contained in:
Daniel Rojas 2020-05-22 14:28:54 +02:00
parent a198d27a26
commit d42b12fd0f
2 changed files with 38 additions and 22 deletions

View File

@ -8,12 +8,16 @@ COLORS_I2C = ('BK', 'RD', 'YE', 'GN')
PINOUT_SPI_DATAONLY = ('MISO','MOSI','SCK')
# example 1
# X1 = wireviz.Node("X1", pinout=PINOUT_SERIAL, ports_right=True)
# X2 = wireviz.Node("X2", num_pins=6, ports_left=True)
# W1 = wireviz.Cable("W1", show_name=True, num_wires=3, color_code="DIN", shield=True)
# W1.connect(X1,(2,3,5),(1,2,3),X2,(1,3,2))
# X2.loop(5,6)
# objects = [X1, X2, W1]
X1 = wireviz.Node("X1", pinout=PINOUT_SERIAL, ports_right=True)
X2 = wireviz.Node("X2", num_pins=6, ports_left=True)
W1 = wireviz.Cable("W1", show_name=True, num_wires=3, color_code="DIN", shield=True)
# Option 1: define wires and shield in one line
# W1.connect(X1,(5,2,3,5),(1,2,3,'s'),X2,(1,3,2,None))
# Option 2: define wires and shield separately
W1.connect(X1,(5,2,3),'auto',X2,(1,3,2)) # wires
W1.connect(X1,(5,),('s',),X2,(None,)) # shield
X2.loop(5,6)
objects = [X1, X2, W1]
# example 2
# X1 = wireviz.Node("X1", pinout=(
@ -41,15 +45,15 @@ PINOUT_SPI_DATAONLY = ('MISO','MOSI','SCK')
# objects = [X1, X2, X3, X4, X5, W1, W2, W3, W4]
# example 3
X1 = wireviz.Node("X1", num_pins=10, ports_right=True)
X2 = wireviz.Node("X2", num_pins=10, ports_left=True)
W1 = wireviz.Cable("W1", num_wires=10, color_code="IEC")
W1.connect_all_straight(X1,X2)
X3 = wireviz.Node("X3", num_pins=10, ports_right=True)
X4 = wireviz.Node("X4", num_pins=10, ports_left=True)
W2 = wireviz.Cable("W2", num_wires=10, color_code="DIN")
W2.connect_all_straight(X3,X4)
objects = [X1, X2, W1, X3, X4, W2]
# X1 = wireviz.Node("X1", num_pins=10, ports_right=True)
# X2 = wireviz.Node("X2", num_pins=10, ports_left=True)
# W1 = wireviz.Cable("W1", num_wires=10, color_code="IEC")
# W1.connect_all_straight(X1,X2)
# X3 = wireviz.Node("X3", num_pins=10, ports_right=True)
# X4 = wireviz.Node("X4", num_pins=10, ports_left=True)
# W2 = wireviz.Cable("W2", num_wires=10, color_code="DIN")
# W2.connect_all_straight(X3,X4)
# objects = [X1, X2, W1, X3, X4, W2]
with open('output/output.dot','w') as f:
with open('input/header.dot','r') as infile:

View File

@ -93,6 +93,7 @@ class Cable:
def __init__(self, name, show_name=False, num_wires=None, colors=None, color_code=None, shield=False):
self.name = name
self.show_name = show_name
self.shield = shield
self.connections = []
if color_code is None and colors is None:
self.colors = ("",) * num_wires
@ -113,8 +114,8 @@ class Cable:
self.colors = colors
else:
self.colors = colors[:num_wires]
if shield == True:
self.colors = self.colors + ('Shield',)
# if shield == True:
# self.colors = self.colors + ('Shield',)
def connect(self, from_name, from_pin, via, to_name, to_pin):
if from_pin == 'auto':
@ -161,10 +162,14 @@ class Cable:
for i,x in enumerate(self.colors,1):
l.append('<w{wireno}i>{wireno}'.format(wireno=i))
s = s + '|'.join(l)
if self.shield == True:
s = s + '|<wsi>'
s = s + '} | '
s = s + '{'
s = s + '|'.join(self.colors)
if self.shield == True:
s = s + '|Shield'
s = s + '}'
s = s + ' | {'
@ -172,6 +177,8 @@ class Cable:
for i,x in enumerate(self.colors,1):
l.append('<w{wireno}o>{wireno}'.format(wireno=i))
s = s + '|'.join(l)
if self.shield == True:
s = s + '|<wso>'
s = s + '}'
s = s + '}}"]'
@ -179,11 +186,16 @@ class Cable:
s = s + '\n\n{edge[style=bold]\n'
for x in self.connections:
s = s + '{'
search_color = self.colors[x[2]-1]
if search_color in color_dict:
s = s + 'edge[color="#000000:{wire_color}:#000000"] '.format(wire_color=color_dict[search_color])
t = '{from_name}:p{from_port} -> {via_name}:w{via_wire}i; {via_name}:w{via_wire}o -> {to_name}:p{to_port}'.format(from_name=x[0],from_port=x[1],via_name=self.name, via_wire=x[2],to_name=x[3],to_port=x[4])
s = s + t
if isinstance(x[2], int):
search_color = self.colors[x[2]-1]
if search_color in color_dict:
s = s + 'edge[color="#000000:{wire_color}:#000000"] '.format(wire_color=color_dict[search_color])
if x[1] is not None:
t = '{from_name}:p{from_port} -> {via_name}:w{via_wire}i; '.format(from_name=x[0],from_port=x[1],via_name=self.name, via_wire=x[2])
s = s + t
if x[4] is not None:
t = '{via_name}:w{via_wire}o -> {to_name}:p{to_port}'.format(via_name=self.name, via_wire=x[2],to_name=x[3],to_port=x[4])
s = s + t
s = s + '}\n'
s = s + '}'