From 504399c62e0a8ff950c5e3704f8a901906844ba8 Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 22 May 2020 21:26:18 +0200 Subject: [PATCH 1/4] =?UTF-8?q?Fix=20UTF=20encoding=20for=20=C2=B2=20chara?= =?UTF-8?q?cter?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/wireviz.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/wireviz.py b/src/wireviz.py index 511bfa6..0f7f81a 100644 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -223,7 +223,7 @@ class Cable: if self.mm2 is not None: e = awg_equiv(self.mm2) es = ' ({} AWG)'.format(e) if e is not None else '' - mm ='{} mm²{}'.format(self.mm2, es) + mm ='{} mm\u00B2{}'.format(self.mm2, es) l.append(mm) if self.awg is not None: l.append('{} AWG'.format(self.awg)) From db73fa5c817c54538425bb7d25b5a41f4c7796bc Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 22 May 2020 21:26:41 +0200 Subject: [PATCH 2/4] Expand DIN 47100 colors (up to 20 wires) --- src/example3.py | 6 +++--- src/wireviz.py | 3 ++- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/example3.py b/src/example3.py index b0f75d0..25af45e 100644 --- a/src/example3.py +++ b/src/example3.py @@ -8,9 +8,9 @@ Harness.add(Node('X2', num_pins=10, ports_left=True)) Harness.add(Cable('W1', num_wires=10, color_code='IEC')) Harness.objects['W1'].connect_all_straight('X1','X2') -Harness.add(Node('X3', num_pins=12, ports_right=True)) -Harness.add(Node('X4', num_pins=12, ports_left=True)) -Harness.add(Cable('W2', num_wires=12, color_code='DIN')) +Harness.add(Node('X3', num_pins=20, ports_right=True)) +Harness.add(Node('X4', num_pins=20, ports_left=True)) +Harness.add(Cable('W2', num_wires=20, color_code='DIN')) Harness.objects['W2'].connect_all_straight('X3','X4') Harness.add(Node('X5', num_pins=20, ports_right=True)) diff --git a/src/wireviz.py b/src/wireviz.py index 0f7f81a..636ab93 100644 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -1,8 +1,9 @@ -COLOR_CODES = {'DIN': ['WH','BN','GN','YE','GY','PK','BU','RD','BK','VT'], +COLOR_CODES = {'DIN': ['WH','BN','GN','YE','GY','PK','BU','RD','BK','VT','GYPK','RDBU','WHGN','BNGN','WHYE','YEBN','WHGY','GYBN','WHPK','PKBN'], 'IEC': ['BN','RD','OG','YE','GN','BU','VT','GY','WH','BK'], 'BW': ['BK','WH']} +# TODO: parse and render double-colored cables ('RDBU' etc) color_hex = { 'BK': '#000000', 'WH': '#ffffff', From ff94b475c496e3c4aaafa71aa82b9ac14a6b556a Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 22 May 2020 21:34:37 +0200 Subject: [PATCH 3/4] Make output background color transparent --- src/input/header.dot | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/input/header.dot b/src/input/header.dot index e8b319b..86c0d19 100644 --- a/src/input/header.dot +++ b/src/input/header.dot @@ -3,6 +3,6 @@ // Daniel Rojas - 2020 graph G { - graph [rankdir = LR, ranksep=2, fontname = "arial"]; - edge [fontname = "arial"]; - node [shape=record, style=rounded, fontname = "arial"]; + graph [rankdir = "LR", ranksep=2, fontname = "arial", bgcolor="transparent"] + edge [fontname = "arial"] + node [shape="record", style="rounded,filled", fontname = "arial", fillcolor="white"] From 5278904234ee844e229c5d77b24242194a02ef64 Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Sat, 23 May 2020 20:15:31 +0200 Subject: [PATCH 4/4] Update readme --- readme.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/readme.md b/readme.md index 7cc8375..45f2743 100644 --- a/readme.md +++ b/readme.md @@ -2,7 +2,7 @@ ## Summary -WireViz is a simple yet flexible markup language for documenting wires and connector pinouts with beautiful graphical output. +WireViz is a simple yet flexible markup language for documenting cables, wiring harnesses and connector pinouts with beautiful graphical output. It is based on [GraphViz](https://www.graphviz.org/) and designed as an "extension" of it. A parser reads a WireViz file and generates valid GraphViz output, which can instantly be rendered to SVG/PNG. @@ -93,11 +93,11 @@ GraphViz code generated by parser: ## Status -This is very much a work in progress, and mainly an idea in my head. -A Python module and test scripts is available. Running the test script will generate GraphViz output. +This is very much a work in progress. +A Python module and test scripts are available. Running the test script will generate GraphViz output. The parser will follow later; contributions are welcome! -# To do +## To do * Automate creation of left/right side ports for connectors * Add simple connectors (ferrules, cable lugs)