diff --git a/examples/demo01.gv b/examples/demo01.gv index c23e536..24abe51 100644 --- a/examples/demo01.gv +++ b/examples/demo01.gv @@ -1,23 +1,21 @@ graph { // Graph generated by WireViz // https://github.com/formatc1702/WireViz - graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + graph [bgcolor=white fontname=arial nodesep=0.33 rankdir=LR ranksep=2] node [fillcolor=white fontname=arial shape=record style=filled] edge [fontname=arial style=bold] X1 [label="X1|{D-Sub|female|9-pin}|{{DCD|RX|TX|DTR|GND|DSR|RTS|CTS|RI}|{1|2|3|4|5|6|7|8|9}}"] - X2 [label="X2|{Molex KK 254|female|6-pin}|{{1|2|3|4|5|6}|{GND|RX|TX|N/C|OUT|IN}}"] - edge [color="#000000"] - X2:p5l:w -- X2:p6l:w - W1 [label="W1|{3x|0.25 mm²|+ S|0.2 m}|{{WH|BN|GN|Shield}}"] + X2 [label="X2|{Molex KK 254|female|3-pin}|{{1|2|3}|{GND|RX|TX}}"] edge [color="#000000:#ffffff:#000000"] - X1:p5r -- W1:w1 - W1:w1 -- X2:p1l + X1:p5r:e -- W1:w1:w + W1:w1:e -- X2:p1l:w edge [color="#000000:#666600:#000000"] - X1:p2r -- W1:w2 - W1:w2 -- X2:p3l + X1:p2r:e -- W1:w2:w + W1:w2:e -- X2:p3l:w edge [color="#000000:#00ff00:#000000"] - X1:p1r -- W1:w3 - W1:w3 -- X2:p2l + X1:p1r:e -- W1:w3:w + W1:w3:e -- X2:p2l:w edge [color="#000000"] - X1:p5r -- W1:ws + X1:p5r:e -- W1:ws:w + W1 [label=<
W1
3x0.25 mm²+ S0.2 m
 
X1:5WHX2:1
X1:2BNX2:3
X1:1GNX2:2
 
X1:5Shield
 
> fillcolor=white margin=0 shape=box style=""] } diff --git a/examples/demo01.png b/examples/demo01.png index 2d74b55..6e56db1 100644 Binary files a/examples/demo01.png and b/examples/demo01.png differ diff --git a/examples/demo01.svg b/examples/demo01.svg index 7615ca0..bc7b2f9 100644 --- a/examples/demo01.svg +++ b/examples/demo01.svg @@ -4,9 +4,10 @@ - - + + + X1 @@ -58,112 +59,112 @@ W1 - -W1 - -3x - -0.25 mm² - -+ S - -0.2 m - -WH - -BN - -GN - -Shield + + +W1 + +3x + +0.25 mm² + ++ S + +0.2 m +  +X1:5 +WH +X2:1 + + + +X1:2 +BN +X2:3 + + + +X1:1 +GN +X2:2 + + + +  +X1:5 +Shield + +  - -X1:p5r--W1:w1 - - - + +X1:e--W1:w + + + - -X1:p2r--W1:w2 - - - + +X1:e--W1:w + + + - -X1:p1r--W1:w3 - - - + +X1:e--W1:w + + + - -X1:p5r--W1:ws - + +X1:e--W1:w + X2 - -X2 - -Molex KK 254 - -female - -6-pin - -1 - -2 - -3 - -4 - -5 - -6 - -GND - -RX - -TX - -N/C - -OUT - -IN - - - -X2:w--X2:w - + +X2 + +Molex KK 254 + +female + +3-pin + +1 + +2 + +3 + +GND + +RX + +TX - -W1:w1--X2:p1l - - - + +W1:e--X2:w + + + - -W1:w2--X2:p3l - - - + +W1:e--X2:w + + + - -W1:w3--X2:p2l - - - + +W1:e--X2:w + + + diff --git a/examples/demo01.yml b/examples/demo01.yml index 7398666..6538d3d 100644 --- a/examples/demo01.yml +++ b/examples/demo01.yml @@ -6,7 +6,7 @@ nodes: X2: type: Molex KK 254 gender: female - pinout: [GND, RX, TX, N/C, OUT, IN] + pinout: [GND, RX, TX] wires: W1: @@ -17,13 +17,10 @@ wires: shield: true connections: - - # format: connector->wire->connector + - - X1: [5,2,1] - W1: [1,2,3] - X2: [1,3,2] - - # format: connector->wire or wire->connector + - - X1: 5 - W1: s - - # loop: connector-connector - - X2: 5 - - X2: 6 diff --git a/examples/demo02.gv b/examples/demo02.gv index 5dbe6b5..04af751 100644 --- a/examples/demo02.gv +++ b/examples/demo02.gv @@ -1,7 +1,7 @@ graph { // Graph generated by WireViz // https://github.com/formatc1702/WireViz - graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + graph [bgcolor=white fontname=arial nodesep=0.33 rankdir=LR ranksep=2] node [fillcolor=white fontname=arial shape=record style=filled] edge [fontname=arial style=bold] X1 [label="X1|{Molex KK 254|female|8-pin}|{{GND|+5V|SCL|SDA|MISO|MOSI|SCK|N/C}|{1|2|3|4|5|6|7|8}}"] @@ -9,108 +9,50 @@ graph { X3 [label="X3|{Molex KK 254|female|4-pin}|{{1|2|3|4}|{GND|+5V|SCL|SDA}}"] X4 [label="X4|{Molex KK 254|female|5-pin}|{{1|2|3|4|5}|{GND|+12V|MISO|MOSI|SCK}}"] X5 [label="X5|{Molex Micro-Fit|male|2-pin}|{{GND|+12V}|{1|2}}"] - subgraph cluster_W1 { - graph [fillcolor=white label="4x | 0.14 mm² (26 AWG) | 0.2 m - " style="filled, dashed"] - node [fixedsize=true height=0 label="" shape=point width=0] - W1_w1l - W1_w1r - W1_w2l - W1_w2r - W1_w3l - W1_w3r - W1_w4l - W1_w4r - } edge [color="#000000:#000000:#000000"] - W1_w1l -- W1_w1r [labelangle=60 labeldist=0 taillabel=" BK"] - X1:p1r -- W1_w1l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] - W1_w1r:e -- X2:p1l [labelangle=60 labeldist=0 taillabel="X2:1 "] + X1:p1r:e -- W1:w1:w + W1:w1:e -- X2:p1l:w edge [color="#000000:#ff0000:#000000"] - W1_w2l -- W1_w2r [labelangle=60 labeldist=0 taillabel=" RD"] - X1:p2r -- W1_w2l:w [headlabel=" X1:2" labelangle=-60 labeldist=0] - W1_w2r:e -- X2:p2l [labelangle=60 labeldist=0 taillabel="X2:2 "] + X1:p2r:e -- W1:w2:w + W1:w2:e -- X2:p2l:w edge [color="#000000:#ffff00:#000000"] - W1_w3l -- W1_w3r [labelangle=60 labeldist=0 taillabel=" YE"] - X1:p3r -- W1_w3l:w [headlabel=" X1:3" labelangle=-60 labeldist=0] - W1_w3r:e -- X2:p3l [labelangle=60 labeldist=0 taillabel="X2:3 "] + X1:p3r:e -- W1:w3:w + W1:w3:e -- X2:p3l:w edge [color="#000000:#00ff00:#000000"] - W1_w4l -- W1_w4r [labelangle=60 labeldist=0 taillabel=" GN"] - X1:p4r -- W1_w4l:w [headlabel=" X1:4" labelangle=-60 labeldist=0] - W1_w4r:e -- X2:p4l [labelangle=60 labeldist=0 taillabel="X2:4 "] - subgraph cluster_W2 { - graph [fillcolor=white label="4x | 0.14 mm² (26 AWG) | 0.2 m - " style="filled, dashed"] - node [fixedsize=true height=0 label="" shape=point width=0] - W2_w1l - W2_w1r - W2_w2l - W2_w2r - W2_w3l - W2_w3r - W2_w4l - W2_w4r - } + X1:p4r:e -- W1:w4:w + W1:w4:e -- X2:p4l:w + W1 [label=<
4x0.14 mm² (26 AWG)0.2 m
 
X1:1BKX2:1
X1:2RDX2:2
X1:3YEX2:3
X1:4GNX2:4
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] edge [color="#000000:#000000:#000000"] - W2_w1l -- W2_w1r [labelangle=60 labeldist=0 taillabel=" BK"] - X1:p1r -- W2_w1l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] - W2_w1r:e -- X3:p1l [labelangle=60 labeldist=0 taillabel="X3:1 "] + X1:p1r:e -- W2:w1:w + W2:w1:e -- X3:p1l:w edge [color="#000000:#ff0000:#000000"] - W2_w2l -- W2_w2r [labelangle=60 labeldist=0 taillabel=" RD"] - X1:p2r -- W2_w2l:w [headlabel=" X1:2" labelangle=-60 labeldist=0] - W2_w2r:e -- X3:p2l [labelangle=60 labeldist=0 taillabel="X3:2 "] + X1:p2r:e -- W2:w2:w + W2:w2:e -- X3:p2l:w edge [color="#000000:#ffff00:#000000"] - W2_w3l -- W2_w3r [labelangle=60 labeldist=0 taillabel=" YE"] - X1:p3r -- W2_w3l:w [headlabel=" X1:3" labelangle=-60 labeldist=0] - W2_w3r:e -- X3:p3l [labelangle=60 labeldist=0 taillabel="X3:3 "] + X1:p3r:e -- W2:w3:w + W2:w3:e -- X3:p3l:w edge [color="#000000:#00ff00:#000000"] - W2_w4l -- W2_w4r [labelangle=60 labeldist=0 taillabel=" GN"] - X1:p4r -- W2_w4l:w [headlabel=" X1:4" labelangle=-60 labeldist=0] - W2_w4r:e -- X3:p4l [labelangle=60 labeldist=0 taillabel="X3:4 "] - subgraph cluster_W3 { - graph [fillcolor=white label="4x | 0.14 mm² (26 AWG) | 0.2 m - " style="filled, dashed"] - node [fixedsize=true height=0 label="" shape=point width=0] - W3_w1l - W3_w1r - W3_w2l - W3_w2r - W3_w3l - W3_w3r - W3_w4l - W3_w4r - } + X1:p4r:e -- W2:w4:w + W2:w4:e -- X3:p4l:w + W2 [label=<
4x0.14 mm² (26 AWG)0.2 m
 
X1:1BKX3:1
X1:2RDX3:2
X1:3YEX3:3
X1:4GNX3:4
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] edge [color="#000000:#000000:#000000"] - W3_w1l -- W3_w1r [labelangle=60 labeldist=0 taillabel=" BK"] - X1:p1r -- W3_w1l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] - W3_w1r:e -- X4:p1l [labelangle=60 labeldist=0 taillabel="X4:1 "] + X1:p1r:e -- W3:w1:w + W3:w1:e -- X4:p1l:w edge [color="#000000:#0066ff:#000000"] - W3_w2l -- W3_w2r [labelangle=60 labeldist=0 taillabel=" BU"] - X1:p5r -- W3_w2l:w [headlabel=" X1:5" labelangle=-60 labeldist=0] - W3_w2r:e -- X4:p3l [labelangle=60 labeldist=0 taillabel="X4:3 "] + X1:p5r:e -- W3:w2:w + W3:w2:e -- X4:p3l:w edge [color="#000000:#ff8000:#000000"] - W3_w3l -- W3_w3r [labelangle=60 labeldist=0 taillabel=" OG"] - X1:p6r -- W3_w3l:w [headlabel=" X1:6" labelangle=-60 labeldist=0] - W3_w3r:e -- X4:p4l [labelangle=60 labeldist=0 taillabel="X4:4 "] + X1:p6r:e -- W3:w3:w + W3:w3:e -- X4:p4l:w edge [color="#000000:#8000ff:#000000"] - W3_w4l -- W3_w4r [labelangle=60 labeldist=0 taillabel=" VT"] - X1:p7r -- W3_w4l:w [headlabel=" X1:7" labelangle=-60 labeldist=0] - W3_w4r:e -- X4:p5l [labelangle=60 labeldist=0 taillabel="X4:5 "] - subgraph cluster_W4 { - graph [fillcolor=white label="2x | 0.5 mm² (21 AWG) | 0.35 m - " style="filled, dashed"] - node [fixedsize=true height=0 label="" shape=point width=0] - W4_w1l - W4_w1r - W4_w2l - W4_w2r - } + X1:p7r:e -- W3:w4:w + W3:w4:e -- X4:p5l:w + W3 [label=<
4x0.14 mm² (26 AWG)0.2 m
 
X1:1BKX4:1
X1:5BUX4:3
X1:6OGX4:4
X1:7VTX4:5
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] edge [color="#000000:#000000:#000000"] - W4_w1l -- W4_w1r [labelangle=60 labeldist=0 taillabel=" BK"] - X5:p1r -- W4_w1l:w [headlabel=" X5:1" labelangle=-60 labeldist=0] - W4_w1r:e -- X4:p1l [labelangle=60 labeldist=0 taillabel="X4:1 "] + X5:p1r:e -- W4:w1:w + W4:w1:e -- X4:p1l:w edge [color="#000000:#ff0000:#000000"] - W4_w2l -- W4_w2r [labelangle=60 labeldist=0 taillabel=" RD"] - X5:p2r -- W4_w2l:w [headlabel=" X5:2" labelangle=-60 labeldist=0] - W4_w2r:e -- X4:p2l [labelangle=60 labeldist=0 taillabel="X4:2 "] + X5:p2r:e -- W4:w2:w + W4:w2:e -- X4:p2l:w + W4 [label=<
2x0.5 mm² (21 AWG)0.35 m
 
X5:1BKX4:1
X5:2RDX4:2
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] } diff --git a/examples/demo02.png b/examples/demo02.png index 0572b16..53e7923 100644 Binary files a/examples/demo02.png and b/examples/demo02.png differ diff --git a/examples/demo02.svg b/examples/demo02.svg index 7f2532c..9c32c7f 100644 --- a/examples/demo02.svg +++ b/examples/demo02.svg @@ -4,660 +4,493 @@ - - - -cluster_W1 - -4x  |  0.14 mm² (26 AWG)  |  0.2 m - - - -cluster_W2 - -4x  |  0.14 mm² (26 AWG)  |  0.2 m - - - -cluster_W3 - -4x  |  0.14 mm² (26 AWG)  |  0.2 m - - - -cluster_W4 - -2x  |  0.5 mm² (21 AWG)  |  0.35 m - - + + + X1 - -X1 - -Molex KK 254 - -female - -8-pin - -GND - -+5V - -SCL - -SDA - -MISO - -MOSI - -SCK - -N/C - -1 - -2 - -3 - -4 - -5 - -6 - -7 - -8 + +X1 + +Molex KK 254 + +female + +8-pin + +GND + ++5V + +SCL + +SDA + +MISO + +MOSI + +SCK + +N/C + +1 + +2 + +3 + +4 + +5 + +6 + +7 + +8 - + -W1_w1l - +W1 + + +4x + +0.14 mm² (26 AWG) + +0.2 m +  +X1:1 +BK +X2:1 + + + +X1:2 +RD +X2:2 + + + +X1:3 +YE +X2:3 + + + +X1:4 +GN +X2:4 + + + +  - - -X1:p1r--W1_w1l:w - - - -            X1:1 + + +X1:e--W1:w + + + - - -W1_w2l - + + +X1:e--W1:w + + + - + -X1:p2r--W1_w2l:w - - - -            X1:2 +X1:e--W1:w + + + - - -W1_w3l - + + +X1:e--W1:w + + + - - -X1:p3r--W1_w3l:w - - - -            X1:3 + + +W2 + + +4x + +0.14 mm² (26 AWG) + +0.2 m +  +X1:1 +BK +X3:1 + + + +X1:2 +RD +X3:2 + + + +X1:3 +YE +X3:3 + + + +X1:4 +GN +X3:4 + + + +  - - -W1_w4l - + + +X1:e--W2:w + + + - + -X1:p4r--W1_w4l:w - - - -            X1:4 +X1:e--W2:w + + + - - -W2_w1l - + + +X1:e--W2:w + + + - - -X1:p1r--W2_w1l:w - - - -            X1:1 + + +X1:e--W2:w + + + - - -W2_w2l - + + +W3 + + +4x + +0.14 mm² (26 AWG) + +0.2 m +  +X1:1 +BK +X4:1 + + + +X1:5 +BU +X4:3 + + + +X1:6 +OG +X4:4 + + + +X1:7 +VT +X4:5 + + + +  - + -X1:p2r--W2_w2l:w - - - -            X1:2 +X1:e--W3:w + + + - - -W2_w3l - + + +X1:e--W3:w + + + - - -X1:p3r--W2_w3l:w - - - -            X1:3 + + +X1:e--W3:w + + + - - -W2_w4l - - - + -X1:p4r--W2_w4l:w - - - -            X1:4 - - - -W3_w1l - - - - -X1:p1r--W3_w1l:w - - - -            X1:1 - - - -W3_w2l - - - - -X1:p5r--W3_w2l:w - - - -            X1:5 - - - -W3_w3l - - - - -X1:p6r--W3_w3l:w - - - -            X1:6 - - - -W3_w4l - - - - -X1:p7r--W3_w4l:w - - - -            X1:7 +X1:e--W3:w + + + X2 - -X2 - -Molex KK 254 - -female - -4-pin - -1 - -2 - -3 - -4 - -GND - -+5V - -SCL - -SDA + +X2 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + ++5V + +SCL + +SDA X3 - -X3 - -Molex KK 254 - -female - -4-pin - -1 - -2 - -3 - -4 - -GND - -+5V - -SCL - -SDA + +X3 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + ++5V + +SCL + +SDA X4 - -X4 - -Molex KK 254 - -female - -5-pin - -1 - -2 - -3 - -4 - -5 - -GND - -+12V - -MISO - -MOSI - -SCK + +X4 + +Molex KK 254 + +female + +5-pin + +1 + +2 + +3 + +4 + +5 + +GND + ++12V + +MISO + +MOSI + +SCK X5 - -X5 - -Molex Micro-Fit - -male - -2-pin - -GND - -+12V - -1 - -2 + +X5 + +Molex Micro-Fit + +male + +2-pin + +GND + ++12V + +1 + +2 - - -W4_w1l - - - - -X5:p1r--W4_w1l:w - - - -            X5:1 - - - -W4_w2l - - - - -X5:p2r--W4_w2l:w - - - -            X5:2 - - - -W1_w1r - - - - -W1_w1l--W1_w1r - - - -                                   BK - - - -W1_w1r:e--X2:p1l - - - -X2:1             - - + -W1_w2r - +W4 + + +2x + +0.5 mm² (21 AWG) + +0.35 m +  +X5:1 +BK +X4:1 + + + +X5:2 +RD +X4:2 + + + +  - - -W1_w2l--W1_w2r - - - -                                   RD - - - -W1_w2r:e--X2:p2l - - - -X2:2             - - - -W1_w3r - - - - -W1_w3l--W1_w3r - - - -                                   YE - - - -W1_w3r:e--X2:p3l - - - -X2:3             - - - -W1_w4r - - - - -W1_w4l--W1_w4r - - - -                                   GN - - - -W1_w4r:e--X2:p4l - - - -X2:4             - - - -W2_w1r - - - - -W2_w1l--W2_w1r - - - -                                   BK - - - -W2_w1r:e--X3:p1l - - - -X3:1             - - - -W2_w2r - - - - -W2_w2l--W2_w2r - - - -                                   RD - - - -W2_w2r:e--X3:p2l - - - -X3:2             - - - -W2_w3r - - - - -W2_w3l--W2_w3r - - - -                                   YE - - - -W2_w3r:e--X3:p3l - - - -X3:3             - - - -W2_w4r - - - - -W2_w4l--W2_w4r - - - -                                   GN - - - -W2_w4r:e--X3:p4l - - - -X3:4             - - - -W3_w1r - - - + -W3_w1l--W3_w1r - - - -                                   BK +X5:e--W4:w + + + - + -W3_w1r:e--X4:p1l - - - -X4:1             +X5:e--W4:w + + + - - -W3_w2r - + + +W1:e--X2:w + + + - + + +W1:e--X2:w + + + + + + +W1:e--X2:w + + + + + + +W1:e--X2:w + + + + + + +W2:e--X3:w + + + + + + +W2:e--X3:w + + + + + + +W2:e--X3:w + + + + + + +W2:e--X3:w + + + + + + +W3:e--X4:w + + + + + + +W3:e--X4:w + + + + + + +W3:e--X4:w + + + + + + +W3:e--X4:w + + + + + + +W4:e--X4:w + + + + + -W3_w2l--W3_w2r - - - -                                   BU - - - -W3_w2r:e--X4:p3l - - - -X4:3             - - - -W3_w3r - - - - -W3_w3l--W3_w3r - - - -                                   OG - - - -W3_w3r:e--X4:p4l - - - -X4:4             - - - -W3_w4r - - - - -W3_w4l--W3_w4r - - - -                                   VT - - - -W3_w4r:e--X4:p5l - - - -X4:5             - - - -W4_w1r - - - - -W4_w1l--W4_w1r - - - -                                   BK - - - -W4_w1r:e--X4:p1l - - - -X4:1             - - - -W4_w2r - - - - -W4_w2l--W4_w2r - - - -                                   RD - - - -W4_w2r:e--X4:p2l - - - -X4:2             +W4:e--X4:w + + + diff --git a/examples/ex01.gv b/examples/ex01.gv index 4010c31..eda6ecc 100644 --- a/examples/ex01.gv +++ b/examples/ex01.gv @@ -1,24 +1,24 @@ graph { // Graph generated by WireViz // https://github.com/formatc1702/WireViz - graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + graph [bgcolor=white fontname=arial nodesep=0.33 rankdir=LR ranksep=2] node [fillcolor=white fontname=arial shape=record style=filled] edge [fontname=arial style=bold] X1 [label="X1|{Molex KK 254|female|4-pin}|{{GND|VCC|RX|TX}|{1|2|3|4}}"] X2 [label="X2|{Molex KK 254|female|4-pin}|{{1|2|3|4}|{GND|VCC|RX|TX}}"] - W1 [label="W1|{4x|0.25 mm² (24 AWG)|+ S|0.2 m}|{{BN|RD|OG|YE|Shield}}"] edge [color="#000000:#666600:#000000"] - X1:p1r -- W1:w1 - W1:w1 -- X2:p1l + X1:p1r:e -- W1:w1:w + W1:w1:e -- X2:p1l:w edge [color="#000000:#ff0000:#000000"] - X1:p2r -- W1:w2 - W1:w2 -- X2:p2l + X1:p2r:e -- W1:w2:w + W1:w2:e -- X2:p2l:w edge [color="#000000:#ff8000:#000000"] - X1:p3r -- W1:w3 - W1:w3 -- X2:p4l + X1:p3r:e -- W1:w3:w + W1:w3:e -- X2:p4l:w edge [color="#000000:#ffff00:#000000"] - X1:p4r -- W1:w4 - W1:w4 -- X2:p3l + X1:p4r:e -- W1:w4:w + W1:w4:e -- X2:p3l:w edge [color="#000000"] - X1:p1r -- W1:ws + X1:p1r:e -- W1:ws:w + W1 [label=<
W1
4x0.25 mm² (24 AWG)+ S0.2 m
 
X1:1BNX2:1
X1:2RDX2:2
X1:3OGX2:4
X1:4YEX2:3
 
X1:1Shield
 
> fillcolor=white margin=0 shape=box style=""] } diff --git a/examples/ex01.png b/examples/ex01.png index f5b828e..935b484 100644 Binary files a/examples/ex01.png and b/examples/ex01.png differ diff --git a/examples/ex01.svg b/examples/ex01.svg index 0a90308..a22e320 100644 --- a/examples/ex01.svg +++ b/examples/ex01.svg @@ -4,149 +4,171 @@ - - + + + X1 - -X1 - -Molex KK 254 - -female - -4-pin - -GND - -VCC - -RX - -TX - -1 - -2 - -3 - -4 + +X1 + +Molex KK 254 + +female + +4-pin + +GND + +VCC + +RX + +TX + +1 + +2 + +3 + +4 W1 - -W1 - -4x - -0.25 mm² (24 AWG) - -+ S - -0.2 m - -BN - -RD - -OG - -YE - -Shield + + +W1 + +4x + +0.25 mm² (24 AWG) + ++ S + +0.2 m +  +X1:1 +BN +X2:1 + + + +X1:2 +RD +X2:2 + + + +X1:3 +OG +X2:4 + + + +X1:4 +YE +X2:3 + + + +  +X1:1 +Shield + +  -X1:p1r--W1:w1 - - - +X1:e--W1:w + + + -X1:p2r--W1:w2 - - - +X1:e--W1:w + + + -X1:p3r--W1:w3 - - - +X1:e--W1:w + + + -X1:p4r--W1:w4 - - - +X1:e--W1:w + + + -X1:p1r--W1:ws - +X1:e--W1:w + X2 - -X2 - -Molex KK 254 - -female - -4-pin - -1 - -2 - -3 - -4 - -GND - -VCC - -RX - -TX + +X2 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + +VCC + +RX + +TX -W1:w1--X2:p1l - - - +W1:e--X2:w + + + -W1:w2--X2:p2l - - - +W1:e--X2:w + + + -W1:w3--X2:p4l - - - +W1:e--X2:w + + + -W1:w4--X2:p3l - - - +W1:e--X2:w + + + diff --git a/examples/ex02.gv b/examples/ex02.gv index 7ba74d2..b914864 100644 --- a/examples/ex02.gv +++ b/examples/ex02.gv @@ -1,32 +1,32 @@ graph { // Graph generated by WireViz // https://github.com/formatc1702/WireViz - graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + graph [bgcolor=white fontname=arial nodesep=0.33 rankdir=LR ranksep=2] node [fillcolor=white fontname=arial shape=record style=filled] edge [fontname=arial style=bold] X1 [label="X1|{Molex Micro-Fit|male|2-pin}|{{GND|VCC}|{1|2}}"] X2 [label="X2|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] X3 [label="X3|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] X4 [label="X4|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] - W1 [label="W1|{2x|0.25 mm² (24 AWG)|0.2 m}|{{BK|RD}}"] edge [color="#000000:#000000:#000000"] - X1:p1r -- W1:w1 - W1:w1 -- X2:p1l + X1:p1r:e -- W1:w1:w + W1:w1:e -- X2:p1l:w edge [color="#000000:#ff0000:#000000"] - X1:p2r -- W1:w2 - W1:w2 -- X2:p2l - W2 [label="W2|{2x|0.25 mm² (24 AWG)|0.2 m}|{{BK|RD}}"] + X1:p2r:e -- W1:w2:w + W1:w2:e -- X2:p2l:w + W1 [label=<
W1
2x0.25 mm² (24 AWG)0.2 m
 
X1:1BKX2:1
X1:2RDX2:2
 
> fillcolor=white margin=0 shape=box style=""] edge [color="#000000:#000000:#000000"] - X1:p1r -- W2:w1 - W2:w1 -- X3:p1l + X1:p1r:e -- W2:w1:w + W2:w1:e -- X3:p1l:w edge [color="#000000:#ff0000:#000000"] - X1:p2r -- W2:w2 - W2:w2 -- X3:p2l - W3 [label="W3|{2x|0.25 mm² (24 AWG)|0.2 m}|{{BK|RD}}"] + X1:p2r:e -- W2:w2:w + W2:w2:e -- X3:p2l:w + W2 [label=<
W2
2x0.25 mm² (24 AWG)0.2 m
 
X1:1BKX3:1
X1:2RDX3:2
 
> fillcolor=white margin=0 shape=box style=""] edge [color="#000000:#000000:#000000"] - X1:p1r -- W3:w1 - W3:w1 -- X4:p1l + X1:p1r:e -- W3:w1:w + W3:w1:e -- X4:p1l:w edge [color="#000000:#ff0000:#000000"] - X1:p2r -- W3:w2 - W3:w2 -- X4:p2l + X1:p2r:e -- W3:w2:w + W3:w2:e -- X4:p2l:w + W3 [label=<
W3
2x0.25 mm² (24 AWG)0.2 m
 
X1:1BKX4:1
X1:2RDX4:2
 
> fillcolor=white margin=0 shape=box style=""] } diff --git a/examples/ex02.png b/examples/ex02.png index a617ee4..7dbb395 100644 Binary files a/examples/ex02.png and b/examples/ex02.png differ diff --git a/examples/ex02.svg b/examples/ex02.svg index 6e335d2..6ddeb7b 100644 --- a/examples/ex02.svg +++ b/examples/ex02.svg @@ -4,220 +4,254 @@ - - + + + X1 - -X1 - -Molex Micro-Fit - -male - -2-pin - -GND - -VCC - -1 - -2 + +X1 + +Molex Micro-Fit + +male + +2-pin + +GND + +VCC + +1 + +2 W1 - -W1 - -2x - -0.25 mm² (24 AWG) - -0.2 m - -BK - -RD + + +W1 + +2x + +0.25 mm² (24 AWG) + +0.2 m +  +X1:1 +BK +X2:1 + + + +X1:2 +RD +X2:2 + + + +  -X1:p1r--W1:w1 - - - +X1:e--W1:w + + + -X1:p2r--W1:w2 - - - +X1:e--W1:w + + + W2 - -W2 - -2x - -0.25 mm² (24 AWG) - -0.2 m - -BK - -RD + + +W2 + +2x + +0.25 mm² (24 AWG) + +0.2 m +  +X1:1 +BK +X3:1 + + + +X1:2 +RD +X3:2 + + + +  -X1:p1r--W2:w1 - - - +X1:e--W2:w + + + -X1:p2r--W2:w2 - - - +X1:e--W2:w + + + W3 - -W3 - -2x - -0.25 mm² (24 AWG) - -0.2 m - -BK - -RD + + +W3 + +2x + +0.25 mm² (24 AWG) + +0.2 m +  +X1:1 +BK +X4:1 + + + +X1:2 +RD +X4:2 + + + +  -X1:p1r--W3:w1 - - - +X1:e--W3:w + + + -X1:p2r--W3:w2 - - - +X1:e--W3:w + + + X2 - -X2 - -Molex Micro-Fit - -female - -2-pin - -1 - -2 - -GND - -VCC + +X2 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC X3 - -X3 - -Molex Micro-Fit - -female - -2-pin - -1 - -2 - -GND - -VCC + +X3 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC X4 - -X4 - -Molex Micro-Fit - -female - -2-pin - -1 - -2 - -GND - -VCC + +X4 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC -W1:w1--X2:p1l - - - +W1:e--X2:w + + + -W1:w2--X2:p2l - - - +W1:e--X2:w + + + -W2:w1--X3:p1l - - - +W2:e--X3:w + + + -W2:w2--X3:p2l - - - +W2:e--X3:w + + + -W3:w1--X4:p1l - - - +W3:e--X4:w + + + -W3:w2--X4:p2l - - - +W3:e--X4:w + + + diff --git a/examples/ex03.gv b/examples/ex03.gv index 810d334..dbad2f8 100644 --- a/examples/ex03.gv +++ b/examples/ex03.gv @@ -1,52 +1,30 @@ graph { // Graph generated by WireViz // https://github.com/formatc1702/WireViz - graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + graph [bgcolor=white fontname=arial nodesep=0.33 rankdir=LR ranksep=2] node [fillcolor=white fontname=arial shape=record style=filled] edge [fontname=arial style=bold] X1 [label="X1|{Molex Micro-Fit|male|2-pin}|{{GND|VCC}|{1|2}}"] X2 [label="X2|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] X3 [label="X3|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] X4 [label="X4|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] - subgraph cluster_W1 { - graph [fillcolor=white label="6x | 0.25 mm² (24 AWG) | 0.2 m - " style="filled, dashed"] - node [fixedsize=true height=0 label="" shape=point width=0] - W1_w1l - W1_w1r - W1_w2l - W1_w2r - W1_w3l - W1_w3r - W1_w4l - W1_w4r - W1_w5l - W1_w5r - W1_w6l - W1_w6r - } edge [color="#000000:#000000:#000000"] - W1_w1l -- W1_w1r [labelangle=60 labeldist=0 taillabel=" BK"] - X1:p1r -- W1_w1l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] - W1_w1r:e -- X2:p1l [labelangle=60 labeldist=0 taillabel="X2:1 "] + X1:p1r:e -- W1:w1:w + W1:w1:e -- X2:p1l:w edge [color="#000000:#ff0000:#000000"] - W1_w2l -- W1_w2r [labelangle=60 labeldist=0 taillabel=" RD"] - X1:p2r -- W1_w2l:w [headlabel=" X1:2" labelangle=-60 labeldist=0] - W1_w2r:e -- X2:p2l [labelangle=60 labeldist=0 taillabel="X2:2 "] + X1:p2r:e -- W1:w2:w + W1:w2:e -- X2:p2l:w edge [color="#000000:#000000:#000000"] - W1_w3l -- W1_w3r [labelangle=60 labeldist=0 taillabel=" BK"] - X1:p1r -- W1_w3l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] - W1_w3r:e -- X3:p1l [labelangle=60 labeldist=0 taillabel="X3:1 "] + X1:p1r:e -- W1:w3:w + W1:w3:e -- X3:p1l:w edge [color="#000000:#ff0000:#000000"] - W1_w4l -- W1_w4r [labelangle=60 labeldist=0 taillabel=" RD"] - X1:p2r -- W1_w4l:w [headlabel=" X1:2" labelangle=-60 labeldist=0] - W1_w4r:e -- X3:p2l [labelangle=60 labeldist=0 taillabel="X3:2 "] + X1:p2r:e -- W1:w4:w + W1:w4:e -- X3:p2l:w edge [color="#000000:#000000:#000000"] - W1_w5l -- W1_w5r [labelangle=60 labeldist=0 taillabel=" BK"] - X1:p1r -- W1_w5l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] - W1_w5r:e -- X4:p1l [labelangle=60 labeldist=0 taillabel="X4:1 "] + X1:p1r:e -- W1:w5:w + W1:w5:e -- X4:p1l:w edge [color="#000000:#ff0000:#000000"] - W1_w6l -- W1_w6r [labelangle=60 labeldist=0 taillabel=" RD"] - X1:p2r -- W1_w6l:w [headlabel=" X1:2" labelangle=-60 labeldist=0] - W1_w6r:e -- X4:p2l [labelangle=60 labeldist=0 taillabel="X4:2 "] + X1:p2r:e -- W1:w6:w + W1:w6:e -- X4:p2l:w + W1 [label=<
6x0.25 mm² (24 AWG)0.2 m
 
X1:1BKX2:1
X1:2RDX2:2
X1:1BKX3:1
X1:2RDX3:2
X1:1BKX4:1
X1:2RDX4:2
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] } diff --git a/examples/ex03.png b/examples/ex03.png index f1a5e9f..34c8b63 100644 Binary files a/examples/ex03.png and b/examples/ex03.png differ diff --git a/examples/ex03.svg b/examples/ex03.svg index ed8a261..24e80e2 100644 --- a/examples/ex03.svg +++ b/examples/ex03.svg @@ -4,298 +4,222 @@ - + - -cluster_W1 - -6x  |  0.25 mm² (24 AWG)  |  0.2 m - - + X1 - -X1 - -Molex Micro-Fit - -male - -2-pin - -GND - -VCC - -1 - -2 + +X1 + +Molex Micro-Fit + +male + +2-pin + +GND + +VCC + +1 + +2 - + -W1_w1l - +W1 + + +6x + +0.25 mm² (24 AWG) + +0.2 m +  +X1:1 +BK +X2:1 + + + +X1:2 +RD +X2:2 + + + +X1:1 +BK +X3:1 + + + +X1:2 +RD +X3:2 + + + +X1:1 +BK +X4:1 + + + +X1:2 +RD +X4:2 + + + +  - - -X1:p1r--W1_w1l:w - - - -            X1:1 + + +X1:e--W1:w + + + - - -W1_w2l - + + +X1:e--W1:w + + + - + -X1:p2r--W1_w2l:w - - - -            X1:2 +X1:e--W1:w + + + - - -W1_w3l - + + +X1:e--W1:w + + + - - -X1:p1r--W1_w3l:w - - - -            X1:1 + + +X1:e--W1:w + + + - - -W1_w4l - - - + -X1:p2r--W1_w4l:w - - - -            X1:2 - - - -W1_w5l - - - - -X1:p1r--W1_w5l:w - - - -            X1:1 - - - -W1_w6l - - - - -X1:p2r--W1_w6l:w - - - -            X1:2 +X1:e--W1:w + + + X2 - -X2 - -Molex Micro-Fit - -female - -2-pin - -1 - -2 - -GND - -VCC + +X2 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC X3 - -X3 - -Molex Micro-Fit - -female - -2-pin - -1 - -2 - -GND - -VCC + +X3 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC X4 - -X4 - -Molex Micro-Fit - -female - -2-pin - -1 - -2 - -GND - -VCC + +X4 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC - - -W1_w1r - + + +W1:e--X2:w + + + - - -W1_w1l--W1_w1r - - - -                                   BK - - - -W1_w1r:e--X2:p1l - - - -X2:1             - - - -W1_w2r - - - + -W1_w2l--W1_w2r - - - -                                   RD +W1:e--X2:w + + + - + -W1_w2r:e--X2:p2l - - - -X2:2             +W1:e--X3:w + + + - - -W1_w3r - + + +W1:e--X3:w + + + - - -W1_w3l--W1_w3r - - - -                                   BK - - - -W1_w3r:e--X3:p1l - - - -X3:1             - - - -W1_w4r - - - + -W1_w4l--W1_w4r - - - -                                   RD +W1:e--X4:w + + + - + -W1_w4r:e--X3:p2l - - - -X3:2             - - - -W1_w5r - - - - -W1_w5l--W1_w5r - - - -                                   BK - - - -W1_w5r:e--X4:p1l - - - -X4:1             - - - -W1_w6r - - - - -W1_w6l--W1_w6r - - - -                                   RD - - - -W1_w6r:e--X4:p2l - - - -X4:2             +W1:e--X4:w + + + diff --git a/examples/ex04.gv b/examples/ex04.gv index a191bba..b41fe00 100644 --- a/examples/ex04.gv +++ b/examples/ex04.gv @@ -1,66 +1,152 @@ graph { // Graph generated by WireViz // https://github.com/formatc1702/WireViz - graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + graph [bgcolor=white fontname=arial nodesep=0.33 rankdir=LR ranksep=2] node [fillcolor=white fontname=arial shape=record style=filled] edge [fontname=arial style=bold] - F1 [label="{crimp}|{{1}}"] - F2 [label="{crimp}|{{1}}"] - F3 [label="{crimp}|{{1}}"] - F4 [label="{crimp}|{{1}}"] - F5 [label="{crimp}|{{1}}"] - F6 [label="{crimp}|{{1}}"] - F7 [label="{crimp}|{{1}}"] - F8 [label="{crimp}|{{1}}"] - F9 [label="{crimp}|{{1}}"] - F10 [label="{crimp}|{{1}}"] - F11 [label="{crimp}|{{1}}"] - F12 [label="{crimp}|{{1}}"] - subgraph cluster_W1 { - graph [fillcolor=white label="6x | 0.25 mm² (24 AWG) | 0.2 m - " style="filled, dashed"] - node [fixedsize=true height=0 label="" shape=point width=0] - W1_w1l - W1_w1r - W1_w2l - W1_w2r - W1_w3l - W1_w3r - W1_w4l - W1_w4r - W1_w5l - W1_w5r - W1_w6l - W1_w6r - } + F1 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=180 shape=none style=filled] + F2 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=180 shape=none style=filled] + F3 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=180 shape=none style=filled] + F4 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=180 shape=none style=filled] + F5 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=180 shape=none style=filled] + F6 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=180 shape=none style=filled] + F7 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=0 shape=none style=filled] + F8 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=0 shape=none style=filled] + F9 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=0 shape=none style=filled] + F10 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=0 shape=none style=filled] + F11 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=0 shape=none style=filled] + F12 [label=< + + + + + +
crimp
+ + + > margin=0 orientation=0 shape=none style=filled] edge [color="#000000:#666600:#000000"] - W1_w1l -- W1_w1r [labelangle=60 labeldist=0 taillabel=" BN"] - F1:p1r -- W1_w1l:w [headlabel=" F1:1" labelangle=-60 labeldist=0] + F1:e -- W1:w1:w edge [color="#000000:#ff0000:#000000"] - W1_w2l -- W1_w2r [labelangle=60 labeldist=0 taillabel=" RD"] - F2:p1r -- W1_w2l:w [headlabel=" F2:1" labelangle=-60 labeldist=0] + F2:e -- W1:w2:w edge [color="#000000:#ff8000:#000000"] - W1_w3l -- W1_w3r [labelangle=60 labeldist=0 taillabel=" OG"] - F3:p1r -- W1_w3l:w [headlabel=" F3:1" labelangle=-60 labeldist=0] + F3:e -- W1:w3:w edge [color="#000000:#ffff00:#000000"] - W1_w4l -- W1_w4r [labelangle=60 labeldist=0 taillabel=" YE"] - F4:p1r -- W1_w4l:w [headlabel=" F4:1" labelangle=-60 labeldist=0] + F4:e -- W1:w4:w edge [color="#000000:#00ff00:#000000"] - W1_w5l -- W1_w5r [labelangle=60 labeldist=0 taillabel=" GN"] - F5:p1r -- W1_w5l:w [headlabel=" F5:1" labelangle=-60 labeldist=0] + F5:e -- W1:w5:w edge [color="#000000:#0066ff:#000000"] - W1_w6l -- W1_w6r [labelangle=60 labeldist=0 taillabel=" BU"] - F6:p1r -- W1_w6l:w [headlabel=" F6:1" labelangle=-60 labeldist=0] + F6:e -- W1:w6:w edge [color="#000000:#0066ff:#000000"] - W1_w6r:e -- F7:p1l [labelangle=60 labeldist=0 taillabel="F7:1 "] + W1:w6:e -- F7:w edge [color="#000000:#00ff00:#000000"] - W1_w5r:e -- F8:p1l [labelangle=60 labeldist=0 taillabel="F8:1 "] + W1:w5:e -- F8:w edge [color="#000000:#ffff00:#000000"] - W1_w4r:e -- F9:p1l [labelangle=60 labeldist=0 taillabel="F9:1 "] + W1:w4:e -- F9:w edge [color="#000000:#ff8000:#000000"] - W1_w3r:e -- F10:p1l [labelangle=60 labeldist=0 taillabel="F10:1 "] + W1:w3:e -- F10:w edge [color="#000000:#ff0000:#000000"] - W1_w2r:e -- F11:p1l [labelangle=60 labeldist=0 taillabel="F11:1 "] + W1:w2:e -- F11:w edge [color="#000000:#666600:#000000"] - W1_w1r:e -- F12:p1l [labelangle=60 labeldist=0 taillabel="F12:1 "] + W1:w1:e -- F12:w + W1 [label=<
6x0.25 mm² (24 AWG)0.2 m
 
BN
RD
OG
YE
GN
BU
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] } diff --git a/examples/ex04.png b/examples/ex04.png index 1b1fcea..5a1c603 100644 Binary files a/examples/ex04.png and b/examples/ex04.png differ diff --git a/examples/ex04.svg b/examples/ex04.svg index c09923f..2773290 100644 --- a/examples/ex04.svg +++ b/examples/ex04.svg @@ -4,314 +4,226 @@ - - - -cluster_W1 - -6x  |  0.25 mm² (24 AWG)  |  0.2 m - - + + + F1 - -crimp - -1 + + crimp   +   + - + -W1_w1l - +W1 + + +6x + +0.25 mm² (24 AWG) + +0.2 m +  +BN + + + +RD + + + +OG + + + +YE + + + +GN + + + +BU + + + +  - - -F1:p1r--W1_w1l:w - - - -            F1:1 + + +F1:e--W1:w + + + F2 - -crimp - -1 + + crimp   +   + - - -W1_w2l - - - - -F2:p1r--W1_w2l:w - - - -            F2:1 + + +F2:e--W1:w + + + F3 - -crimp - -1 + + crimp   +   + - - -W1_w3l - - - - -F3:p1r--W1_w3l:w - - - -            F3:1 + + +F3:e--W1:w + + + F4 - -crimp - -1 + + crimp   +   + - - -W1_w4l - - - - -F4:p1r--W1_w4l:w - - - -            F4:1 + + +F4:e--W1:w + + + F5 - -crimp - -1 + + crimp   +   + - - -W1_w5l - - - - -F5:p1r--W1_w5l:w - - - -            F5:1 + + +F5:e--W1:w + + + F6 - -crimp - -1 + + crimp   +   + - - -W1_w6l - - - - -F6:p1r--W1_w6l:w - - - -            F6:1 + + +F6:e--W1:w + + + F7 - -crimp - -1 + +   + crimp   + F8 - -crimp - -1 + +   + crimp   + F9 - -crimp - -1 + +   + crimp   + F10 - -crimp - -1 + +   + crimp   + F11 - -crimp - -1 + +   + crimp   + F12 - -crimp - -1 + +   + crimp   + - - -W1_w1r - - - - -W1_w1l--W1_w1r - - - -                                   BN - - - -W1_w1r:e--F12:p1l - - - -F12:1             - - - -W1_w2r - - - - -W1_w2l--W1_w2r - - - -                                   RD - - - -W1_w2r:e--F11:p1l - - - -F11:1             - - - -W1_w3r - - - - -W1_w3l--W1_w3r - - - -                                   OG - - - -W1_w3r:e--F10:p1l - - - -F10:1             - - - -W1_w4r - - - + -W1_w4l--W1_w4r - - - -                                   YE +W1:e--F7:w + + + - - -W1_w4r:e--F9:p1l - - - -F9:1             + + +W1:e--F8:w + + + - - -W1_w5r - - - + -W1_w5l--W1_w5r - - - -                                   GN +W1:e--F9:w + + + - - -W1_w5r:e--F8:p1l - - - -F8:1             + + +W1:e--F10:w + + + - - -W1_w6r - - - + -W1_w6l--W1_w6r - - - -                                   BU +W1:e--F11:w + + + - - -W1_w6r:e--F7:p1l - - - -F7:1             + + +W1:e--F12:w + + + diff --git a/examples/ex05.gv b/examples/ex05.gv new file mode 100644 index 0000000..f4b51bb --- /dev/null +++ b/examples/ex05.gv @@ -0,0 +1,36 @@ +graph { +// Graph generated by WireViz +// https://github.com/formatc1702/WireViz + graph [bgcolor=white fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + node [fillcolor=white fontname=arial shape=record style=filled] + edge [fontname=arial style=bold] + X1 [label="X1|{Molex KK 254|female|4-pin}|{{GND|VCC|SCL|SDA}|{1|2|3|4}}"] + X2 [label="X2|{Molex KK 254|female|4-pin}|{{1|2|3|4}|{GND|VCC|SCL|SDA}|{1|2|3|4}}"] + X3 [label="X3|{Molex KK 254|female|4-pin}|{{1|2|3|4}|{GND|VCC|SCL|SDA}}"] + edge [color="#000000:#ff66cc:#000000"] + X1:p1r:e -- W1:w1:w + W1:w1:e -- X2:p1l:w + edge [color="#000000:#00ffff:#000000"] + X1:p2r:e -- W1:w2:w + W1:w2:e -- X2:p2l:w + edge [color="#000000:#ffff00:#000000"] + X1:p3r:e -- W1:w3:w + W1:w3:e -- X2:p3l:w + edge [color="#000000:#8000ff:#000000"] + X1:p4r:e -- W1:w4:w + W1:w4:e -- X2:p4l:w + W1 [label=<
4x0.25 mm²0.2 m
 
X1:1PKX2:1
X1:2TQX2:2
X1:3YEX2:3
X1:4VTX2:4
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] + edge [color="#000000:#ff66cc:#000000"] + X2:p1r:e -- W2:w1:w + W2:w1:e -- X3:p1l:w + edge [color="#000000:#00ffff:#000000"] + X2:p2r:e -- W2:w2:w + W2:w2:e -- X3:p2l:w + edge [color="#000000:#ffff00:#000000"] + X2:p3r:e -- W2:w3:w + W2:w3:e -- X3:p3l:w + edge [color="#000000:#8000ff:#000000"] + X2:p4r:e -- W2:w4:w + W2:w4:e -- X3:p4l:w + W2 [label=<
4x0.25 mm²0.2 m
 
X2:1PKX3:1
X2:2TQX3:2
X2:3YEX3:3
X2:4VTX3:4
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] +} diff --git a/examples/ex05.png b/examples/ex05.png new file mode 100644 index 0000000..715713f Binary files /dev/null and b/examples/ex05.png differ diff --git a/examples/ex05.svg b/examples/ex05.svg new file mode 100644 index 0000000..dcb33e6 --- /dev/null +++ b/examples/ex05.svg @@ -0,0 +1,290 @@ + + + + + + + + + +X1 + +X1 + +Molex KK 254 + +female + +4-pin + +GND + +VCC + +SCL + +SDA + +1 + +2 + +3 + +4 + + + +W1 + + +4x + +0.25 mm² + +0.2 m +  +X1:1 +PK +X2:1 + + + +X1:2 +TQ +X2:2 + + + +X1:3 +YE +X2:3 + + + +X1:4 +VT +X2:4 + + + +  + + + +X1:e--W1:w + + + + + + +X1:e--W1:w + + + + + + +X1:e--W1:w + + + + + + +X1:e--W1:w + + + + + + +X2 + +X2 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + +VCC + +SCL + +SDA + +1 + +2 + +3 + +4 + + + +W2 + + +4x + +0.25 mm² + +0.2 m +  +X2:1 +PK +X3:1 + + + +X2:2 +TQ +X3:2 + + + +X2:3 +YE +X3:3 + + + +X2:4 +VT +X3:4 + + + +  + + + +X2:e--W2:w + + + + + + +X2:e--W2:w + + + + + + +X2:e--W2:w + + + + + + +X2:e--W2:w + + + + + + +X3 + +X3 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + +VCC + +SCL + +SDA + + + +W1:e--X2:w + + + + + + +W1:e--X2:w + + + + + + +W1:e--X2:w + + + + + + +W1:e--X2:w + + + + + + +W2:e--X3:w + + + + + + +W2:e--X3:w + + + + + + +W2:e--X3:w + + + + + + +W2:e--X3:w + + + + + + diff --git a/examples/ex05.yml b/examples/ex05.yml new file mode 100644 index 0000000..f5dc80e --- /dev/null +++ b/examples/ex05.yml @@ -0,0 +1,35 @@ +# daisy chain, variant 1 +templates: + - &template_con + type: Molex KK 254 + gender: female + pinout: [GND, VCC, SCL, SDA] + - &template_wire + mm2: 0.25 + length: 0.2 + colors: [PK, TQ, YE, VT] + type: bundle + +nodes: + X1: + <<: *template_con + X2: + <<: *template_con + X3: + <<: *template_con + +wires: + W1: + <<: *template_wire + W2: + <<: *template_wire + +connections: + - + - X1: [1-4] + - W1: [1-4] + - X2: [1-4] + - + - X2: [1-4] + - W2: [1-4] + - X3: [1-4] diff --git a/examples/ex06.gv b/examples/ex06.gv new file mode 100644 index 0000000..e3f4ea0 --- /dev/null +++ b/examples/ex06.gv @@ -0,0 +1,78 @@ +graph { +// Graph generated by WireViz +// https://github.com/formatc1702/WireViz + graph [bgcolor=white fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + node [fillcolor=white fontname=arial shape=record style=filled] + edge [fontname=arial style=bold] + X1 [label="X1|{Molex KK 254|female|4-pin}|{{GND|VCC|SCL|SDA}|{1|2|3|4}}"] + X2 [label="X2|{Molex KK 254|female|4-pin}|{{1|2|3|4}|{GND|VCC|SCL|SDA}}"] + X3 [label="X3|{Molex KK 254|female|4-pin}|{{GND|VCC|SCL|SDA}|{1|2|3|4}}"] + X4 [label="X4|{Molex KK 254|female|4-pin}|{{1|2|3|4}|{GND|VCC|SCL|SDA}}"] + X5 [label="X5|{Molex KK 254|female|4-pin}|{{GND|VCC|SCL|SDA}|{1|2|3|4}}"] + X6 [label="X6|{Molex KK 254|female|4-pin}|{{1|2|3|4}|{GND|VCC|SCL|SDA}}"] + edge [color="#000000:#ff66cc:#000000"] + X1:p1r:e -- W1:w1:w + W1:w1:e -- X2:p1l:w + edge [color="#000000:#00ffff:#000000"] + X1:p2r:e -- W1:w2:w + W1:w2:e -- X2:p2l:w + edge [color="#000000:#ffff00:#000000"] + X1:p3r:e -- W1:w3:w + W1:w3:e -- X2:p3l:w + edge [color="#000000:#8000ff:#000000"] + X1:p4r:e -- W1:w4:w + W1:w4:e -- X2:p4l:w + W1 [label=<
4x0.25 mm²0.2 m
 
X1:1PKX2:1
X1:2TQX2:2
X1:3YEX2:3
X1:4VTX2:4
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] + edge [color="#000000:#ff66cc:#000000"] + X3:p1r:e -- W2:w1:w + W2:w1:e -- X2:p1l:w + edge [color="#000000:#00ffff:#000000"] + X3:p2r:e -- W2:w2:w + W2:w2:e -- X2:p2l:w + edge [color="#000000:#ffff00:#000000"] + X3:p3r:e -- W2:w3:w + W2:w3:e -- X2:p3l:w + edge [color="#000000:#8000ff:#000000"] + X3:p4r:e -- W2:w4:w + W2:w4:e -- X2:p4l:w + W2 [label=<
4x0.25 mm²0.2 m
 
X3:1PKX2:1
X3:2TQX2:2
X3:3YEX2:3
X3:4VTX2:4
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] + edge [color="#000000:#ff66cc:#000000"] + X3:p1r:e -- W3:w1:w + W3:w1:e -- X4:p1l:w + edge [color="#000000:#00ffff:#000000"] + X3:p2r:e -- W3:w2:w + W3:w2:e -- X4:p2l:w + edge [color="#000000:#ffff00:#000000"] + X3:p3r:e -- W3:w3:w + W3:w3:e -- X4:p3l:w + edge [color="#000000:#8000ff:#000000"] + X3:p4r:e -- W3:w4:w + W3:w4:e -- X4:p4l:w + W3 [label=<
4x0.25 mm²0.2 m
 
X3:1PKX4:1
X3:2TQX4:2
X3:3YEX4:3
X3:4VTX4:4
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] + edge [color="#000000:#ff66cc:#000000"] + X5:p1r:e -- W4:w1:w + W4:w1:e -- X4:p1l:w + edge [color="#000000:#00ffff:#000000"] + X5:p2r:e -- W4:w2:w + W4:w2:e -- X4:p2l:w + edge [color="#000000:#ffff00:#000000"] + X5:p3r:e -- W4:w3:w + W4:w3:e -- X4:p3l:w + edge [color="#000000:#8000ff:#000000"] + X5:p4r:e -- W4:w4:w + W4:w4:e -- X4:p4l:w + W4 [label=<
4x0.25 mm²0.2 m
 
X5:1PKX4:1
X5:2TQX4:2
X5:3YEX4:3
X5:4VTX4:4
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] + edge [color="#000000:#ff66cc:#000000"] + X5:p1r:e -- W5:w1:w + W5:w1:e -- X6:p1l:w + edge [color="#000000:#00ffff:#000000"] + X5:p2r:e -- W5:w2:w + W5:w2:e -- X6:p2l:w + edge [color="#000000:#ffff00:#000000"] + X5:p3r:e -- W5:w3:w + W5:w3:e -- X6:p3l:w + edge [color="#000000:#8000ff:#000000"] + X5:p4r:e -- W5:w4:w + W5:w4:e -- X6:p4l:w + W5 [label=<
4x0.25 mm²0.2 m
 
X5:1PKX6:1
X5:2TQX6:2
X5:3YEX6:3
X5:4VTX6:4
 
> fillcolor=white margin=0 shape=box style="filled,dashed"] +} diff --git a/examples/ex06.png b/examples/ex06.png new file mode 100644 index 0000000..43cc416 Binary files /dev/null and b/examples/ex06.png differ diff --git a/examples/ex06.svg b/examples/ex06.svg new file mode 100644 index 0000000..0646f25 --- /dev/null +++ b/examples/ex06.svg @@ -0,0 +1,645 @@ + + + + + + + + + +X1 + +X1 + +Molex KK 254 + +female + +4-pin + +GND + +VCC + +SCL + +SDA + +1 + +2 + +3 + +4 + + + +W1 + + +4x + +0.25 mm² + +0.2 m +  +X1:1 +PK +X2:1 + + + +X1:2 +TQ +X2:2 + + + +X1:3 +YE +X2:3 + + + +X1:4 +VT +X2:4 + + + +  + + + +X1:e--W1:w + + + + + + +X1:e--W1:w + + + + + + +X1:e--W1:w + + + + + + +X1:e--W1:w + + + + + + +X2 + +X2 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + +VCC + +SCL + +SDA + + + +X3 + +X3 + +Molex KK 254 + +female + +4-pin + +GND + +VCC + +SCL + +SDA + +1 + +2 + +3 + +4 + + + +W2 + + +4x + +0.25 mm² + +0.2 m +  +X3:1 +PK +X2:1 + + + +X3:2 +TQ +X2:2 + + + +X3:3 +YE +X2:3 + + + +X3:4 +VT +X2:4 + + + +  + + + +X3:e--W2:w + + + + + + +X3:e--W2:w + + + + + + +X3:e--W2:w + + + + + + +X3:e--W2:w + + + + + + +W3 + + +4x + +0.25 mm² + +0.2 m +  +X3:1 +PK +X4:1 + + + +X3:2 +TQ +X4:2 + + + +X3:3 +YE +X4:3 + + + +X3:4 +VT +X4:4 + + + +  + + + +X3:e--W3:w + + + + + + +X3:e--W3:w + + + + + + +X3:e--W3:w + + + + + + +X3:e--W3:w + + + + + + +X4 + +X4 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + +VCC + +SCL + +SDA + + + +X5 + +X5 + +Molex KK 254 + +female + +4-pin + +GND + +VCC + +SCL + +SDA + +1 + +2 + +3 + +4 + + + +W4 + + +4x + +0.25 mm² + +0.2 m +  +X5:1 +PK +X4:1 + + + +X5:2 +TQ +X4:2 + + + +X5:3 +YE +X4:3 + + + +X5:4 +VT +X4:4 + + + +  + + + +X5:e--W4:w + + + + + + +X5:e--W4:w + + + + + + +X5:e--W4:w + + + + + + +X5:e--W4:w + + + + + + +W5 + + +4x + +0.25 mm² + +0.2 m +  +X5:1 +PK +X6:1 + + + +X5:2 +TQ +X6:2 + + + +X5:3 +YE +X6:3 + + + +X5:4 +VT +X6:4 + + + +  + + + +X5:e--W5:w + + + + + + +X5:e--W5:w + + + + + + +X5:e--W5:w + + + + + + +X5:e--W5:w + + + + + + +X6 + +X6 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + +VCC + +SCL + +SDA + + + +W1:e--X2:w + + + + + + +W1:e--X2:w + + + + + + +W1:e--X2:w + + + + + + +W1:e--X2:w + + + + + + +W2:e--X2:w + + + + + + +W2:e--X2:w + + + + + + +W2:e--X2:w + + + + + + +W2:e--X2:w + + + + + + +W3:e--X4:w + + + + + + +W3:e--X4:w + + + + + + +W3:e--X4:w + + + + + + +W3:e--X4:w + + + + + + +W4:e--X4:w + + + + + + +W4:e--X4:w + + + + + + +W4:e--X4:w + + + + + + +W4:e--X4:w + + + + + + +W5:e--X6:w + + + + + + +W5:e--X6:w + + + + + + +W5:e--X6:w + + + + + + +W5:e--X6:w + + + + + + diff --git a/examples/ex06.yml b/examples/ex06.yml new file mode 100644 index 0000000..a06f670 --- /dev/null +++ b/examples/ex06.yml @@ -0,0 +1,59 @@ +# daisy chain, variant 2 +templates: + - &template_con + type: Molex KK 254 + gender: female + pinout: [GND, VCC, SCL, SDA] + - &template_wire + mm2: 0.25 + length: 0.2 + colors: [PK, TQ, YE, VT] + type: bundle + +nodes: + X1: + <<: *template_con + X2: + <<: *template_con + X3: + <<: *template_con + X4: + <<: *template_con + X5: + <<: *template_con + X6: + <<: *template_con + +wires: + W1: + <<: *template_wire + W2: + <<: *template_wire + W3: + <<: *template_wire + W4: + <<: *template_wire + W5: + <<: *template_wire + +connections: + - + - X1: [1-4] + - W1: [1-4] + - X2: [1-4] + - + - X3: [1-4] + - W2: [1-4] + - X2: [1-4] + - + - X3: [1-4] + - W3: [1-4] + - X4: [1-4] + - + - X5: [1-4] + - W4: [1-4] + - X4: [1-4] + - + - X5: [1-4] + - W5: [1-4] + - X6: [1-4] diff --git a/examples/readme.md b/examples/readme.md index 92a0c3f..28326f1 100644 --- a/examples/readme.md +++ b/examples/readme.md @@ -23,3 +23,15 @@ [Source](ex04.yml) +## Example 05 +![](ex05.png) + +[Source](ex05.yml) + + +## Example 06 +![](ex06.png) + +[Source](ex06.yml) + + diff --git a/idea/example1.gv b/idea/example1.gv deleted file mode 100644 index fc388f5..0000000 --- a/idea/example1.gv +++ /dev/null @@ -1,29 +0,0 @@ -// Graph generated by WireViz -// https://github.com/formatc1702/WireViz -// Daniel Rojas - 2020 - -digraph G { - graph [rankdir = LR, ranksep=2, fontname = "arial"]; - edge [arrowhead=none, fontname = "arial"]; - node [shape=record, style=rounded, fontname = "arial"]; - - -X1[label="X1 | {D-Sub|female|9-pin} | {{DCD|RX|TX|DTR|GND|DSR|RTS|CTS|RI} | {1|2|3|4|5|6|7|8|9}}}"] - -X2[label="X2 | {Molex KK 254|female|6-pin} | {{1|2|3|4|5|6} | {GND|RX|TX|NC|OUT|IN}}}"] - -{edge[style=bold] -X2:p5:w -> X2:p6:w -} - -W1[label="W1 | {3x|0.25 mm²| + S|0.2 m} | {{1|2|3|} | {WH|BN|GN|Shield} | {1|2|3|}}}"] - -{edge[style=bold] -{edge[color="#000000:#ffffff:#000000"] X1:p5 -> W1:w1i; W1:w1o -> X2:p1} -{edge[color="#000000:#666600:#000000"] X1:p2 -> W1:w2i; W1:w2o -> X2:p3} -{edge[color="#000000:#00ff00:#000000"] X1:p3 -> W1:w3i; W1:w3o -> X2:p2} -{X1:p5 -> W1:wsi; } -} - - -} diff --git a/idea/example1.png b/idea/example1.png deleted file mode 100644 index f8ecb55..0000000 Binary files a/idea/example1.png and /dev/null differ diff --git a/idea/example1.wire b/idea/example1.wire deleted file mode 100644 index 5cdb78e..0000000 --- a/idea/example1.wire +++ /dev/null @@ -1,28 +0,0 @@ -// define connectors - -X1 [type="D-Sub", - gender="female", - pin_labels="DCD|RX|TX|DTR|GND|DSR|RTS|CTS|RI", - ] - -X2 [type="Molex KK 254", - gender="female", - pin_labels="GND|RX|TX|NC|OUT|IN", - ] - -// define wire - -W1 [mm2=0.25, - length=0.2, - num_wires=3, - colors="din47100", - shield=true - ] - -// define connections - -X1:5 -> W1:1 -> X2:1 // GND -X1:2 -> W1:2 -> X2:3 // TX-RX -X1:3 -> W1:3 -> X2:2 // RX-TX -X1:5 -> W1:S // shield -X2:5 -> X2:6 // loop diff --git a/idea/example2.gv b/idea/example2.gv deleted file mode 100644 index fa191bd..0000000 --- a/idea/example2.gv +++ /dev/null @@ -1,53 +0,0 @@ -// Graph generated by WireViz -// https://github.com/formatc1702/WireViz -// Daniel Rojas - 2020 - -digraph G { - graph [rankdir = LR, ranksep=2, fontname = "arial"]; - edge [arrowhead=none, fontname = "arial"]; - node [shape=record, style=rounded, fontname = "arial"]; - - -X1[label="X1 | {Molex KK 254|female|8-pin} | {{GND|+5V|SCL|SDA|MISO|MOSI|SCK|N/C} | {1|2|3|4|5|6|7|8}}}"] - -X2[label="X2 | {Molex KK 254|female|4-pin} | {{1|2|3|4} | {GND|+5V|SCL|SDA}}}"] - -X3[label="X3 | {Molex KK 254|female|4-pin} | {{1|2|3|4} | {GND|+5V|SCL|SDA}}}"] - -X4[label="X4 | {Molex KK 254|female|5-pin} | {{1|2|3|4|5} | {GND|+12V|MISO|MOSI|SCK}}}"] - -X5[label="X5 | {Molex Micro-Fit|male|2-pin} | {{GND|+12V} | {1|2}}}"] - -W1[label="{4x|0.14 mm²|0.2 m} | {{BK|RD|YE|GN}}}"] - -{edge[style=bold] -{edge[color="#000000:#000000:#000000"] X1:p1 -> W1:w1; W1:w1 -> X2:p1} -{edge[color="#000000:#ff0000:#000000"] X1:p2 -> W1:w2; W1:w2 -> X2:p2} -{edge[color="#000000:#ffff00:#000000"] X1:p3 -> W1:w3; W1:w3 -> X2:p3} -{edge[color="#000000:#00ff00:#000000"] X1:p4 -> W1:w4; W1:w4 -> X2:p4} -} -W2[label="{4x|0.14 mm²|0.2 m} | {{BK|RD|YE|GN}}}"] - -{edge[style=bold] -{edge[color="#000000:#000000:#000000"] X1:p1 -> W2:w1; W2:w1 -> X3:p1} -{edge[color="#000000:#ff0000:#000000"] X1:p2 -> W2:w2; W2:w2 -> X3:p2} -{edge[color="#000000:#ffff00:#000000"] X1:p3 -> W2:w3; W2:w3 -> X3:p3} -{edge[color="#000000:#00ff00:#000000"] X1:p4 -> W2:w4; W2:w4 -> X3:p4} -} -W3[label="{4x|0.14 mm²|0.2 m} | {{BK|BU|OG|VT}}}"] - -{edge[style=bold] -{edge[color="#000000:#000000:#000000"] X1:p1 -> W3:w1; W3:w1 -> X4:p1} -{edge[color="#000000:#0000ff:#000000"] X1:p5 -> W3:w2; W3:w2 -> X4:p3} -{edge[color="#000000:#ff8000:#000000"] X1:p6 -> W3:w3; W3:w3 -> X4:p4} -{edge[color="#000000:#8000ff:#000000"] X1:p7 -> W3:w4; W3:w4 -> X4:p5} -} -W4[label="{2x|0.5 mm²|0.35 m} | {{BK|RD}}}"] - -{edge[style=bold] -{edge[color="#000000:#000000:#000000"] X5:p1 -> W4:w1; W4:w1 -> X4:p1} -{edge[color="#000000:#ff0000:#000000"] X5:p2 -> W4:w2; W4:w2 -> X4:p2} -} - - -} diff --git a/idea/example2.png b/idea/example2.png deleted file mode 100644 index 79d9131..0000000 Binary files a/idea/example2.png and /dev/null differ diff --git a/src/batch.py b/src/batch.py index 19bc386..fc80270 100644 --- a/src/batch.py +++ b/src/batch.py @@ -11,7 +11,7 @@ with open(readme, 'w') as file: print(fn) wireviz.parse(fn) - for i in range(1,5): + for i in range(1,7): fn = '../examples/ex{:02d}.yml'.format(i) print(fn) wireviz.parse(fn) diff --git a/src/wireviz.py b/src/wireviz.py index 9f5e4a2..0929a38 100755 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -83,7 +83,7 @@ class Harness: font = 'arial' dot.attr('graph', rankdir='LR', ranksep='2', - bgcolor='transparent', + bgcolor='white', nodesep='0.33', fontname=font) dot.attr('node', shape='record', @@ -102,35 +102,59 @@ class Harness: self.nodes[x.to_name].ports_left = True for k, n in self.nodes.items(): - # a = attributes - a = [n.type, - n.gender, - '{}-pin'.format(len(n.pinout)) if n.show_num_pins else ''] - # p = pinout - p = [[],[],[]] - p[1] = list(n.pinout) - for i, x in enumerate(n.pinout, 1): - if n.ports_left: - p[0].append('{portno}'.format(portno=i)) - if n.ports_right: - p[2].append('{portno}'.format(portno=i)) - # l = label - l = [n.name if n.show_name else '', a, p] - dot.node(k, label=nested(l)) + if n.category == 'ferrule': + infostring = '{type} {color}'.format(type=n.type, + color=translate_color(n.color, self.color_mode) if n.color else '') + infostring_l = infostring if n.ports_right else '' + infostring_r = infostring if n.ports_left else '' - if len(n.loops) > 0: - dot.attr('edge',color='#000000') - if n.ports_left: - loop_side = 'l' - loop_dir = 'w' - elif n.ports_right: - loop_side = 'r' - loop_dir = 'e' - else: - raise Exception('No side for loops') - for loop in n.loops: - dot.edge('{name}:p{port_from}{loop_side}:{loop_dir}'.format(name=n.name, port_from=loop[0], port_to=loop[1], loop_side=loop_side, loop_dir=loop_dir), - '{name}:p{port_to}{loop_side}:{loop_dir}'.format(name=n.name, port_from=loop[0], port_to=loop[1], loop_side=loop_side, loop_dir=loop_dir)) + dot.node(k, shape='none', + style='filled', + margin='0', + orientation = '0' if n.ports_left else '180', + label='''< + + + + {colorbar} + +
{infostring_l} {infostring_r}
+ + + >'''.format(infostring_l=infostring_l, + infostring_r=infostring_r, + colorbar=''.format(translate_color(n.color, 'HEX')) if n.color else '')) + # dot.node(k, label='{A|B|{C|D|E}}') + else: + # a = attributes + a = [n.type, + n.gender, + '{}-pin'.format(len(n.pinout)) if n.show_num_pins else ''] + # p = pinout + p = [[],[],[]] + p[1] = list(n.pinout) + for i, x in enumerate(n.pinout, 1): + if n.ports_left: + p[0].append('{portno}'.format(portno=i)) + if n.ports_right: + p[2].append('{portno}'.format(portno=i)) + # l = label + l = [n.name if n.show_name else '', a, p] + dot.node(k, label=nested(l)) + + if len(n.loops) > 0: + dot.attr('edge',color='#000000') + if n.ports_left: + loop_side = 'l' + loop_dir = 'w' + elif n.ports_right: + loop_side = 'r' + loop_dir = 'e' + else: + raise Exception('No side for loops') + for loop in n.loops: + dot.edge('{name}:p{port_from}{loop_side}:{loop_dir}'.format(name=n.name, port_from=loop[0], port_to=loop[1], loop_side=loop_side, loop_dir=loop_dir), + '{name}:p{port_to}{loop_side}:{loop_dir}'.format(name=n.name, port_from=loop[0], port_to=loop[1], loop_side=loop_side, loop_dir=loop_dir)) for k, c in self.cables.items(): # a = attributes @@ -139,47 +163,54 @@ class Harness: c.awg, '+ S' if c.shield else '', '{} m'.format(c.length) if c.length > 0 else ''] - # p = pinout - p = [[],[],[]] - for i, x in enumerate(c.colors,1): - if c.show_pinout: - p[0].append('{wireno}'.format(wireno=i)) - p[1].append('{wirecolor}'.format(wirecolor=translate_color(x, self.color_mode))) - p[2].append('{wireno}'.format(wireno=i)) - else: - p[1].append('{wirecolor}'.format(wireno=i,wirecolor=translate_color(x, self.color_mode))) - if c.shield: - if c.show_pinout: - p[0].append('') - p[1].append('Shield') - p[2].append('') - else: - p[1].append('Shield') - # l = label - l = [c.name if c.show_name else '', a, p] - if c.type == 'bundle': - # create subgraph for wire bundle, add to main graph afterwards - bun = Graph(name='cluster_{}'.format(k)) - labeltext = ' | '.join(p for p in a if p) + '\n ' # newline to add space between label and wires - bun.attr('graph', label=labeltext, - style='filled, dashed', - fillcolor='white') - bun.attr('node', shape='point', - label='', - fixedsize='true', - width='0', height='0') - for i, x in enumerate(c.colors,1): - bun.node('{}_w{}l'.format(k,i)) - bun.node('{}_w{}r'.format(k,i)) - else: - dot.node(k, label=nested(l)) + # print(a) + a = list(filter(None, a)) + # print(a) - # add bundle subgraph to main graph - if c.type == 'bundle': - dot.subgraph(bun) + html = '' # name+attributes table + + html = html + '' # spacer between attributes and wires + + html = html + '
' # main table + + html = html + '' # name+attributes table + if (not c.show_name) or c.type != 'bundle': + html = html + ''.format(colspan=len(a), name=c.name) + html = html + '' # attribute row + for attrib in a: + html = html + ''.format(attrib=attrib) + html = html + '' # attribute row + html = html + '
{name}
{attrib}
 
' # conductor table + + for i, x in enumerate(c.colors,1): + p = [] + p.append(''.format(i)) + p.append(translate_color(x, self.color_mode)) + p.append(''.format(i)) + html = html + '' + for bla in p: + html = html + ''.format(bla) + html = html + '' + html = html + ''.format(colspan=len(p), bgcolor=translate_color(x, 'hex'), port='w{}'.format(i)) + + if c.shield: + p = ['', 'Shield', ''] + html = html + '' # spacer + html = html + '' + for bla in p: + html = html + ''.format(bla) + html = html + '' + html = html + ''.format(colspan=len(p), bgcolor=translate_color(x, 'hex'), port='ws') + + html = html + '' # spacer at the end + + html = html + '
{}
 
{}
 
' # conductor table + + html = html + '
' # main table + + # print(html) # connections - existing_connections = [] # for bundles, avoid multiple edges between a bundle's wire's start and end node for x in c.connections: if isinstance(x.via_port, int): # check if it's an actual wire and not a shield search_color = c.colors[x.via_port-1] @@ -190,36 +221,22 @@ class Harness: else: # it's a shield connection dot.attr('edge',color='#000000') - if c.type == 'bundle': - labeltext = '{sp}{color}'.format(color=translate_color(c.colors[x.via_port-1], self.color_mode), sp=' ' * 35) - if x.via_port not in existing_connections: - dot.edge('{via_name}_w{via_wire}l'.format(via_name=c.name, via_wire=x.via_port), - '{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=x.via_port), - taillabel=labeltext, - labelangle='60', - labeldist='0') - existing_connections.append(x.via_port) - if x.from_port is not None: # connect to left - if c.type == 'bundle': - dot.edge('{from_name}:p{from_port}r'.format(from_name=x.from_name, from_port=x.from_port), - '{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=x.via_port), - headlabel='{}{}:{}'.format(' ' * 12, x.from_name, x.from_port), - labelangle='-60', - labeldist='0') - else: - dot.edge('{from_name}:p{from_port}r'.format(from_name=x.from_name, from_port=x.from_port), - '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x.via_port, via_subport='i' if c.show_pinout else '')) + from_ferrule = self.nodes[x.from_name].category is 'ferrule' + code_left_1 = '{from_name}{from_port}:e'.format(from_name=x.from_name, from_port=':p{}r'.format(x.from_port) if not from_ferrule else '') + code_left_2 = '{via_name}:w{via_wire}:w'.format(via_name=c.name, via_wire=x.via_port, via_subport='i' if c.show_pinout else '') + dot.edge(code_left_1, code_left_2) + from_string = '{}:{}'.format(x.from_name, x.from_port) if not from_ferrule else '' + html = html.replace(''.format(x.via_port), from_string) if x.to_port is not None: # connect to right - if c.type == 'bundle': - dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=x.via_port), - '{to_name}:p{to_port}l'.format(to_name=x.to_name, to_port=x.to_port), - taillabel='{}:{}{}'.format(x.to_name, x.to_port,' ' * 12), - labelangle='60', - labeldist='0') - else: - dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x.via_port, via_subport='o' if c.show_pinout else ''), - '{to_name}:p{to_port}l'.format(to_name=x.to_name, to_port=x.to_port)) + to_ferrule = self.nodes[x.to_name].category is 'ferrule' + code_right_1 = '{via_name}:w{via_wire}:e'.format(via_name=c.name, via_wire=x.via_port, via_subport='o' if c.show_pinout else '') + code_right_2 = '{to_name}{to_port}:w'.format(to_name=x.to_name, to_port=':p{}l'.format(x.to_port) if not to_ferrule else '') + dot.edge(code_right_1, code_right_2) + to_string = '{}:{}'.format(x.to_name, x.to_port) if not to_ferrule else '' + html = html.replace(''.format(x.via_port), to_string) + + dot.node(c.name, label='<{html}>'.format(html=html), shape='box', style='filled,dashed' if c.type=='bundle' else '', margin='0', fillcolor='white') return dot @@ -233,10 +250,12 @@ class Harness: @dataclass class Node: name: str + category: str = None type: str = None gender: str = None num_pins: int = None pinout: List[Any] = field(default_factory=list) + color: str = None show_name: bool = True show_num_pins: bool = True @@ -455,6 +474,7 @@ def parse(file_in, file_out=None): h.add_cable(name=k, **o) elif sec == 'ferrules': pass + # h.add_node(name=k, category='ferrule', **o) else: print('{} section empty'.format(sec)) else: @@ -558,7 +578,7 @@ def parse(file_in, file_out=None): for wire_pin in wire_pins: ferrule_counter = ferrule_counter + 1 ferrule_id = 'F{}'.format(ferrule_counter) - h.add_node(ferrule_id, **ferrule_params) + h.add_node(ferrule_id, category='ferrule', **ferrule_params) if f_w: h.connect(ferrule_id, 1, wire_name, wire_pin, None, None) diff --git a/todo.md b/todo.md index 2bb0277..fc64aa5 100644 --- a/todo.md +++ b/todo.md @@ -32,8 +32,6 @@ ## Visualization * Parse and render double-colored, striped cables ('RDBU' etc) -* Show from/to inside wire node (better netlist) - * Implemented in wire bundles only * Display picture of connector underneath (including pin 1 location) ## Export