diff --git a/src/test.py b/src/test.py
index 536df0f..b7241ec 100644
--- a/src/test.py
+++ b/src/test.py
@@ -10,7 +10,7 @@ PINOUT_SPI_DATAONLY = ('MISO','MOSI','SCK')
 # example 1
 X1 = wireviz.Node('X1', type='D-Sub DE-9', gender='female', pinout=PINOUT_SERIAL, ports_right=True)
 X2 = wireviz.Node('X2', type='Molex KK 254', gender='female', num_pins=6, ports_left=True)
-W1 = wireviz.Cable('W1', mm2=0.25, length=0.2, show_name=False, num_wires=3, color_code='DIN', shield=True)
+W1 = wireviz.Cable('W1', mm2=0.25, length=0.2, show_name=False, show_pinout=False, num_wires=3, color_code='DIN', shield=True)
 # Option 1: define wires and shield in one line
 # W1.connect(X1,(5,2,3,5),(1,2,3,'s'),X2,(1,3,2,None))
 # Option 2: define wires and shield separately
diff --git a/src/wireviz.py b/src/wireviz.py
index 6c97aba..a5444e2 100644
--- a/src/wireviz.py
+++ b/src/wireviz.py
@@ -110,12 +110,13 @@ class Node:
 
 class Cable:
 
-    def __init__(self, name, mm2=0, awg=0, length=0, show_name=False, num_wires=None, colors=None, color_code=None, shield=False):
+    def __init__(self, name, mm2=0, awg=0, length=0, show_name=False, show_pinout=False, num_wires=None, colors=None, color_code=None, shield=False):
         self.name = name
         self.mm2 = mm2
         self.awg = awg
         self.length = length
         self.show_name = show_name
+        self.show_pinout = show_pinout
         self.shield = shield
         self.connections = []
         if color_code is None and colors is None:
@@ -193,29 +194,39 @@ class Cable:
 
         s = s + '{'
         # print pinout
-        s = s + '{'
-        l = []
-        for i,x in enumerate(self.colors,1):
-            l.append('<w{wireno}i>{wireno}'.format(wireno=i))
-        s = s + '|'.join(l)
-        if self.shield == True:
-            s = s + '|<wsi>'
-        s = s + '} | '
+        if self.show_pinout:
+            s = s + '{'
+            l = []
+            for i,x in enumerate(self.colors,1):
+                l.append('<w{wireno}i>{wireno}'.format(wireno=i))
+            s = s + '|'.join(l)
+            if self.shield == True:
+                s = s + '|<wsi>'
+            s = s + '} | '
 
         s = s + '{'
-        s = s + '|'.join(self.colors)
-        if self.shield == True:
-            s = s + '|Shield'
+        if self.show_pinout:
+            s = s + '|'.join(self.colors)
+            if self.shield == True:
+                s = s + '|Shield'
+        else:
+            l = []
+            for i,x in enumerate(self.colors,1):
+                l.append('<w{wireno}>{wirecolor}'.format(wireno=i,wirecolor=x))
+            s = s + '|'.join(l)
+            if self.shield == True:
+                s = s + '|<ws>Shield'
         s = s + '}'
 
-        s = s + ' | {'
-        l = []
-        for i,x in enumerate(self.colors,1):
-            l.append('<w{wireno}o>{wireno}'.format(wireno=i))
-        s = s + '|'.join(l)
-        if self.shield == True:
-            s = s + '|<wso>'
-        s = s + '}'
+        if self.show_pinout:
+            s = s + ' | {'
+            l = []
+            for i,x in enumerate(self.colors,1):
+                l.append('<w{wireno}o>{wireno}'.format(wireno=i))
+            s = s + '|'.join(l)
+            if self.shield == True:
+                s = s + '|<wso>'
+            s = s + '}'
 
         s = s + '}}"]'
 
@@ -228,10 +239,10 @@ class Cable:
                 if search_color in color_dict:
                     s = s + 'edge[color="#000000:{wire_color}:#000000"] '.format(wire_color=color_dict[search_color])
             if x[1] is not None:
-                t = '{from_name}:p{from_port} -> {via_name}:w{via_wire}i; '.format(from_name=x[0],from_port=x[1],via_name=self.name, via_wire=x[2])
+                t = '{from_name}:p{from_port} -> {via_name}:w{via_wire}{via_subport}; '.format(from_name=x[0],from_port=x[1],via_name=self.name, via_wire=x[2], via_subport='i' if self.show_pinout == True else '')
                 s = s + t
             if x[4] is not None:
-                t = '{via_name}:w{via_wire}o -> {to_name}:p{to_port}'.format(via_name=self.name, via_wire=x[2],to_name=x[3],to_port=x[4])
+                t = '{via_name}:w{via_wire}{via_subport} -> {to_name}:p{to_port}'.format(via_name=self.name, via_wire=x[2],to_name=x[3],to_port=x[4], via_subport='o' if self.show_pinout == True else '')
                 s = s + t
             s = s + '}\n'
         s = s + '}'