From 3becef78298d2a3bf15281962f61815f88137479 Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 29 May 2020 22:37:48 +0200 Subject: [PATCH] Add support for wire bundles --- examples/bundles.yml | 65 ++++++++++++++++++++++++++++++++++++++++ examples/ferrules.yml | 6 ++-- src/wireviz.py | 69 ++++++++++++++++++++++++++++++++++++------- src/yaml2wireviz.py | 1 + 4 files changed, 126 insertions(+), 15 deletions(-) create mode 100644 examples/bundles.yml diff --git a/examples/bundles.yml b/examples/bundles.yml new file mode 100644 index 0000000..ccdf2b0 --- /dev/null +++ b/examples/bundles.yml @@ -0,0 +1,65 @@ +templates: # defining templates to be used later on + - &molex_f + type: Molex KK 254 + gender: female + - &con_i2c + pinout: [GND, +5V, SCL, SDA] + - &wire_i2c + mm2: 0.14 + length: 0.2 + colors: [BK, RD, YE, GN] + +nodes: + X1: + <<: *molex_f # copying items from the template + pinout: [GND, +5V, SCL, SDA, MISO, MOSI, SCK, N/C] + X2: + <<: *molex_f + <<: *con_i2c # it is possible to copy from more than one template + X3: + <<: *molex_f + <<: *con_i2c + X4: + <<: *molex_f + pinout: [GND, +12V, MISO, MOSI, flachstecker] + X5: + type: Molex Micro-Fit + gender: male + pinout: [GND, +12V] + +wires: + W1: + <<: *wire_i2c + type: bundle + W2: + <<: *wire_i2c + type: bundle + W3: + mm2: 0.14 + # length: 0.2 + type: bundle + colors: [BK, BU, OG, VT] + W4: + mm2: 0.5 + length: 0.35 + colors: [BK, RD] + type: bundle + show_num_wires: false + +connections: + - + - X1: [1-4] + - W1: [1-4] + - X2: [1-4] + - + - X1: [1-4] + - W2: [1-4] + - X3: [1-4] + - + - X1: [1,5-7] + - W3: [1-4] + - X4: [1,3-5] + - + - X5: [1,2] + - W4: [1,2] + - X4: [1,2] diff --git a/examples/ferrules.yml b/examples/ferrules.yml index 9fb8319..8a88f62 100644 --- a/examples/ferrules.yml +++ b/examples/ferrules.yml @@ -11,10 +11,11 @@ nodes: wires: W1: mm2: 0.25 + show_equiv: true length: 0.2 color_code: IEC num_wires: 10 - shield: true + type: bundle ferrules: F_test: @@ -25,9 +26,6 @@ connections: - X1: [1-3] - W1: [1-3] - X2: [1-3] - - - - X1: 4 - - W1: s - - F_test - W1: [4-10] diff --git a/src/wireviz.py b/src/wireviz.py index 40cc50e..f02899a 100644 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -15,7 +15,7 @@ color_hex = { 'RD': '#ff0000', 'OG': '#ff8000', 'YE': '#ffff00', - 'GN': '#009900', + 'GN': '#00ff00', 'TQ': '#00ffff', 'BU': '#0066ff', 'VT': '#8000ff', @@ -79,9 +79,17 @@ class Harness: dot.body.append('// Graph generated by WireViz') dot.body.append('// https://github.com/formatc1702/WireViz') font = 'arial' - dot.attr('graph', rankdir='LR', ranksep='2', bgcolor='transparent', fontname=font) - dot.attr('node', shape='record', style='rounded,filled', fillcolor='white', fontname=font) - dot.attr('edge', style='bold', fontname=font) + dot.attr('graph', rankdir='LR', + ranksep='2', + bgcolor='transparent', + nodesep='0.33', + fontname=font) + dot.attr('node', shape='record', + style='filled', + fillcolor='white', + fontname=font) + dot.attr('edge', style='bold', + fontname=font) # prepare ports on connectors depending on which side they will connect for k, c in self.cables.items(): @@ -147,9 +155,29 @@ class Harness: p[1].append('Shield') # l = label l = [c.name if c.show_name else '', a, p] - dot.node(k, label=nested(l)) + if c.type == 'bundle': + # create subgraph for wire bundle, add to main graph afterwards + bun = Graph(name='cluster_{}'.format(k)) + labeltext = ' | '.join(p for p in a if p) + '\n ' # newline to add space between label and wires + bun.attr('graph', label=labeltext, + style='filled, dashed', + fillcolor='white') + bun.attr('node', shape='point', + label='', + fixedsize='true', + width='0', height='0') + for i, x in enumerate(c.colors,1): + bun.node('{}_w{}l'.format(k,i)) + bun.node('{}_w{}r'.format(k,i)) + else: + dot.node(k, label=nested(l)) + + # add bundle subgraph to main graph + if c.type == 'bundle': + dot.subgraph(bun) # connections + existing_connections = [] # for bundles, avoid multiple edges between a bundle's wire's start and end node for x in c.connections: if isinstance(x[2], int): # check if it's an actual wire and not a shield search_color = c.colors[x[2]-1] @@ -159,14 +187,32 @@ class Harness: dot.attr('edge',color='#000000') else: # it's a shield connection dot.attr('edge',color='#000000') + + if c.type == 'bundle': + labeltext = '{sp}{color}'.format(color=translate_color(c.colors[x[2]-1], self.color_mode), sp=' ' * 35) + if x[2] not in existing_connections: + dot.edge('{via_name}_w{via_wire}l'.format(via_name=c.name, via_wire=x[2]), + '{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=x[2]), + taillabel=labeltext, + labelangle='60', + labeldist='0', + labelfloat='true') + existing_connections.append(x[2]) + if x[1] is not None: # connect to left - dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), - '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else '')) - # self.nodes[x[0]].ports_right = True + if c.type == 'bundle': + dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), + '{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=x[2])) + else: + dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), + '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else '')) if x[4] is not None: # connect to right - dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''), - '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) - # self.nodes[x[3]].ports_left = True + if c.type == 'bundle': + dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=x[2]), + '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) + else: + dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''), + '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) return dot @@ -206,6 +252,7 @@ class Node: @dataclass class Cable: name: str + type: str = None mm2: float = None awg: int = None show_equiv: bool = False diff --git a/src/yaml2wireviz.py b/src/yaml2wireviz.py index b922d4e..2275e3c 100644 --- a/src/yaml2wireviz.py +++ b/src/yaml2wireviz.py @@ -4,6 +4,7 @@ import wireviz filename = '../examples/example1.yml' filename = '../examples/example2.yml' filename = '../examples/ferrules.yml' +filename = '../examples/bundles.yml' def check_designators(what, where): for i, x in enumerate(what):